cm_t35.c 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il>
  4. *
  5. * Authors: Mike Rapoport <mike@compulab.co.il>
  6. * Igor Grinberg <grinberg@compulab.co.il>
  7. *
  8. * Derived from omap3evm and Beagle Board by
  9. * Manikandan Pillai <mani.pillai@ti.com>
  10. * Richard Woodruff <r-woodruff2@ti.com>
  11. * Syed Mohammed Khasim <x0khasim@ti.com>
  12. */
  13. #include <common.h>
  14. #include <env.h>
  15. #include <status_led.h>
  16. #include <netdev.h>
  17. #include <net.h>
  18. #include <i2c.h>
  19. #include <usb.h>
  20. #include <mmc.h>
  21. #include <splash.h>
  22. #include <twl4030.h>
  23. #include <linux/compiler.h>
  24. #include <asm/io.h>
  25. #include <linux/errno.h>
  26. #include <asm/arch/mem.h>
  27. #include <asm/arch/mux.h>
  28. #include <asm/arch/mmc_host_def.h>
  29. #include <asm/arch/sys_proto.h>
  30. #include <asm/mach-types.h>
  31. #include <asm/ehci-omap.h>
  32. #include <asm/gpio.h>
  33. #include "../common/common.h"
  34. #include "../common/eeprom.h"
  35. DECLARE_GLOBAL_DATA_PTR;
  36. const omap3_sysinfo sysinfo = {
  37. DDR_DISCRETE,
  38. "CM-T3x board",
  39. "NAND",
  40. };
  41. #ifdef CONFIG_SPL_BUILD
  42. /*
  43. * Routine: get_board_mem_timings
  44. * Description: If we use SPL then there is no x-loader nor config header
  45. * so we have to setup the DDR timings ourself on both banks.
  46. */
  47. void get_board_mem_timings(struct board_sdrc_timings *timings)
  48. {
  49. timings->mr = MICRON_V_MR_165;
  50. timings->mcfg = MICRON_V_MCFG_200(256 << 20); /* raswidth 14 needed */
  51. timings->ctrla = MICRON_V_ACTIMA_165;
  52. timings->ctrlb = MICRON_V_ACTIMB_165;
  53. timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
  54. }
  55. #endif
  56. struct splash_location splash_locations[] = {
  57. {
  58. .name = "nand",
  59. .storage = SPLASH_STORAGE_NAND,
  60. .flags = SPLASH_STORAGE_RAW,
  61. .offset = 0x100000,
  62. },
  63. };
  64. int splash_screen_prepare(void)
  65. {
  66. return splash_source_load(splash_locations,
  67. ARRAY_SIZE(splash_locations));
  68. }
  69. /*
  70. * Routine: board_init
  71. * Description: hardware init.
  72. */
  73. int board_init(void)
  74. {
  75. gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
  76. /* board id for Linux */
  77. if (get_cpu_family() == CPU_OMAP34XX)
  78. gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
  79. else
  80. gd->bd->bi_arch_number = MACH_TYPE_CM_T3730;
  81. /* boot param addr */
  82. gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  83. #if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
  84. status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
  85. #endif
  86. return 0;
  87. }
  88. /*
  89. * Routine: get_board_rev
  90. * Description: read system revision
  91. */
  92. u32 get_board_rev(void)
  93. {
  94. return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
  95. };
  96. int misc_init_r(void)
  97. {
  98. cl_print_pcb_info();
  99. omap_die_id_display();
  100. return 0;
  101. }
  102. /*
  103. * Routine: set_muxconf_regs
  104. * Description: Setting up the configuration Mux registers specific to the
  105. * hardware. Many pins need to be moved from protect to primary
  106. * mode.
  107. */
  108. static void cm_t3x_set_common_muxconf(void)
  109. {
  110. /* SDRC */
  111. MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/
  112. MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/
  113. MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/
  114. MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/
  115. MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/
  116. MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/
  117. MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/
  118. MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/
  119. MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/
  120. MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/
  121. MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/
  122. MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/
  123. MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/
  124. MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/
  125. MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/
  126. MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/
  127. MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/
  128. MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/
  129. MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/
  130. MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/
  131. MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/
  132. MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/
  133. MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/
  134. MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/
  135. MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/
  136. MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/
  137. MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/
  138. MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/
  139. MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/
  140. MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/
  141. MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/
  142. MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/
  143. MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/
  144. MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/
  145. MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/
  146. MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/
  147. MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/
  148. MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/
  149. MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/
  150. /* GPMC */
  151. MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/
  152. MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/
  153. MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/
  154. MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/
  155. MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/
  156. MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/
  157. MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/
  158. MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/
  159. MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/
  160. MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/
  161. MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/
  162. MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/
  163. MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/
  164. MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/
  165. MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/
  166. MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/
  167. MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/
  168. MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/
  169. MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/
  170. MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/
  171. MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/
  172. MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/
  173. MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/
  174. MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/
  175. MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/
  176. MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/
  177. MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/
  178. /* SB-T35 Ethernet */
  179. MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/
  180. /* DVI enable */
  181. MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/
  182. /* DataImage backlight */
  183. MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/
  184. /* CM-T3x Ethernet */
  185. MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
  186. MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/
  187. MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/
  188. MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*nOE*/
  189. MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*nWE*/
  190. MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*nBE0_CLE*/
  191. MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); /*GPIO_61*/
  192. MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*nWP*/
  193. MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*WAIT0*/
  194. /* DSS */
  195. MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/
  196. MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/
  197. MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/
  198. MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/
  199. MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/
  200. MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/
  201. MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/
  202. MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/
  203. MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/
  204. MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/
  205. MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/
  206. MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/
  207. MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/
  208. MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/
  209. MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/
  210. MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/
  211. /* serial interface */
  212. MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/
  213. MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX*/
  214. /* mUSB */
  215. MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/
  216. MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/
  217. MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/
  218. MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/
  219. MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/
  220. MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/
  221. MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/
  222. MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/
  223. MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/
  224. MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/
  225. MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/
  226. MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/
  227. /* USB EHCI */
  228. MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/
  229. MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/
  230. MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/
  231. MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/
  232. MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/
  233. MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/
  234. MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/
  235. MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/
  236. MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/
  237. MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/
  238. MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/
  239. MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/
  240. MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/
  241. MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/
  242. MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/
  243. MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/
  244. MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/
  245. MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/
  246. MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/
  247. MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/
  248. MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/
  249. MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/
  250. MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/
  251. MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
  252. /* SB_T35_USB_HUB_RESET_GPIO */
  253. MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)); /*GPIO_167*/
  254. /* I2C1 */
  255. MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/
  256. MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/
  257. /* I2C2 */
  258. MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/
  259. MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/
  260. /* I2C3 */
  261. MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/
  262. MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/
  263. /* control and debug */
  264. MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/
  265. MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/
  266. MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/
  267. MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/
  268. MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/
  269. MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/
  270. MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)); /*JTAG_NTRST*/
  271. MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/
  272. MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/
  273. MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/
  274. /* MMC1 */
  275. MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/
  276. MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/
  277. MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/
  278. MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/
  279. MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/
  280. MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/
  281. /* SPI */
  282. MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/
  283. MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/
  284. MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/
  285. MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/
  286. /* display controls */
  287. MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/
  288. }
  289. static void cm_t35_set_muxconf(void)
  290. {
  291. /* DSS */
  292. MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/
  293. MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/
  294. MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/
  295. MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/
  296. MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/
  297. MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/
  298. MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/
  299. MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/
  300. MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/
  301. MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/
  302. MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/
  303. MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/
  304. /* MMC1 */
  305. MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/
  306. MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/
  307. MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/
  308. MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/
  309. }
  310. static void cm_t3730_set_muxconf(void)
  311. {
  312. /* DSS */
  313. MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)); /*DSS_DATA0*/
  314. MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)); /*DSS_DATA1*/
  315. MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)); /*DSS_DATA2*/
  316. MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)); /*DSS_DATA3*/
  317. MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)); /*DSS_DATA4*/
  318. MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)); /*DSS_DATA5*/
  319. MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)); /*DSS_DATA18*/
  320. MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)); /*DSS_DATA19*/
  321. MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)); /*DSS_DATA20*/
  322. MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)); /*DSS_DATA21*/
  323. MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)); /*DSS_DATA22*/
  324. MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)); /*DSS_DATA23*/
  325. }
  326. void set_muxconf_regs(void)
  327. {
  328. cm_t3x_set_common_muxconf();
  329. if (get_cpu_family() == CPU_OMAP34XX)
  330. cm_t35_set_muxconf();
  331. else
  332. cm_t3730_set_muxconf();
  333. }
  334. #if defined(CONFIG_MMC)
  335. #define SB_T35_WP_GPIO 59
  336. int board_mmc_getcd(struct mmc *mmc)
  337. {
  338. u8 val;
  339. if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO, &val))
  340. return -1;
  341. return !(val & 1);
  342. }
  343. int board_mmc_init(bd_t *bis)
  344. {
  345. return omap_mmc_init(0, 0, 0, -1, SB_T35_WP_GPIO);
  346. }
  347. #endif
  348. #if defined(CONFIG_MMC)
  349. void board_mmc_power_init(void)
  350. {
  351. twl4030_power_mmc_init(0);
  352. }
  353. #endif
  354. #ifdef CONFIG_SYS_I2C_OMAP24XX
  355. /*
  356. * Routine: reset_net_chip
  357. * Description: reset the Ethernet controller via TPS65930 GPIO
  358. */
  359. static int cm_t3x_reset_net_chip(int gpio)
  360. {
  361. /* Set GPIO1 of TPS65930 as output */
  362. twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03,
  363. 0x02);
  364. /* Send a pulse on the GPIO pin */
  365. twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C,
  366. 0x02);
  367. udelay(1);
  368. twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x09,
  369. 0x02);
  370. mdelay(40);
  371. twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C,
  372. 0x02);
  373. mdelay(1);
  374. return 0;
  375. }
  376. #else
  377. static inline int cm_t3x_reset_net_chip(int gpio) { return 0; }
  378. #endif
  379. #ifdef CONFIG_SMC911X
  380. /*
  381. * Routine: handle_mac_address
  382. * Description: prepare MAC address for on-board Ethernet.
  383. */
  384. static int handle_mac_address(void)
  385. {
  386. unsigned char enetaddr[6];
  387. int rc;
  388. rc = eth_env_get_enetaddr("ethaddr", enetaddr);
  389. if (rc)
  390. return 0;
  391. rc = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS);
  392. if (rc)
  393. return rc;
  394. if (!is_valid_ethaddr(enetaddr))
  395. return -1;
  396. return eth_env_set_enetaddr("ethaddr", enetaddr);
  397. }
  398. /*
  399. * Routine: board_eth_init
  400. * Description: initialize module and base-board Ethernet chips
  401. */
  402. #define SB_T35_SMC911X_BASE (CONFIG_SMC911X_BASE + SZ_16M)
  403. int board_eth_init(bd_t *bis)
  404. {
  405. int rc = 0, rc1 = 0;
  406. rc1 = handle_mac_address();
  407. if (rc1)
  408. printf("No MAC address found! ");
  409. rc1 = cl_omap3_smc911x_init(0, 5, CONFIG_SMC911X_BASE,
  410. cm_t3x_reset_net_chip, -EINVAL);
  411. if (rc1 > 0)
  412. rc++;
  413. rc1 = cl_omap3_smc911x_init(1, 4, SB_T35_SMC911X_BASE, NULL, -EINVAL);
  414. if (rc1 > 0)
  415. rc++;
  416. return rc;
  417. }
  418. #endif
  419. #ifdef CONFIG_USB_EHCI_OMAP
  420. struct omap_usbhs_board_data usbhs_bdata = {
  421. .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
  422. .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
  423. .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
  424. };
  425. #define SB_T35_USB_HUB_RESET_GPIO 167
  426. int ehci_hcd_init(int index, enum usb_init_type init,
  427. struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  428. {
  429. u8 val;
  430. int offset;
  431. cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst");
  432. offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1;
  433. twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val);
  434. /* Set GPIO6 and GPIO7 of TPS65930 as output */
  435. val |= 0xC0;
  436. twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, val);
  437. offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1;
  438. /* Take both PHYs out of reset */
  439. twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, 0xC0);
  440. udelay(1);
  441. return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
  442. }
  443. int ehci_hcd_stop(void)
  444. {
  445. cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO);
  446. return omap_ehci_hcd_stop();
  447. }
  448. #endif /* CONFIG_USB_EHCI_OMAP */