cm_t335.c 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Board functions for Compulab CM-T335 board
  4. *
  5. * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
  6. *
  7. * Author: Ilya Ledvich <ilya@compulab.co.il>
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <errno.h>
  12. #include <miiphy.h>
  13. #include <cpsw.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <asm/arch/hardware_am33xx.h>
  16. #include <asm/io.h>
  17. #include <asm/gpio.h>
  18. #include "../common/eeprom.h"
  19. DECLARE_GLOBAL_DATA_PTR;
  20. /*
  21. * Basic board specific setup. Pinmux has been handled already.
  22. */
  23. int board_init(void)
  24. {
  25. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  26. gpmc_init();
  27. #if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
  28. status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_OFF);
  29. #endif
  30. return 0;
  31. }
  32. #if defined (CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)
  33. static void cpsw_control(int enabled)
  34. {
  35. /* VTP can be added here */
  36. return;
  37. }
  38. static struct cpsw_slave_data cpsw_slave = {
  39. .slave_reg_ofs = 0x208,
  40. .sliver_reg_ofs = 0xd80,
  41. .phy_addr = 0,
  42. .phy_if = PHY_INTERFACE_MODE_RGMII,
  43. };
  44. static struct cpsw_platform_data cpsw_data = {
  45. .mdio_base = CPSW_MDIO_BASE,
  46. .cpsw_base = CPSW_BASE,
  47. .mdio_div = 0xff,
  48. .channels = 8,
  49. .cpdma_reg_ofs = 0x800,
  50. .slaves = 1,
  51. .slave_data = &cpsw_slave,
  52. .ale_reg_ofs = 0xd00,
  53. .ale_entries = 1024,
  54. .host_port_reg_ofs = 0x108,
  55. .hw_stats_reg_ofs = 0x900,
  56. .bd_ram_ofs = 0x2000,
  57. .mac_control = (1 << 5),
  58. .control = cpsw_control,
  59. .host_port_num = 0,
  60. .version = CPSW_CTRL_VERSION_2,
  61. };
  62. /* PHY reset GPIO */
  63. #define GPIO_PHY_RST GPIO_PIN(3, 7)
  64. static void board_phy_init(void)
  65. {
  66. gpio_request(GPIO_PHY_RST, "phy_rst");
  67. gpio_direction_output(GPIO_PHY_RST, 0);
  68. mdelay(2);
  69. gpio_set_value(GPIO_PHY_RST, 1);
  70. mdelay(2);
  71. }
  72. static void get_efuse_mac_addr(uchar *enetaddr)
  73. {
  74. uint32_t mac_hi, mac_lo;
  75. struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  76. mac_lo = readl(&cdev->macid0l);
  77. mac_hi = readl(&cdev->macid0h);
  78. enetaddr[0] = mac_hi & 0xFF;
  79. enetaddr[1] = (mac_hi & 0xFF00) >> 8;
  80. enetaddr[2] = (mac_hi & 0xFF0000) >> 16;
  81. enetaddr[3] = (mac_hi & 0xFF000000) >> 24;
  82. enetaddr[4] = mac_lo & 0xFF;
  83. enetaddr[5] = (mac_lo & 0xFF00) >> 8;
  84. }
  85. /*
  86. * Routine: handle_mac_address
  87. * Description: prepare MAC address for on-board Ethernet.
  88. */
  89. static int handle_mac_address(void)
  90. {
  91. uchar enetaddr[6];
  92. int rv;
  93. rv = eth_env_get_enetaddr("ethaddr", enetaddr);
  94. if (rv)
  95. return 0;
  96. rv = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS);
  97. if (rv)
  98. get_efuse_mac_addr(enetaddr);
  99. if (!is_valid_ethaddr(enetaddr))
  100. return -1;
  101. return eth_env_set_enetaddr("ethaddr", enetaddr);
  102. }
  103. #define AR8051_PHY_DEBUG_ADDR_REG 0x1d
  104. #define AR8051_PHY_DEBUG_DATA_REG 0x1e
  105. #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
  106. #define AR8051_RGMII_TX_CLK_DLY 0x100
  107. int board_eth_init(bd_t *bis)
  108. {
  109. int rv, n = 0;
  110. const char *devname;
  111. struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  112. rv = handle_mac_address();
  113. if (rv)
  114. printf("No MAC address found!\n");
  115. writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
  116. board_phy_init();
  117. rv = cpsw_register(&cpsw_data);
  118. if (rv < 0)
  119. printf("Error %d registering CPSW switch\n", rv);
  120. else
  121. n += rv;
  122. /*
  123. * CPSW RGMII Internal Delay Mode is not supported in all PVT
  124. * operating points. So we must set the TX clock delay feature
  125. * in the AR8051 PHY. Since we only support a single ethernet
  126. * device, we only do this for the first instance.
  127. */
  128. devname = miiphy_get_current_dev();
  129. miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
  130. AR8051_DEBUG_RGMII_CLK_DLY_REG);
  131. miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
  132. AR8051_RGMII_TX_CLK_DLY);
  133. return n;
  134. }
  135. #endif /* CONFIG_DRIVER_TI_CPSW && !CONFIG_SPL_BUILD */