cl-som-imx7.c 7.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * U-Boot board functions for CompuLab CL-SOM-iMX7 module
  4. *
  5. * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
  6. *
  7. * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <mmc.h>
  12. #include <phy.h>
  13. #include <netdev.h>
  14. #include <fsl_esdhc_imx.h>
  15. #include <power/pmic.h>
  16. #include <power/pfuze3000_pmic.h>
  17. #include <asm/mach-imx/mxc_i2c.h>
  18. #include <asm/mach-imx/iomux-v3.h>
  19. #include <asm/arch-mx7/mx7-pins.h>
  20. #include <asm/arch-mx7/sys_proto.h>
  21. #include <asm/arch-mx7/clock.h>
  22. #include "../common/eeprom.h"
  23. #include "common.h"
  24. DECLARE_GLOBAL_DATA_PTR;
  25. #ifdef CONFIG_SYS_I2C_MXC
  26. #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  27. PAD_CTL_HYS)
  28. #define CL_SOM_IMX7_GPIO_I2C2_SCL IMX_GPIO_NR(1, 6)
  29. #define CL_SOM_IMX7_GPIO_I2C2_SDA IMX_GPIO_NR(1, 7)
  30. static struct i2c_pads_info cl_som_imx7_i2c_pad_info2 = {
  31. .scl = {
  32. .i2c_mode = MX7D_PAD_GPIO1_IO06__I2C2_SCL |
  33. MUX_PAD_CTRL(I2C_PAD_CTRL),
  34. .gpio_mode = MX7D_PAD_GPIO1_IO06__GPIO1_IO6 |
  35. MUX_PAD_CTRL(I2C_PAD_CTRL),
  36. .gp = CL_SOM_IMX7_GPIO_I2C2_SCL,
  37. },
  38. .sda = {
  39. .i2c_mode = MX7D_PAD_GPIO1_IO07__I2C2_SDA |
  40. MUX_PAD_CTRL(I2C_PAD_CTRL),
  41. .gpio_mode = MX7D_PAD_GPIO1_IO07__GPIO1_IO7 |
  42. MUX_PAD_CTRL(I2C_PAD_CTRL),
  43. .gp = CL_SOM_IMX7_GPIO_I2C2_SDA,
  44. },
  45. };
  46. /*
  47. * cl_som_imx7_setup_i2c() - I2C pinmux configuration.
  48. */
  49. static void cl_som_imx7_setup_i2c(void)
  50. {
  51. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &cl_som_imx7_i2c_pad_info2);
  52. }
  53. #else /* !CONFIG_SYS_I2C_MXC */
  54. static void cl_som_imx7_setup_i2c(void) {}
  55. #endif /* CONFIG_SYS_I2C_MXC */
  56. int dram_init(void)
  57. {
  58. gd->ram_size = imx_ddr_size();
  59. return 0;
  60. }
  61. #ifdef CONFIG_FSL_ESDHC_IMX
  62. #define CL_SOM_IMX7_GPIO_USDHC3_PWR IMX_GPIO_NR(6, 11)
  63. static struct fsl_esdhc_cfg cl_som_imx7_usdhc_cfg[3] = {
  64. {USDHC1_BASE_ADDR, 0, 4},
  65. {USDHC3_BASE_ADDR},
  66. };
  67. int board_mmc_init(bd_t *bis)
  68. {
  69. int i, ret;
  70. /*
  71. * According to the board_mmc_init() the following map is done:
  72. * (U-boot device node) (Physical Port)
  73. * mmc0 USDHC1
  74. * mmc2 USDHC3 (eMMC)
  75. */
  76. for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  77. switch (i) {
  78. case 0:
  79. cl_som_imx7_usdhc1_pads_set();
  80. gpio_request(CL_SOM_IMX7_GPIO_USDHC1_CD, "usdhc1_cd");
  81. cl_som_imx7_usdhc_cfg[0].sdhc_clk =
  82. mxc_get_clock(MXC_ESDHC_CLK);
  83. break;
  84. case 1:
  85. cl_som_imx7_usdhc3_emmc_pads_set();
  86. gpio_request(CL_SOM_IMX7_GPIO_USDHC3_PWR, "usdhc3_pwr");
  87. gpio_direction_output(CL_SOM_IMX7_GPIO_USDHC3_PWR, 0);
  88. udelay(500);
  89. gpio_direction_output(CL_SOM_IMX7_GPIO_USDHC3_PWR, 1);
  90. cl_som_imx7_usdhc_cfg[1].sdhc_clk =
  91. mxc_get_clock(MXC_ESDHC3_CLK);
  92. break;
  93. default:
  94. printf("Warning: you configured more USDHC controllers "
  95. "(%d) than supported by the board\n", i + 1);
  96. return -EINVAL;
  97. }
  98. ret = fsl_esdhc_initialize(bis, &cl_som_imx7_usdhc_cfg[i]);
  99. if (ret)
  100. return ret;
  101. }
  102. return 0;
  103. }
  104. #endif /* CONFIG_FSL_ESDHC_IMX */
  105. #ifdef CONFIG_FEC_MXC
  106. #define CL_SOM_IMX7_ETH1_PHY_NRST IMX_GPIO_NR(1, 4)
  107. /*
  108. * cl_som_imx7_rgmii_rework() - Ethernet PHY configuration.
  109. */
  110. static void cl_som_imx7_rgmii_rework(struct phy_device *phydev)
  111. {
  112. unsigned short val;
  113. /* Ar8031 phy SmartEEE feature cause link status generates glitch,
  114. * which cause ethernet link down/up issue, so disable SmartEEE
  115. */
  116. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
  117. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
  118. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
  119. val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  120. val &= ~(0x1 << 8);
  121. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  122. /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
  123. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  124. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  125. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  126. val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  127. val &= 0xffe3;
  128. val |= 0x18;
  129. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  130. /* introduce tx clock delay */
  131. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  132. val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  133. val |= 0x0100;
  134. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  135. }
  136. int board_phy_config(struct phy_device *phydev)
  137. {
  138. cl_som_imx7_rgmii_rework(phydev);
  139. if (phydev->drv->config)
  140. phydev->drv->config(phydev);
  141. return 0;
  142. }
  143. /*
  144. * cl_som_imx7_handle_mac_address() - set Ethernet MAC address environment.
  145. *
  146. * @env_var: MAC address environment variable
  147. * @eeprom_bus: I2C bus of the environment EEPROM
  148. *
  149. * @return: 0 on success, < 0 on failure
  150. */
  151. static int cl_som_imx7_handle_mac_address(char *env_var, uint eeprom_bus)
  152. {
  153. int ret;
  154. unsigned char enetaddr[6];
  155. ret = eth_env_get_enetaddr(env_var, enetaddr);
  156. if (ret)
  157. return 0;
  158. ret = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
  159. if (ret)
  160. return ret;
  161. ret = is_valid_ethaddr(enetaddr);
  162. if (!ret)
  163. return -1;
  164. return eth_env_set_enetaddr(env_var, enetaddr);
  165. }
  166. #define CL_SOM_IMX7_FEC_DEV_ID_PRI 0
  167. int board_eth_init(bd_t *bis)
  168. {
  169. /* set Ethernet MAC address environment */
  170. cl_som_imx7_handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS);
  171. /* Ethernet interface pinmux configuration */
  172. cl_som_imx7_phy1_rst_pads_set();
  173. cl_som_imx7_fec1_pads_set();
  174. /* PHY reset */
  175. gpio_request(CL_SOM_IMX7_ETH1_PHY_NRST, "eth1_phy_nrst");
  176. gpio_direction_output(CL_SOM_IMX7_ETH1_PHY_NRST, 0);
  177. mdelay(10);
  178. gpio_set_value(CL_SOM_IMX7_ETH1_PHY_NRST, 1);
  179. /* MAC initialization */
  180. return fecmxc_initialize_multi(bis, CL_SOM_IMX7_FEC_DEV_ID_PRI,
  181. CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
  182. }
  183. /*
  184. * cl_som_imx7_setup_fec() - Ethernet MAC 1 clock configuration.
  185. * - ENET1 reference clock mode select.
  186. * - ENET1_TX_CLK output driver is disabled when configured for ALT1.
  187. */
  188. static void cl_som_imx7_setup_fec(void)
  189. {
  190. struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
  191. = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  192. /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
  193. clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
  194. (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
  195. IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
  196. set_clk_enet(ENET_125MHZ);
  197. }
  198. #else /* !CONFIG_FEC_MXC */
  199. static void cl_som_imx7_setup_fec(void) {}
  200. #endif /* CONFIG_FEC_MXC */
  201. #ifdef CONFIG_SPI
  202. static void cl_som_imx7_spi_init(void)
  203. {
  204. cl_som_imx7_espi1_pads_set();
  205. }
  206. #else /* !CONFIG_SPI */
  207. static void cl_som_imx7_spi_init(void) {}
  208. #endif /* CONFIG_SPI */
  209. int board_early_init_f(void)
  210. {
  211. cl_som_imx7_uart1_pads_set();
  212. cl_som_imx7_usb_otg1_pads_set();
  213. return 0;
  214. }
  215. int board_init(void)
  216. {
  217. /* address of boot parameters */
  218. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  219. cl_som_imx7_setup_i2c();
  220. cl_som_imx7_setup_fec();
  221. cl_som_imx7_spi_init();
  222. return 0;
  223. }
  224. #ifdef CONFIG_POWER
  225. #define I2C_PMIC 0
  226. int power_init_board(void)
  227. {
  228. struct pmic *p;
  229. int ret;
  230. unsigned int reg, rev_id;
  231. ret = power_pfuze3000_init(I2C_PMIC);
  232. if (ret)
  233. return ret;
  234. p = pmic_get("PFUZE3000");
  235. ret = pmic_probe(p);
  236. if (ret)
  237. return ret;
  238. pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
  239. pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
  240. printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
  241. /* disable Low Power Mode during standby mode */
  242. pmic_reg_write(p, PFUZE3000_LDOGCTL, 0x1);
  243. return 0;
  244. }
  245. #endif /* CONFIG_POWER */
  246. /*
  247. * cl_som_imx7_setup_wdog() - watchdog configuration.
  248. * - Output WDOG_B signal to reset external pmic.
  249. * - Suspend the watchdog timer during low-power modes.
  250. */
  251. void cl_som_imx7_setup_wdog(void)
  252. {
  253. struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  254. cl_som_imx7_wdog_pads_set();
  255. set_wdog_reset(wdog);
  256. /*
  257. * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
  258. * since we use PMIC_PWRON to reset the board.
  259. */
  260. clrsetbits_le16(&wdog->wcr, 0, 0x10);
  261. }
  262. int board_late_init(void)
  263. {
  264. env_set("board_name", "CL-SOM-iMX7");
  265. cl_som_imx7_setup_wdog();
  266. return 0;
  267. }
  268. int checkboard(void)
  269. {
  270. char *mode;
  271. if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
  272. mode = "secure";
  273. else
  274. mode = "non-secure";
  275. printf("Board: CL-SOM-iMX7 in %s mode\n", mode);
  276. return 0;
  277. }