board.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * (C) Copyright 2016
  6. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  7. *
  8. * Based on:
  9. * Board functions for TI AM335X based boards
  10. *
  11. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  12. */
  13. #include <common.h>
  14. #include <env.h>
  15. #include <errno.h>
  16. #include <spl.h>
  17. #include <asm/arch/cpu.h>
  18. #include <asm/arch/hardware.h>
  19. #include <asm/arch/omap.h>
  20. #include <asm/arch/ddr_defs.h>
  21. #include <asm/arch/clock.h>
  22. #include <asm/arch/gpio.h>
  23. #include <asm/arch/mmc_host_def.h>
  24. #include <asm/arch/sys_proto.h>
  25. #include <asm/arch/mem.h>
  26. #include <asm/io.h>
  27. #include <asm/emif.h>
  28. #include <asm/gpio.h>
  29. #include <i2c.h>
  30. #include <miiphy.h>
  31. #include <cpsw.h>
  32. #include <power/tps65217.h>
  33. #include <environment.h>
  34. #include <watchdog.h>
  35. #include "mmc.h"
  36. #include "board.h"
  37. DECLARE_GLOBAL_DATA_PTR;
  38. static struct shc_eeprom __attribute__((section(".data"))) header;
  39. static int shc_eeprom_valid;
  40. /*
  41. * Read header information from EEPROM into global structure.
  42. */
  43. static int read_eeprom(void)
  44. {
  45. /* Check if baseboard eeprom is available */
  46. if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  47. puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
  48. return -ENODEV;
  49. }
  50. /* read the eeprom using i2c */
  51. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
  52. sizeof(header))) {
  53. puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n");
  54. return -EIO;
  55. }
  56. if (header.magic != HDR_MAGIC) {
  57. printf("Incorrect magic number (0x%x) in EEPROM\n",
  58. header.magic);
  59. return -EIO;
  60. }
  61. shc_eeprom_valid = 1;
  62. return 0;
  63. }
  64. static void shc_request_gpio(void)
  65. {
  66. gpio_request(LED_PWR_BL_GPIO, "LED PWR BL");
  67. gpio_request(LED_PWR_RD_GPIO, "LED PWR RD");
  68. gpio_request(RESET_GPIO, "reset");
  69. gpio_request(WIFI_REGEN_GPIO, "WIFI REGEN");
  70. gpio_request(WIFI_RST_GPIO, "WIFI rst");
  71. gpio_request(ZIGBEE_RST_GPIO, "ZigBee rst");
  72. gpio_request(BIDCOS_RST_GPIO, "BIDCOS rst");
  73. gpio_request(ENOC_RST_GPIO, "ENOC rst");
  74. #if defined CONFIG_B_SAMPLE
  75. gpio_request(LED_PWR_GN_GPIO, "LED PWR GN");
  76. gpio_request(LED_CONN_BL_GPIO, "LED CONN BL");
  77. gpio_request(LED_CONN_RD_GPIO, "LED CONN RD");
  78. gpio_request(LED_CONN_GN_GPIO, "LED CONN GN");
  79. #else
  80. gpio_request(LED_LAN_BL_GPIO, "LED LAN BL");
  81. gpio_request(LED_LAN_RD_GPIO, "LED LAN RD");
  82. gpio_request(LED_CLOUD_BL_GPIO, "LED CLOUD BL");
  83. gpio_request(LED_CLOUD_RD_GPIO, "LED CLOUD RD");
  84. gpio_request(LED_PWM_GPIO, "LED PWM");
  85. gpio_request(Z_WAVE_RST_GPIO, "Z WAVE rst");
  86. #endif
  87. gpio_request(BACK_BUTTON_GPIO, "Back button");
  88. gpio_request(FRONT_BUTTON_GPIO, "Front button");
  89. }
  90. /*
  91. * Function which forces all installed modules into running state for ICT
  92. * testing. Called by SPL.
  93. */
  94. static void __maybe_unused force_modules_running(void)
  95. {
  96. /* Wi-Fi power regulator enable - high = enabled */
  97. gpio_direction_output(WIFI_REGEN_GPIO, 1);
  98. /*
  99. * Wait for Wi-Fi power regulator to reach a stable voltage
  100. * (soft-start time, max. 350 µs)
  101. */
  102. __udelay(350);
  103. /* Wi-Fi module reset - high = running */
  104. gpio_direction_output(WIFI_RST_GPIO, 1);
  105. /* ZigBee reset - high = running */
  106. gpio_direction_output(ZIGBEE_RST_GPIO, 1);
  107. /* BidCos reset - high = running */
  108. gpio_direction_output(BIDCOS_RST_GPIO, 1);
  109. #if !defined(CONFIG_B_SAMPLE)
  110. /* Z-Wave reset - high = running */
  111. gpio_direction_output(Z_WAVE_RST_GPIO, 1);
  112. #endif
  113. /* EnOcean reset - low = running */
  114. gpio_direction_output(ENOC_RST_GPIO, 0);
  115. }
  116. /*
  117. * Function which forces all installed modules into reset - to be released by
  118. * the OS, called by SPL
  119. */
  120. static void __maybe_unused force_modules_reset(void)
  121. {
  122. /* Wi-Fi module reset - low = reset */
  123. gpio_direction_output(WIFI_RST_GPIO, 0);
  124. /* Wi-Fi power regulator enable - low = disabled */
  125. gpio_direction_output(WIFI_REGEN_GPIO, 0);
  126. /* ZigBee reset - low = reset */
  127. gpio_direction_output(ZIGBEE_RST_GPIO, 0);
  128. /* BidCos reset - low = reset */
  129. /*gpio_direction_output(BIDCOS_RST_GPIO, 0);*/
  130. #if !defined(CONFIG_B_SAMPLE)
  131. /* Z-Wave reset - low = reset */
  132. gpio_direction_output(Z_WAVE_RST_GPIO, 0);
  133. #endif
  134. /* EnOcean reset - high = reset*/
  135. gpio_direction_output(ENOC_RST_GPIO, 1);
  136. }
  137. /*
  138. * Function to set the LEDs in the state "Bootloader booting"
  139. */
  140. static void __maybe_unused leds_set_booting(void)
  141. {
  142. #if defined(CONFIG_B_SAMPLE)
  143. /* Turn all red LEDs on */
  144. gpio_direction_output(LED_PWR_RD_GPIO, 1);
  145. gpio_direction_output(LED_CONN_RD_GPIO, 1);
  146. #else /* All other SHCs starting with B2-Sample */
  147. /* Set the PWM GPIO */
  148. gpio_direction_output(LED_PWM_GPIO, 1);
  149. /* Turn all red LEDs on */
  150. gpio_direction_output(LED_PWR_RD_GPIO, 1);
  151. gpio_direction_output(LED_LAN_RD_GPIO, 1);
  152. gpio_direction_output(LED_CLOUD_RD_GPIO, 1);
  153. #endif
  154. }
  155. /*
  156. * Function to set the LEDs in the state "Bootloader error"
  157. */
  158. static void leds_set_failure(int state)
  159. {
  160. #if defined(CONFIG_B_SAMPLE)
  161. /* Turn all blue and green LEDs off */
  162. gpio_set_value(LED_PWR_BL_GPIO, 0);
  163. gpio_set_value(LED_PWR_GN_GPIO, 0);
  164. gpio_set_value(LED_CONN_BL_GPIO, 0);
  165. gpio_set_value(LED_CONN_GN_GPIO, 0);
  166. /* Turn all red LEDs to 'state' */
  167. gpio_set_value(LED_PWR_RD_GPIO, state);
  168. gpio_set_value(LED_CONN_RD_GPIO, state);
  169. #else /* All other SHCs starting with B2-Sample */
  170. /* Set the PWM GPIO */
  171. gpio_direction_output(LED_PWM_GPIO, 1);
  172. /* Turn all blue LEDs off */
  173. gpio_set_value(LED_PWR_BL_GPIO, 0);
  174. gpio_set_value(LED_LAN_BL_GPIO, 0);
  175. gpio_set_value(LED_CLOUD_BL_GPIO, 0);
  176. /* Turn all red LEDs to 'state' */
  177. gpio_set_value(LED_PWR_RD_GPIO, state);
  178. gpio_set_value(LED_LAN_RD_GPIO, state);
  179. gpio_set_value(LED_CLOUD_RD_GPIO, state);
  180. #endif
  181. }
  182. /*
  183. * Function to set the LEDs in the state "Bootloader finished"
  184. */
  185. static void leds_set_finish(void)
  186. {
  187. #if defined(CONFIG_B_SAMPLE)
  188. /* Turn all LEDs off */
  189. gpio_set_value(LED_PWR_BL_GPIO, 0);
  190. gpio_set_value(LED_PWR_RD_GPIO, 0);
  191. gpio_set_value(LED_PWR_GN_GPIO, 0);
  192. gpio_set_value(LED_CONN_BL_GPIO, 0);
  193. gpio_set_value(LED_CONN_RD_GPIO, 0);
  194. gpio_set_value(LED_CONN_GN_GPIO, 0);
  195. #else /* All other SHCs starting with B2-Sample */
  196. /* Turn all LEDs off */
  197. gpio_set_value(LED_PWR_BL_GPIO, 0);
  198. gpio_set_value(LED_PWR_RD_GPIO, 0);
  199. gpio_set_value(LED_LAN_BL_GPIO, 0);
  200. gpio_set_value(LED_LAN_RD_GPIO, 0);
  201. gpio_set_value(LED_CLOUD_BL_GPIO, 0);
  202. gpio_set_value(LED_CLOUD_RD_GPIO, 0);
  203. /* Turn off the PWM GPIO and mux it to EHRPWM */
  204. gpio_set_value(LED_PWM_GPIO, 0);
  205. enable_shc_board_pwm_pin_mux();
  206. #endif
  207. }
  208. static void check_button_status(void)
  209. {
  210. ulong value;
  211. gpio_direction_input(FRONT_BUTTON_GPIO);
  212. value = gpio_get_value(FRONT_BUTTON_GPIO);
  213. if (value == 0) {
  214. printf("front button activated !\n");
  215. env_set("harakiri", "1");
  216. }
  217. }
  218. #if defined(CONFIG_SPL_BUILD)
  219. #ifdef CONFIG_SPL_OS_BOOT
  220. int spl_start_uboot(void)
  221. {
  222. return 1;
  223. }
  224. #endif
  225. static void shc_board_early_init(void)
  226. {
  227. shc_request_gpio();
  228. # ifdef CONFIG_SHC_ICT
  229. /* Force all modules into enabled state for ICT testing */
  230. force_modules_running();
  231. # else
  232. /* Force all modules to enter Reset state until released by the OS */
  233. force_modules_reset();
  234. # endif
  235. leds_set_booting();
  236. }
  237. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  238. #define MPU_SPREADING_PERMILLE 18 /* Spread 1.8 percent */
  239. #define OSC (V_OSCK/1000000)
  240. /* Bosch: Predivider must be fixed to 4, so N = 4-1 */
  241. #define MPUPLL_N (4-1)
  242. /* Bosch: Fref = 24 MHz / (N+1) = 24 MHz / 4 = 6 MHz */
  243. #define MPUPLL_FREF (OSC / (MPUPLL_N + 1))
  244. const struct dpll_params dpll_ddr_shc = {
  245. 400, OSC-1, 1, -1, -1, -1, -1};
  246. const struct dpll_params *get_dpll_ddr_params(void)
  247. {
  248. return &dpll_ddr_shc;
  249. }
  250. /*
  251. * As we enabled downspread SSC with 1.8%, the values needed to be corrected
  252. * such that the 20% overshoot will not lead to too high frequencies.
  253. * In all cases, this is achieved by subtracting one from M (6 MHz less).
  254. * Example: 600 MHz CPU
  255. * Step size: 24 MHz OSC, N = 4 (fix) --> Fref = 6 MHz
  256. * 600 MHz - 6 MHz (1x Fref) = 594 MHz
  257. * SSC: 594 MHz * 1.8% = 10.7 MHz SSC
  258. * Overshoot: 10.7 MHz * 20 % = 2.2 MHz
  259. * --> Fmax = 594 MHz + 2.2 MHz = 596.2 MHz, lower than 600 MHz --> OK!
  260. */
  261. const struct dpll_params dpll_mpu_shc_opp100 = {
  262. 99, MPUPLL_N, 1, -1, -1, -1, -1};
  263. void am33xx_spl_board_init(void)
  264. {
  265. int sil_rev;
  266. int mpu_vdd;
  267. puts(BOARD_ID_STR);
  268. /*
  269. * Set CORE Frequency to OPP100
  270. * Hint: DCDC3 (CORE) defaults to 1.100V (for OPP100)
  271. */
  272. do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  273. sil_rev = readl(&cdev->deviceid) >> 28;
  274. if (sil_rev < 2) {
  275. puts("We do not support Silicon Revisions below 2.0!\n");
  276. return;
  277. }
  278. dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  279. if (i2c_probe(TPS65217_CHIP_PM))
  280. return;
  281. /*
  282. * Retrieve the CPU max frequency by reading the efuse
  283. * SHC-Default: 600 MHz
  284. */
  285. switch (dpll_mpu_opp100.m) {
  286. case MPUPLL_M_1000:
  287. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
  288. break;
  289. case MPUPLL_M_800:
  290. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
  291. break;
  292. case MPUPLL_M_720:
  293. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
  294. break;
  295. case MPUPLL_M_600:
  296. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
  297. break;
  298. case MPUPLL_M_300:
  299. mpu_vdd = TPS65217_DCDC_VOLT_SEL_950MV;
  300. break;
  301. default:
  302. puts("Cannot determine the frequency, failing!\n");
  303. return;
  304. }
  305. if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
  306. puts("tps65217_voltage_update failure\n");
  307. return;
  308. }
  309. /* Set MPU Frequency to what we detected */
  310. printf("MPU reference clock runs at %d MHz\n", MPUPLL_FREF);
  311. printf("Setting MPU clock to %d MHz\n", MPUPLL_FREF *
  312. dpll_mpu_shc_opp100.m);
  313. do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_shc_opp100);
  314. /* Enable Spread Spectrum for this freq to be clean on EMI side */
  315. set_mpu_spreadspectrum(MPU_SPREADING_PERMILLE);
  316. /*
  317. * Using the default voltages for the PMIC (TPS65217D)
  318. * LS1 = 1.8V (VDD_1V8)
  319. * LS2 = 3.3V (VDD_3V3A)
  320. * LDO1 = 1.8V (VIO and VRTC)
  321. * LDO2 = 3.3V (VDD_3V3AUX)
  322. */
  323. shc_board_early_init();
  324. }
  325. void set_uart_mux_conf(void)
  326. {
  327. enable_uart0_pin_mux();
  328. }
  329. void set_mux_conf_regs(void)
  330. {
  331. enable_shc_board_pin_mux();
  332. }
  333. const struct ctrl_ioregs ioregs_evmsk = {
  334. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  335. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  336. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  337. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  338. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  339. };
  340. static const struct ddr_data ddr3_shc_data = {
  341. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  342. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  343. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  344. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  345. };
  346. static const struct cmd_control ddr3_shc_cmd_ctrl_data = {
  347. .cmd0csratio = MT41K256M16HA125E_RATIO,
  348. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  349. .cmd1csratio = MT41K256M16HA125E_RATIO,
  350. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  351. .cmd2csratio = MT41K256M16HA125E_RATIO,
  352. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  353. };
  354. static struct emif_regs ddr3_shc_emif_reg_data = {
  355. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  356. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  357. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  358. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  359. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  360. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  361. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
  362. PHY_EN_DYN_PWRDN,
  363. };
  364. void sdram_init(void)
  365. {
  366. /* Configure the DDR3 RAM */
  367. config_ddr(400, &ioregs_evmsk, &ddr3_shc_data,
  368. &ddr3_shc_cmd_ctrl_data, &ddr3_shc_emif_reg_data, 0);
  369. }
  370. #endif
  371. /*
  372. * Basic board specific setup. Pinmux has been handled already.
  373. */
  374. int board_init(void)
  375. {
  376. #if defined(CONFIG_HW_WATCHDOG)
  377. hw_watchdog_init();
  378. #endif
  379. i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  380. if (read_eeprom() < 0)
  381. puts("EEPROM Content Invalid.\n");
  382. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  383. #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
  384. gpmc_init();
  385. #endif
  386. shc_request_gpio();
  387. return 0;
  388. }
  389. #ifdef CONFIG_BOARD_LATE_INIT
  390. int board_late_init(void)
  391. {
  392. check_button_status();
  393. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  394. if (shc_eeprom_valid)
  395. if (is_valid_ethaddr(header.mac_addr))
  396. eth_env_set_enetaddr("ethaddr", header.mac_addr);
  397. #endif
  398. return 0;
  399. }
  400. #endif
  401. #if defined(CONFIG_USB_ETHER) && \
  402. (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
  403. int board_eth_init(bd_t *bis)
  404. {
  405. return usb_eth_initialize(bis);
  406. }
  407. #endif
  408. #ifdef CONFIG_SHOW_BOOT_PROGRESS
  409. static void bosch_check_reset_pin(void)
  410. {
  411. if (readl(GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0) & RESET_MASK) {
  412. printf("Resetting ...\n");
  413. writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
  414. disable_interrupts();
  415. reset_cpu(0);
  416. /*NOTREACHED*/
  417. }
  418. }
  419. static void hang_bosch(const char *cause, int code)
  420. {
  421. int lv;
  422. gpio_direction_input(RESET_GPIO);
  423. /* Enable reset pin interrupt on falling edge */
  424. writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
  425. writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_FALLINGDETECT);
  426. enable_interrupts();
  427. puts(cause);
  428. for (;;) {
  429. for (lv = 0; lv < code; lv++) {
  430. bosch_check_reset_pin();
  431. leds_set_failure(1);
  432. __udelay(150 * 1000);
  433. leds_set_failure(0);
  434. __udelay(150 * 1000);
  435. }
  436. #if defined(BLINK_CODE)
  437. __udelay(300 * 1000);
  438. #endif
  439. }
  440. }
  441. void show_boot_progress(int val)
  442. {
  443. switch (val) {
  444. case BOOTSTAGE_ID_NEED_RESET:
  445. hang_bosch("need reset", 4);
  446. break;
  447. }
  448. }
  449. void arch_preboot_os(void)
  450. {
  451. leds_set_finish();
  452. }
  453. #endif