board.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for Birdland Audio BAV335x Network Processor
  6. *
  7. * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <errno.h>
  12. #include <spl.h>
  13. #include <asm/arch/cpu.h>
  14. #include <asm/arch/hardware.h>
  15. #include <asm/arch/omap.h>
  16. #include <asm/arch/ddr_defs.h>
  17. #include <asm/arch/clock.h>
  18. #include <asm/arch/gpio.h>
  19. #include <asm/arch/mmc_host_def.h>
  20. #include <asm/arch/sys_proto.h>
  21. #include <asm/arch/mem.h>
  22. #include <asm/io.h>
  23. #include <asm/emif.h>
  24. #include <asm/gpio.h>
  25. #include <i2c.h>
  26. #include <miiphy.h>
  27. #include <cpsw.h>
  28. #include <power/tps65217.h>
  29. #include <power/tps65910.h>
  30. #include <environment.h>
  31. #include <watchdog.h>
  32. #include "board.h"
  33. DECLARE_GLOBAL_DATA_PTR;
  34. /* GPIO that controls power to DDR on EVM-SK */
  35. #define GPIO_DDR_VTT_EN 7
  36. static __maybe_unused struct ctrl_dev *cdev =
  37. (struct ctrl_dev *)CTRL_DEVICE_BASE;
  38. /*
  39. * Read header information from EEPROM into global structure.
  40. */
  41. static int read_eeprom(struct board_eeconfig *header)
  42. {
  43. /* Check if baseboard eeprom is available */
  44. if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR))
  45. return -ENODEV;
  46. /* read the eeprom using i2c */
  47. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
  48. sizeof(struct board_eeconfig)))
  49. return -EIO;
  50. if (header->magic != BOARD_MAGIC) {
  51. /* read the i2c eeprom again using only a 1 byte address */
  52. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
  53. sizeof(struct board_eeconfig)))
  54. return -EIO;
  55. if (header->magic != BOARD_MAGIC)
  56. return -EINVAL;
  57. }
  58. return 0;
  59. }
  60. enum board_type get_board_type(bool debug)
  61. {
  62. int ecode;
  63. struct board_eeconfig header;
  64. ecode = read_eeprom(&header);
  65. if (ecode == 0) {
  66. if (header.version[1] == 'A') {
  67. if (debug)
  68. puts("=== Detected Board model BAV335x Rev.A");
  69. return BAV335A;
  70. } else if (header.version[1] == 'B') {
  71. if (debug)
  72. puts("=== Detected Board model BAV335x Rev.B");
  73. return BAV335B;
  74. } else if (debug) {
  75. puts("### Un-known board model in serial-EE\n");
  76. }
  77. } else if (debug) {
  78. switch (ecode) {
  79. case -ENODEV:
  80. puts("### Board doesn't have a serial-EE\n");
  81. break;
  82. case -EINVAL:
  83. puts("### Board serial-EE signature is incorrect.\n");
  84. break;
  85. default:
  86. puts("### IO Error reading serial-EE.\n");
  87. break;
  88. }
  89. }
  90. #if (CONFIG_BAV_VERSION == 1)
  91. if (debug)
  92. puts("### Selecting BAV335A as per config\n");
  93. return BAV335A;
  94. #elif (CONFIG_BAV_VERSION == 2)
  95. if (debug)
  96. puts("### Selecting BAV335B as per config\n");
  97. return BAV335B;
  98. #endif
  99. #if (NOT_DEFINED == 2)
  100. #error "SHOULD NEVER DISPLAY THIS"
  101. #endif
  102. if (debug)
  103. puts("### Defaulting to model BAV335x Rev.B\n");
  104. return BAV335B;
  105. }
  106. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  107. static const struct ddr_data ddr3_bav335x_data = {
  108. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  109. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  110. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  111. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  112. };
  113. static const struct cmd_control ddr3_bav335x_cmd_ctrl_data = {
  114. .cmd0csratio = MT41K256M16HA125E_RATIO,
  115. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  116. .cmd1csratio = MT41K256M16HA125E_RATIO,
  117. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  118. .cmd2csratio = MT41K256M16HA125E_RATIO,
  119. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  120. };
  121. static struct emif_regs ddr3_bav335x_emif_reg_data = {
  122. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  123. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  124. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  125. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  126. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  127. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  128. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  129. };
  130. #ifdef CONFIG_SPL_OS_BOOT
  131. int spl_start_uboot(void)
  132. {
  133. /* break into full u-boot on 'c' */
  134. if (serial_tstc() && serial_getc() == 'c')
  135. return 1;
  136. #ifdef CONFIG_SPL_ENV_SUPPORT
  137. env_init();
  138. env_load();
  139. if (env_get_yesno("boot_os") != 1)
  140. return 1;
  141. #endif
  142. return 0;
  143. }
  144. #endif
  145. #define OSC (V_OSCK/1000000)
  146. const struct dpll_params dpll_ddr = {
  147. 266, OSC-1, 1, -1, -1, -1, -1};
  148. const struct dpll_params dpll_ddr_evm_sk = {
  149. 303, OSC-1, 1, -1, -1, -1, -1};
  150. const struct dpll_params dpll_ddr_bone_black = {
  151. 400, OSC-1, 1, -1, -1, -1, -1};
  152. void am33xx_spl_board_init(void)
  153. {
  154. /* debug print detect status */
  155. (void)get_board_type(true);
  156. /* Get the frequency */
  157. /* dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); */
  158. dpll_mpu_opp100.m = MPUPLL_M_1000;
  159. if (i2c_probe(TPS65217_CHIP_PM))
  160. return;
  161. /* Set the USB Current Limit */
  162. if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
  163. TPS65217_USB_INPUT_CUR_LIMIT_1800MA,
  164. TPS65217_USB_INPUT_CUR_LIMIT_MASK))
  165. puts("! tps65217_reg_write: could not set USB limit\n");
  166. /* Set the Core Voltage (DCDC3) to 1.125V */
  167. if (tps65217_voltage_update(TPS65217_DEFDCDC3,
  168. TPS65217_DCDC_VOLT_SEL_1125MV)) {
  169. puts("! tps65217_reg_write: could not set Core Voltage\n");
  170. return;
  171. }
  172. /* Set CORE Frequencies to OPP100 */
  173. do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  174. /* Set the MPU Voltage (DCDC2) */
  175. if (tps65217_voltage_update(TPS65217_DEFDCDC2,
  176. TPS65217_DCDC_VOLT_SEL_1325MV)) {
  177. puts("! tps65217_reg_write: could not set MPU Voltage\n");
  178. return;
  179. }
  180. /*
  181. * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
  182. * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
  183. */
  184. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS1,
  185. TPS65217_LDO_VOLTAGE_OUT_1_8, TPS65217_LDO_MASK))
  186. puts("! tps65217_reg_write: could not set LDO3\n");
  187. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS2,
  188. TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK))
  189. puts("! tps65217_reg_write: could not set LDO4\n");
  190. /* Set MPU Frequency to what we detected now that voltages are set */
  191. do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
  192. }
  193. const struct dpll_params *get_dpll_ddr_params(void)
  194. {
  195. enable_i2c0_pin_mux();
  196. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  197. return &dpll_ddr_bone_black;
  198. }
  199. void set_uart_mux_conf(void)
  200. {
  201. #if CONFIG_CONS_INDEX == 1
  202. enable_uart0_pin_mux();
  203. #elif CONFIG_CONS_INDEX == 2
  204. enable_uart1_pin_mux();
  205. #elif CONFIG_CONS_INDEX == 3
  206. enable_uart2_pin_mux();
  207. #elif CONFIG_CONS_INDEX == 4
  208. enable_uart3_pin_mux();
  209. #elif CONFIG_CONS_INDEX == 5
  210. enable_uart4_pin_mux();
  211. #elif CONFIG_CONS_INDEX == 6
  212. enable_uart5_pin_mux();
  213. #endif
  214. }
  215. void set_mux_conf_regs(void)
  216. {
  217. enum board_type board;
  218. board = get_board_type(false);
  219. enable_board_pin_mux(board);
  220. }
  221. const struct ctrl_ioregs ioregs_bonelt = {
  222. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  223. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  224. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  225. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  226. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  227. };
  228. void sdram_init(void)
  229. {
  230. config_ddr(400, &ioregs_bonelt,
  231. &ddr3_bav335x_data,
  232. &ddr3_bav335x_cmd_ctrl_data,
  233. &ddr3_bav335x_emif_reg_data, 0);
  234. }
  235. #endif
  236. /*
  237. * Basic board specific setup. Pinmux has been handled already.
  238. */
  239. int board_init(void)
  240. {
  241. #if defined(CONFIG_HW_WATCHDOG)
  242. hw_watchdog_init();
  243. #endif
  244. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  245. #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
  246. gpmc_init();
  247. #endif
  248. return 0;
  249. }
  250. #ifdef CONFIG_BOARD_LATE_INIT
  251. int board_late_init(void)
  252. {
  253. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  254. env_set("board_name", "BAV335xB");
  255. env_set("board_rev", "B"); /* Fix me, but why bother.. */
  256. #endif
  257. return 0;
  258. }
  259. #endif
  260. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  261. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  262. static void cpsw_control(int enabled)
  263. {
  264. /* VTP can be added here */
  265. return;
  266. }
  267. static struct cpsw_slave_data cpsw_slaves[] = {
  268. {
  269. .slave_reg_ofs = 0x208,
  270. .sliver_reg_ofs = 0xd80,
  271. .phy_addr = 0,
  272. },
  273. {
  274. .slave_reg_ofs = 0x308,
  275. .sliver_reg_ofs = 0xdc0,
  276. .phy_addr = 1,
  277. },
  278. };
  279. static struct cpsw_platform_data cpsw_data = {
  280. .mdio_base = CPSW_MDIO_BASE,
  281. .cpsw_base = CPSW_BASE,
  282. .mdio_div = 0xff,
  283. .channels = 8,
  284. .cpdma_reg_ofs = 0x800,
  285. .slaves = 1,
  286. .slave_data = cpsw_slaves,
  287. .ale_reg_ofs = 0xd00,
  288. .ale_entries = 1024,
  289. .host_port_reg_ofs = 0x108,
  290. .hw_stats_reg_ofs = 0x900,
  291. .bd_ram_ofs = 0x2000,
  292. .mac_control = (1 << 5),
  293. .control = cpsw_control,
  294. .host_port_num = 0,
  295. .version = CPSW_CTRL_VERSION_2,
  296. };
  297. #endif
  298. /*
  299. * This function will:
  300. * Perform fixups to the PHY present on certain boards. We only need this
  301. * function in:
  302. * - SPL with either CPSW or USB ethernet support
  303. * - Full U-Boot, with either CPSW or USB ethernet
  304. * Build in only these cases to avoid warnings about unused variables
  305. * when we build an SPL that has neither option but full U-Boot will.
  306. */
  307. #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) &&\
  308. defined(CONFIG_SPL_BUILD)) || \
  309. ((defined(CONFIG_DRIVER_TI_CPSW) || \
  310. defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
  311. !defined(CONFIG_SPL_BUILD))
  312. int board_eth_init(bd_t *bis)
  313. {
  314. int ecode, rv, n;
  315. uint8_t mac_addr[6];
  316. struct board_eeconfig header;
  317. __maybe_unused enum board_type board;
  318. /* Default manufacturing address; used when no EE or invalid */
  319. n = 0;
  320. mac_addr[0] = 0;
  321. mac_addr[1] = 0x20;
  322. mac_addr[2] = 0x18;
  323. mac_addr[3] = 0x1C;
  324. mac_addr[4] = 0x00;
  325. mac_addr[5] = 0x01;
  326. ecode = read_eeprom(&header);
  327. /* if we have a valid EE, get mac address from there */
  328. if ((ecode == 0) &&
  329. is_valid_ethaddr((const u8 *)&header.mac_addr[0][0])) {
  330. memcpy(mac_addr, (const void *)&header.mac_addr[0][0], 6);
  331. }
  332. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  333. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  334. if (!env_get("ethaddr")) {
  335. printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  336. if (is_valid_ethaddr(mac_addr))
  337. eth_env_set_enetaddr("ethaddr", mac_addr);
  338. }
  339. #ifdef CONFIG_DRIVER_TI_CPSW
  340. board = get_board_type(false);
  341. /* Rev.A uses 10/100 PHY in mii mode */
  342. if (board == BAV335A) {
  343. writel(MII_MODE_ENABLE, &cdev->miisel);
  344. cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
  345. cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII;
  346. }
  347. /* Rev.B (default) uses GB PHY in rmii mode */
  348. else {
  349. writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
  350. cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if
  351. = PHY_INTERFACE_MODE_RGMII;
  352. }
  353. rv = cpsw_register(&cpsw_data);
  354. if (rv < 0)
  355. printf("Error %d registering CPSW switch\n", rv);
  356. else
  357. n += rv;
  358. #endif
  359. #endif
  360. return n;
  361. }
  362. #endif