fdt.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007-2011 Freescale Semiconductor, Inc.
  4. *
  5. * (C) Copyright 2000
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. */
  8. #include <common.h>
  9. #include <env.h>
  10. #include <linux/libfdt.h>
  11. #include <fdt_support.h>
  12. #include <asm/processor.h>
  13. #include <linux/ctype.h>
  14. #include <asm/io.h>
  15. #include <asm/fsl_fdt.h>
  16. #include <asm/fsl_portals.h>
  17. #include <fsl_qbman.h>
  18. #include <hwconfig.h>
  19. #ifdef CONFIG_FSL_ESDHC
  20. #include <fsl_esdhc.h>
  21. #endif
  22. #ifdef CONFIG_SYS_DPAA_FMAN
  23. #include <fsl_fman.h>
  24. #endif
  25. DECLARE_GLOBAL_DATA_PTR;
  26. extern void ft_qe_setup(void *blob);
  27. extern void ft_fixup_num_cores(void *blob);
  28. extern void ft_srio_setup(void *blob);
  29. #ifdef CONFIG_MP
  30. #include "mp.h"
  31. void ft_fixup_cpu(void *blob, u64 memory_limit)
  32. {
  33. int off;
  34. phys_addr_t spin_tbl_addr = get_spin_phys_addr();
  35. u32 bootpg = determine_mp_bootpg(NULL);
  36. u32 id = get_my_id();
  37. const char *enable_method;
  38. #if defined(T1040_TDM_QUIRK_CCSR_BASE)
  39. int ret;
  40. int tdm_hwconfig_enabled = 0;
  41. char buffer[HWCONFIG_BUFFER_SIZE] = {0};
  42. #endif
  43. off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  44. while (off != -FDT_ERR_NOTFOUND) {
  45. u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
  46. if (reg) {
  47. u32 phys_cpu_id = thread_to_core(*reg);
  48. u64 val = phys_cpu_id * SIZE_BOOT_ENTRY + spin_tbl_addr;
  49. val = cpu_to_fdt64(val);
  50. if (*reg == id) {
  51. fdt_setprop_string(blob, off, "status",
  52. "okay");
  53. } else {
  54. fdt_setprop_string(blob, off, "status",
  55. "disabled");
  56. }
  57. if (hold_cores_in_reset(0)) {
  58. #ifdef CONFIG_FSL_CORENET
  59. /* Cores held in reset, use BRR to release */
  60. enable_method = "fsl,brr-holdoff";
  61. #else
  62. /* Cores held in reset, use EEBPCR to release */
  63. enable_method = "fsl,eebpcr-holdoff";
  64. #endif
  65. } else {
  66. /* Cores out of reset and in a spin-loop */
  67. enable_method = "spin-table";
  68. fdt_setprop(blob, off, "cpu-release-addr",
  69. &val, sizeof(val));
  70. }
  71. fdt_setprop_string(blob, off, "enable-method",
  72. enable_method);
  73. } else {
  74. printf ("cpu NULL\n");
  75. }
  76. off = fdt_node_offset_by_prop_value(blob, off,
  77. "device_type", "cpu", 4);
  78. }
  79. #if defined(T1040_TDM_QUIRK_CCSR_BASE)
  80. #define CONFIG_MEM_HOLE_16M 0x1000000
  81. /*
  82. * Extract hwconfig from environment.
  83. * Search for tdm entry in hwconfig.
  84. */
  85. ret = env_get_f("hwconfig", buffer, sizeof(buffer));
  86. if (ret > 0)
  87. tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
  88. /* Reserve the memory hole created by TDM LAW, so OSes dont use it */
  89. if (tdm_hwconfig_enabled) {
  90. off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE,
  91. CONFIG_MEM_HOLE_16M);
  92. if (off < 0)
  93. printf("Failed to reserve memory for tdm: %s\n",
  94. fdt_strerror(off));
  95. }
  96. #endif
  97. /* Reserve the boot page so OSes dont use it */
  98. if ((u64)bootpg < memory_limit) {
  99. off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
  100. if (off < 0)
  101. printf("Failed to reserve memory for bootpg: %s\n",
  102. fdt_strerror(off));
  103. }
  104. #ifndef CONFIG_MPC8xxx_DISABLE_BPTR
  105. /*
  106. * Reserve the default boot page so OSes dont use it.
  107. * The default boot page is always mapped to bootpg above using
  108. * boot page translation.
  109. */
  110. if (0xfffff000ull < memory_limit) {
  111. off = fdt_add_mem_rsv(blob, 0xfffff000ull, (u64)4096);
  112. if (off < 0) {
  113. printf("Failed to reserve memory for 0xfffff000: %s\n",
  114. fdt_strerror(off));
  115. }
  116. }
  117. #endif
  118. /* Reserve spin table page */
  119. if (spin_tbl_addr < memory_limit) {
  120. off = fdt_add_mem_rsv(blob,
  121. (spin_tbl_addr & ~0xffful), 4096);
  122. if (off < 0)
  123. printf("Failed to reserve memory for spin table: %s\n",
  124. fdt_strerror(off));
  125. }
  126. #ifdef CONFIG_DEEP_SLEEP
  127. #ifdef CONFIG_SPL_MMC_BOOT
  128. off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START,
  129. CONFIG_SYS_MMC_U_BOOT_SIZE);
  130. if (off < 0)
  131. printf("Failed to reserve memory for SD deep sleep: %s\n",
  132. fdt_strerror(off));
  133. #elif defined(CONFIG_SPL_SPI_BOOT)
  134. off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START,
  135. CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE);
  136. if (off < 0)
  137. printf("Failed to reserve memory for SPI deep sleep: %s\n",
  138. fdt_strerror(off));
  139. #endif
  140. #endif
  141. }
  142. #endif
  143. #ifdef CONFIG_SYS_FSL_CPC
  144. static inline void ft_fixup_l3cache(void *blob, int off)
  145. {
  146. u32 line_size, num_ways, size, num_sets;
  147. cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR;
  148. u32 cfg0 = in_be32(&cpc->cpccfg0);
  149. size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
  150. num_ways = CPC_CFG0_NUM_WAYS(cfg0);
  151. line_size = CPC_CFG0_LINE_SZ(cfg0);
  152. num_sets = size / (line_size * num_ways);
  153. fdt_setprop(blob, off, "cache-unified", NULL, 0);
  154. fdt_setprop_cell(blob, off, "cache-block-size", line_size);
  155. fdt_setprop_cell(blob, off, "cache-size", size);
  156. fdt_setprop_cell(blob, off, "cache-sets", num_sets);
  157. fdt_setprop_cell(blob, off, "cache-level", 3);
  158. #ifdef CONFIG_SYS_CACHE_STASHING
  159. fdt_setprop_cell(blob, off, "cache-stash-id", 1);
  160. #endif
  161. }
  162. #else
  163. #define ft_fixup_l3cache(x, y)
  164. #endif
  165. #if defined(CONFIG_L2_CACHE) || \
  166. defined(CONFIG_BACKSIDE_L2_CACHE) || \
  167. defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
  168. static inline void ft_fixup_l2cache_compatible(void *blob, int off)
  169. {
  170. int len;
  171. struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
  172. if (cpu) {
  173. char buf[40];
  174. if (isdigit(cpu->name[0])) {
  175. /* MPCxxxx, where xxxx == 4-digit number */
  176. len = sprintf(buf, "fsl,mpc%s-l2-cache-controller",
  177. cpu->name) + 1;
  178. } else {
  179. /* Pxxxx or Txxxx, where xxxx == 4-digit number */
  180. len = sprintf(buf, "fsl,%c%s-l2-cache-controller",
  181. tolower(cpu->name[0]), cpu->name + 1) + 1;
  182. }
  183. /*
  184. * append "cache" after the NULL character that the previous
  185. * sprintf wrote. This is how a device tree stores multiple
  186. * strings in a property.
  187. */
  188. len += sprintf(buf + len, "cache") + 1;
  189. fdt_setprop(blob, off, "compatible", buf, len);
  190. }
  191. }
  192. #endif
  193. #if defined(CONFIG_L2_CACHE)
  194. /* return size in kilobytes */
  195. static inline u32 l2cache_size(void)
  196. {
  197. volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
  198. volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
  199. u32 ver = SVR_SOC_VER(get_svr());
  200. switch (l2siz_field) {
  201. case 0x0:
  202. break;
  203. case 0x1:
  204. if (ver == SVR_8540 || ver == SVR_8560 ||
  205. ver == SVR_8541 || ver == SVR_8555)
  206. return 128;
  207. else
  208. return 256;
  209. break;
  210. case 0x2:
  211. if (ver == SVR_8540 || ver == SVR_8560 ||
  212. ver == SVR_8541 || ver == SVR_8555)
  213. return 256;
  214. else
  215. return 512;
  216. break;
  217. case 0x3:
  218. return 1024;
  219. break;
  220. }
  221. return 0;
  222. }
  223. static inline void ft_fixup_l2cache(void *blob)
  224. {
  225. int off;
  226. u32 *ph;
  227. const u32 line_size = 32;
  228. const u32 num_ways = 8;
  229. const u32 size = l2cache_size() * 1024;
  230. const u32 num_sets = size / (line_size * num_ways);
  231. off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  232. if (off < 0) {
  233. debug("no cpu node fount\n");
  234. return;
  235. }
  236. ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
  237. if (ph == NULL) {
  238. debug("no next-level-cache property\n");
  239. return ;
  240. }
  241. off = fdt_node_offset_by_phandle(blob, *ph);
  242. if (off < 0) {
  243. printf("%s: %s\n", __func__, fdt_strerror(off));
  244. return ;
  245. }
  246. ft_fixup_l2cache_compatible(blob, off);
  247. fdt_setprop(blob, off, "cache-unified", NULL, 0);
  248. fdt_setprop_cell(blob, off, "cache-block-size", line_size);
  249. fdt_setprop_cell(blob, off, "cache-size", size);
  250. fdt_setprop_cell(blob, off, "cache-sets", num_sets);
  251. fdt_setprop_cell(blob, off, "cache-level", 2);
  252. /* we dont bother w/L3 since no platform of this type has one */
  253. }
  254. #elif defined(CONFIG_BACKSIDE_L2_CACHE) || \
  255. defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
  256. static inline void ft_fixup_l2cache(void *blob)
  257. {
  258. int off, l2_off, l3_off = -1;
  259. u32 *ph;
  260. #ifdef CONFIG_BACKSIDE_L2_CACHE
  261. u32 l2cfg0 = mfspr(SPRN_L2CFG0);
  262. #else
  263. struct ccsr_cluster_l2 *l2cache =
  264. (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2);
  265. u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
  266. #endif
  267. u32 size, line_size, num_ways, num_sets;
  268. int has_l2 = 1;
  269. /* P2040/P2040E has no L2, so dont set any L2 props */
  270. if (SVR_SOC_VER(get_svr()) == SVR_P2040)
  271. has_l2 = 0;
  272. size = (l2cfg0 & 0x3fff) * 64 * 1024;
  273. num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
  274. line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32;
  275. num_sets = size / (line_size * num_ways);
  276. off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  277. while (off != -FDT_ERR_NOTFOUND) {
  278. ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
  279. if (ph == NULL) {
  280. debug("no next-level-cache property\n");
  281. goto next;
  282. }
  283. l2_off = fdt_node_offset_by_phandle(blob, *ph);
  284. if (l2_off < 0) {
  285. printf("%s: %s\n", __func__, fdt_strerror(off));
  286. goto next;
  287. }
  288. if (has_l2) {
  289. #ifdef CONFIG_SYS_CACHE_STASHING
  290. u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
  291. #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
  292. /* Only initialize every eighth thread */
  293. if (reg && !((*reg) % 8)) {
  294. fdt_setprop_cell(blob, l2_off, "cache-stash-id",
  295. (*reg / 4) + 32 + 1);
  296. }
  297. #else
  298. if (reg) {
  299. fdt_setprop_cell(blob, l2_off, "cache-stash-id",
  300. (*reg * 2) + 32 + 1);
  301. }
  302. #endif
  303. #endif
  304. fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
  305. fdt_setprop_cell(blob, l2_off, "cache-block-size",
  306. line_size);
  307. fdt_setprop_cell(blob, l2_off, "cache-size", size);
  308. fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
  309. fdt_setprop_cell(blob, l2_off, "cache-level", 2);
  310. ft_fixup_l2cache_compatible(blob, l2_off);
  311. }
  312. if (l3_off < 0) {
  313. ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
  314. if (ph == NULL) {
  315. debug("no next-level-cache property\n");
  316. goto next;
  317. }
  318. l3_off = *ph;
  319. }
  320. next:
  321. off = fdt_node_offset_by_prop_value(blob, off,
  322. "device_type", "cpu", 4);
  323. }
  324. if (l3_off > 0) {
  325. l3_off = fdt_node_offset_by_phandle(blob, l3_off);
  326. if (l3_off < 0) {
  327. printf("%s: %s\n", __func__, fdt_strerror(off));
  328. return ;
  329. }
  330. ft_fixup_l3cache(blob, l3_off);
  331. }
  332. }
  333. #else
  334. #define ft_fixup_l2cache(x)
  335. #endif
  336. static inline void ft_fixup_cache(void *blob)
  337. {
  338. int off;
  339. off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  340. while (off != -FDT_ERR_NOTFOUND) {
  341. u32 l1cfg0 = mfspr(SPRN_L1CFG0);
  342. u32 l1cfg1 = mfspr(SPRN_L1CFG1);
  343. u32 isize, iline_size, inum_sets, inum_ways;
  344. u32 dsize, dline_size, dnum_sets, dnum_ways;
  345. /* d-side config */
  346. dsize = (l1cfg0 & 0x7ff) * 1024;
  347. dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
  348. dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
  349. dnum_sets = dsize / (dline_size * dnum_ways);
  350. fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
  351. fdt_setprop_cell(blob, off, "d-cache-size", dsize);
  352. fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
  353. #ifdef CONFIG_SYS_CACHE_STASHING
  354. {
  355. u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
  356. if (reg)
  357. fdt_setprop_cell(blob, off, "cache-stash-id",
  358. (*reg * 2) + 32 + 0);
  359. }
  360. #endif
  361. /* i-side config */
  362. isize = (l1cfg1 & 0x7ff) * 1024;
  363. inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
  364. iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
  365. inum_sets = isize / (iline_size * inum_ways);
  366. fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
  367. fdt_setprop_cell(blob, off, "i-cache-size", isize);
  368. fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
  369. off = fdt_node_offset_by_prop_value(blob, off,
  370. "device_type", "cpu", 4);
  371. }
  372. ft_fixup_l2cache(blob);
  373. }
  374. void fdt_add_enet_stashing(void *fdt)
  375. {
  376. do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
  377. do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
  378. do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
  379. do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1);
  380. do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1);
  381. do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1);
  382. }
  383. #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
  384. #ifdef CONFIG_SYS_DPAA_FMAN
  385. static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
  386. unsigned long freq)
  387. {
  388. phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS;
  389. int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
  390. if (off >= 0) {
  391. off = fdt_setprop_cell(blob, off, "clock-frequency", freq);
  392. if (off > 0)
  393. printf("WARNING enable to set clock-frequency "
  394. "for %s: %s\n", compat, fdt_strerror(off));
  395. }
  396. }
  397. #endif
  398. static void ft_fixup_dpaa_clks(void *blob)
  399. {
  400. sys_info_t sysinfo;
  401. get_sys_info(&sysinfo);
  402. #ifdef CONFIG_SYS_DPAA_FMAN
  403. ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
  404. sysinfo.freq_fman[0]);
  405. #if (CONFIG_SYS_NUM_FMAN == 2)
  406. ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
  407. sysinfo.freq_fman[1]);
  408. #endif
  409. #endif
  410. #ifdef CONFIG_SYS_DPAA_QBMAN
  411. do_fixup_by_compat_u32(blob, "fsl,qman",
  412. "clock-frequency", sysinfo.freq_qman, 1);
  413. #endif
  414. #ifdef CONFIG_SYS_DPAA_PME
  415. do_fixup_by_compat_u32(blob, "fsl,pme",
  416. "clock-frequency", sysinfo.freq_pme, 1);
  417. #endif
  418. }
  419. #else
  420. #define ft_fixup_dpaa_clks(x)
  421. #endif
  422. #ifdef CONFIG_QE
  423. static void ft_fixup_qe_snum(void *blob)
  424. {
  425. unsigned int svr;
  426. svr = mfspr(SPRN_SVR);
  427. if (SVR_SOC_VER(svr) == SVR_8569) {
  428. if(IS_SVR_REV(svr, 1, 0))
  429. do_fixup_by_compat_u32(blob, "fsl,qe",
  430. "fsl,qe-num-snums", 46, 1);
  431. else
  432. do_fixup_by_compat_u32(blob, "fsl,qe",
  433. "fsl,qe-num-snums", 76, 1);
  434. }
  435. }
  436. #endif
  437. #if defined(CONFIG_ARCH_P4080)
  438. static void fdt_fixup_usb(void *fdt)
  439. {
  440. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  441. u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
  442. int off;
  443. off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-mph");
  444. if ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) !=
  445. FSL_CORENET_RCWSR11_EC1_FM1_USB1)
  446. fdt_status_disabled(fdt, off);
  447. off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-dr");
  448. if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) !=
  449. FSL_CORENET_RCWSR11_EC2_USB2)
  450. fdt_status_disabled(fdt, off);
  451. }
  452. #else
  453. #define fdt_fixup_usb(x)
  454. #endif
  455. #if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) || \
  456. defined(CONFIG_ARCH_T4160)
  457. void fdt_fixup_dma3(void *blob)
  458. {
  459. /* the 3rd DMA is not functional if SRIO2 is chosen */
  460. int nodeoff;
  461. ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  462. #define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
  463. #if defined(CONFIG_ARCH_T2080)
  464. u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
  465. FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  466. srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  467. switch (srds_prtcl_s2) {
  468. case 0x29:
  469. case 0x2d:
  470. case 0x2e:
  471. #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
  472. u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
  473. FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
  474. srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
  475. switch (srds_prtcl_s4) {
  476. case 6:
  477. case 8:
  478. case 14:
  479. case 16:
  480. #endif
  481. nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma",
  482. CONFIG_SYS_ELO3_DMA3);
  483. if (nodeoff > 0)
  484. fdt_status_disabled(blob, nodeoff);
  485. else
  486. printf("WARNING: unable to disable dma3\n");
  487. break;
  488. default:
  489. break;
  490. }
  491. }
  492. #else
  493. #define fdt_fixup_dma3(x)
  494. #endif
  495. #if defined(CONFIG_ARCH_T1040)
  496. static void fdt_fixup_l2_switch(void *blob)
  497. {
  498. uchar l2swaddr[6];
  499. int node;
  500. /* The l2switch node from device-tree has
  501. * compatible string "vitesse-9953" */
  502. node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953");
  503. if (node == -FDT_ERR_NOTFOUND)
  504. /* no l2switch node has been found */
  505. return;
  506. /* Get MAC address for the l2switch from "l2switchaddr"*/
  507. if (!eth_env_get_enetaddr("l2switchaddr", l2swaddr)) {
  508. printf("Warning: MAC address for l2switch not found\n");
  509. memset(l2swaddr, 0, sizeof(l2swaddr));
  510. }
  511. /* Add MAC address to l2switch node */
  512. fdt_setprop(blob, node, "local-mac-address", l2swaddr,
  513. sizeof(l2swaddr));
  514. }
  515. #else
  516. #define fdt_fixup_l2_switch(x)
  517. #endif
  518. void ft_cpu_setup(void *blob, bd_t *bd)
  519. {
  520. int off;
  521. int val;
  522. int len;
  523. sys_info_t sysinfo;
  524. /* delete crypto node if not on an E-processor */
  525. if (!IS_E_PROCESSOR(get_svr()))
  526. fdt_fixup_crypto_node(blob, 0);
  527. #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
  528. else {
  529. ccsr_sec_t __iomem *sec;
  530. sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
  531. fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
  532. }
  533. #endif
  534. fdt_add_enet_stashing(blob);
  535. #ifndef CONFIG_FSL_TBCLK_EXTRA_DIV
  536. #define CONFIG_FSL_TBCLK_EXTRA_DIV 1
  537. #endif
  538. do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
  539. "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV,
  540. 1);
  541. do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
  542. "bus-frequency", bd->bi_busfreq, 1);
  543. get_sys_info(&sysinfo);
  544. off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  545. while (off != -FDT_ERR_NOTFOUND) {
  546. u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len);
  547. val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]);
  548. fdt_setprop(blob, off, "clock-frequency", &val, 4);
  549. off = fdt_node_offset_by_prop_value(blob, off, "device_type",
  550. "cpu", 4);
  551. }
  552. do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
  553. "bus-frequency", bd->bi_busfreq, 1);
  554. #ifdef CONFIG_QE
  555. ft_qe_setup(blob);
  556. ft_fixup_qe_snum(blob);
  557. #endif
  558. #ifdef CONFIG_SYS_DPAA_FMAN
  559. fdt_fixup_fman_firmware(blob);
  560. #endif
  561. #ifdef CONFIG_SYS_NS16550
  562. do_fixup_by_compat_u32(blob, "ns16550",
  563. "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
  564. #endif
  565. #ifdef CONFIG_CPM2
  566. do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
  567. "current-speed", gd->baudrate, 1);
  568. do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
  569. "clock-frequency", bd->bi_brgfreq, 1);
  570. #endif
  571. #ifdef CONFIG_FSL_CORENET
  572. do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
  573. "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
  574. do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0",
  575. "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
  576. do_fixup_by_compat_u32(blob, "fsl,mpic",
  577. "clock-frequency", get_bus_freq(0)/2, 1);
  578. #else
  579. do_fixup_by_compat_u32(blob, "fsl,mpic",
  580. "clock-frequency", get_bus_freq(0), 1);
  581. #endif
  582. fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
  583. #ifdef CONFIG_MP
  584. ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
  585. ft_fixup_num_cores(blob);
  586. #endif
  587. ft_fixup_cache(blob);
  588. #if defined(CONFIG_FSL_ESDHC)
  589. fdt_fixup_esdhc(blob, bd);
  590. #endif
  591. ft_fixup_dpaa_clks(blob);
  592. #if defined(CONFIG_SYS_BMAN_MEM_PHYS)
  593. fdt_portal(blob, "fsl,bman-portal", "bman-portals",
  594. (u64)CONFIG_SYS_BMAN_MEM_PHYS,
  595. CONFIG_SYS_BMAN_MEM_SIZE);
  596. fdt_fixup_bportals(blob);
  597. #endif
  598. #if defined(CONFIG_SYS_QMAN_MEM_PHYS)
  599. fdt_portal(blob, "fsl,qman-portal", "qman-portals",
  600. (u64)CONFIG_SYS_QMAN_MEM_PHYS,
  601. CONFIG_SYS_QMAN_MEM_SIZE);
  602. fdt_fixup_qportals(blob);
  603. #endif
  604. #ifdef CONFIG_SYS_SRIO
  605. ft_srio_setup(blob);
  606. #endif
  607. /*
  608. * system-clock = CCB clock/2
  609. * Here gd->bus_clk = CCB clock
  610. * We are using the system clock as 1588 Timer reference
  611. * clock source select
  612. */
  613. do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer",
  614. "timer-frequency", gd->bus_clk/2, 1);
  615. /*
  616. * clock-freq should change to clock-frequency and
  617. * flexcan-v1.0 should change to p1010-flexcan respectively
  618. * in the future.
  619. */
  620. do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
  621. "clock_freq", gd->bus_clk/2, 1);
  622. do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
  623. "clock-frequency", gd->bus_clk/2, 1);
  624. do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan",
  625. "clock-frequency", gd->bus_clk/2, 1);
  626. fdt_fixup_usb(blob);
  627. fdt_fixup_l2_switch(blob);
  628. fdt_fixup_dma3(blob);
  629. }
  630. /*
  631. * For some CCSR devices, we only have the virtual address, not the physical
  632. * address. This is because we map CCSR as a whole, so we typically don't need
  633. * a macro for the physical address of any device within CCSR. In this case,
  634. * we calculate the physical address of that device using it's the difference
  635. * between the virtual address of the device and the virtual address of the
  636. * beginning of CCSR.
  637. */
  638. #define CCSR_VIRT_TO_PHYS(x) \
  639. (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
  640. static void msg(const char *name, uint64_t uaddr, uint64_t daddr)
  641. {
  642. printf("Warning: U-Boot configured %s at address %llx,\n"
  643. "but the device tree has it at %llx\n", name, uaddr, daddr);
  644. }
  645. /*
  646. * Verify the device tree
  647. *
  648. * This function compares several CONFIG_xxx macros that contain physical
  649. * addresses with the corresponding nodes in the device tree, to see if
  650. * the physical addresses are all correct. For example, if
  651. * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address
  652. * of the first UART. We convert this to a physical address and compare
  653. * that with the physical address of the first ns16550-compatible node
  654. * in the device tree. If they don't match, then we display a warning.
  655. *
  656. * Returns 1 on success, 0 on failure
  657. */
  658. int ft_verify_fdt(void *fdt)
  659. {
  660. uint64_t addr = 0;
  661. int aliases;
  662. int off;
  663. /* First check the CCSR base address */
  664. off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4);
  665. if (off > 0) {
  666. int size;
  667. u32 naddr;
  668. const fdt32_t *prop;
  669. naddr = fdt_address_cells(fdt, off);
  670. prop = fdt_getprop(fdt, off, "ranges", &size);
  671. addr = fdt_translate_address(fdt, off, prop + naddr);
  672. }
  673. if (!addr) {
  674. printf("Warning: could not determine base CCSR address in "
  675. "device tree\n");
  676. /* No point in checking anything else */
  677. return 0;
  678. }
  679. if (addr != CONFIG_SYS_CCSRBAR_PHYS) {
  680. msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr);
  681. /* No point in checking anything else */
  682. return 0;
  683. }
  684. /*
  685. * Check some nodes via aliases. We assume that U-Boot and the device
  686. * tree enumerate the devices equally. E.g. the first serial port in
  687. * U-Boot is the same as "serial0" in the device tree.
  688. */
  689. aliases = fdt_path_offset(fdt, "/aliases");
  690. if (aliases > 0) {
  691. #ifdef CONFIG_SYS_NS16550_COM1
  692. if (!fdt_verify_alias_address(fdt, aliases, "serial0",
  693. CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1)))
  694. return 0;
  695. #endif
  696. #ifdef CONFIG_SYS_NS16550_COM2
  697. if (!fdt_verify_alias_address(fdt, aliases, "serial1",
  698. CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2)))
  699. return 0;
  700. #endif
  701. }
  702. /*
  703. * The localbus node is typically a root node, even though the lbc
  704. * controller is part of CCSR. If we were to put the lbc node under
  705. * the SOC node, then the 'ranges' property in the lbc node would
  706. * translate through the 'ranges' property of the parent SOC node, and
  707. * we don't want that. Since it's a separate node, it's possible for
  708. * the 'reg' property to be wrong, so check it here. For now, we
  709. * only check for "fsl,elbc" nodes.
  710. */
  711. #ifdef CONFIG_SYS_LBC_ADDR
  712. off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc");
  713. if (off > 0) {
  714. const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL);
  715. if (reg) {
  716. uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR);
  717. addr = fdt_translate_address(fdt, off, reg);
  718. if (uaddr != addr) {
  719. msg("the localbus", uaddr, addr);
  720. return 0;
  721. }
  722. }
  723. }
  724. #endif
  725. return 1;
  726. }
  727. void fdt_del_diu(void *blob)
  728. {
  729. int nodeoff = 0;
  730. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  731. "fsl,diu")) >= 0) {
  732. fdt_del_node(blob, nodeoff);
  733. }
  734. }