clock.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2008
  4. * Texas Instruments, <www.ti.com>
  5. *
  6. * Author :
  7. * Manikandan Pillai <mani.pillai@ti.com>
  8. *
  9. * Derived from Beagle Board and OMAP3 SDP code by
  10. * Richard Woodruff <r-woodruff2@ti.com>
  11. * Syed Mohammed Khasim <khasim@ti.com>
  12. */
  13. #include <common.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/clocks_omap3.h>
  17. #include <asm/arch/mem.h>
  18. #include <asm/arch/sys_proto.h>
  19. #include <command.h>
  20. /******************************************************************************
  21. * get_sys_clk_speed() - determine reference oscillator speed
  22. * based on known 32kHz clock and gptimer.
  23. *****************************************************************************/
  24. u32 get_osc_clk_speed(void)
  25. {
  26. u32 start, cstart, cend, cdiff, cdiv, val;
  27. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  28. struct prm *prm_base = (struct prm *)PRM_BASE;
  29. struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1;
  30. struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE;
  31. val = readl(&prm_base->clksrc_ctrl);
  32. if (val & SYSCLKDIV_2)
  33. cdiv = 2;
  34. else
  35. cdiv = 1;
  36. /* enable timer2 */
  37. val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
  38. /* select sys_clk for GPT1 */
  39. writel(val, &prcm_base->clksel_wkup);
  40. /* Enable I and F Clocks for GPT1 */
  41. val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC;
  42. writel(val, &prcm_base->iclken_wkup);
  43. val = readl(&prcm_base->fclken_wkup) | EN_GPT1;
  44. writel(val, &prcm_base->fclken_wkup);
  45. writel(0, &gpt1_base->tldr); /* start counting at 0 */
  46. writel(GPT_EN, &gpt1_base->tclr); /* enable clock */
  47. /* enable 32kHz source, determine sys_clk via gauging */
  48. /* start time in 20 cycles */
  49. start = 20 + readl(&s32k_base->s32k_cr);
  50. /* dead loop till start time */
  51. while (readl(&s32k_base->s32k_cr) < start);
  52. /* get start sys_clk count */
  53. cstart = readl(&gpt1_base->tcrr);
  54. /* wait for 40 cycles */
  55. while (readl(&s32k_base->s32k_cr) < (start + 20)) ;
  56. cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */
  57. cdiff = cend - cstart; /* get elapsed ticks */
  58. cdiff *= cdiv;
  59. /* based on number of ticks assign speed */
  60. if (cdiff > 19000)
  61. return S38_4M;
  62. else if (cdiff > 15200)
  63. return S26M;
  64. else if (cdiff > 13000)
  65. return S24M;
  66. else if (cdiff > 9000)
  67. return S19_2M;
  68. else if (cdiff > 7600)
  69. return S13M;
  70. else
  71. return S12M;
  72. }
  73. /******************************************************************************
  74. * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
  75. * input oscillator clock frequency.
  76. *****************************************************************************/
  77. void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
  78. {
  79. switch(osc_clk) {
  80. case S38_4M:
  81. *sys_clkin_sel = 4;
  82. break;
  83. case S26M:
  84. *sys_clkin_sel = 3;
  85. break;
  86. case S19_2M:
  87. *sys_clkin_sel = 2;
  88. break;
  89. case S13M:
  90. *sys_clkin_sel = 1;
  91. break;
  92. case S12M:
  93. default:
  94. *sys_clkin_sel = 0;
  95. }
  96. }
  97. /*
  98. * OMAP34XX/35XX specific functions
  99. */
  100. static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
  101. {
  102. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  103. dpll_param *ptr = (dpll_param *) get_core_dpll_param();
  104. void (*f_lock_pll) (u32, u32, u32, u32);
  105. int xip_safe, p0, p1, p2, p3;
  106. xip_safe = is_running_in_sram();
  107. /* Moving to the right sysclk and ES rev base */
  108. ptr = ptr + (3 * clk_index) + sil_index;
  109. if (xip_safe) {
  110. /*
  111. * CORE DPLL
  112. */
  113. clrsetbits_le32(&prcm_base->clken_pll,
  114. 0x00000007, PLL_FAST_RELOCK_BYPASS);
  115. wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
  116. LDELAY);
  117. /*
  118. * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't
  119. * work. write another value and then default value.
  120. */
  121. /* CM_CLKSEL1_EMU[DIV_DPLL3] */
  122. clrsetbits_le32(&prcm_base->clksel1_emu,
  123. 0x001F0000, (CORE_M3X2 + 1) << 16) ;
  124. clrsetbits_le32(&prcm_base->clksel1_emu,
  125. 0x001F0000, CORE_M3X2 << 16);
  126. /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
  127. clrsetbits_le32(&prcm_base->clksel1_pll,
  128. 0xF8000000, ptr->m2 << 27);
  129. /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
  130. clrsetbits_le32(&prcm_base->clksel1_pll,
  131. 0x07FF0000, ptr->m << 16);
  132. /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
  133. clrsetbits_le32(&prcm_base->clksel1_pll,
  134. 0x00007F00, ptr->n << 8);
  135. /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
  136. clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
  137. /* SSI */
  138. clrsetbits_le32(&prcm_base->clksel_core,
  139. 0x00000F00, CORE_SSI_DIV << 8);
  140. /* FSUSB */
  141. clrsetbits_le32(&prcm_base->clksel_core,
  142. 0x00000030, CORE_FUSB_DIV << 4);
  143. /* L4 */
  144. clrsetbits_le32(&prcm_base->clksel_core,
  145. 0x0000000C, CORE_L4_DIV << 2);
  146. /* L3 */
  147. clrsetbits_le32(&prcm_base->clksel_core,
  148. 0x00000003, CORE_L3_DIV);
  149. /* GFX */
  150. clrsetbits_le32(&prcm_base->clksel_gfx,
  151. 0x00000007, GFX_DIV);
  152. /* RESET MGR */
  153. clrsetbits_le32(&prcm_base->clksel_wkup,
  154. 0x00000006, WKUP_RSM << 1);
  155. /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
  156. clrsetbits_le32(&prcm_base->clken_pll,
  157. 0x000000F0, ptr->fsel << 4);
  158. /* LOCK MODE */
  159. clrsetbits_le32(&prcm_base->clken_pll,
  160. 0x00000007, PLL_LOCK);
  161. wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
  162. LDELAY);
  163. } else if (is_running_in_flash()) {
  164. /*
  165. * if running from flash, jump to small relocated code
  166. * area in SRAM.
  167. */
  168. f_lock_pll = (void *) (SRAM_CLK_CODE);
  169. p0 = readl(&prcm_base->clken_pll);
  170. clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
  171. /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
  172. clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
  173. p1 = readl(&prcm_base->clksel1_pll);
  174. /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
  175. clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
  176. /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
  177. clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
  178. /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
  179. clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
  180. /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
  181. clrbits_le32(&p1, 0x00000040);
  182. p2 = readl(&prcm_base->clksel_core);
  183. /* SSI */
  184. clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
  185. /* FSUSB */
  186. clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
  187. /* L4 */
  188. clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
  189. /* L3 */
  190. clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
  191. p3 = (u32)&prcm_base->idlest_ckgen;
  192. (*f_lock_pll) (p0, p1, p2, p3);
  193. }
  194. }
  195. static void dpll4_init_34xx(u32 sil_index, u32 clk_index)
  196. {
  197. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  198. dpll_param *ptr = (dpll_param *) get_per_dpll_param();
  199. /* Moving it to the right sysclk base */
  200. ptr = ptr + clk_index;
  201. /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
  202. clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
  203. wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
  204. /*
  205. * Errata 1.50 Workaround for OMAP3 ES1.0 only
  206. * If using default divisors, write default divisor + 1
  207. * and then the actual divisor value
  208. */
  209. /* M6 */
  210. clrsetbits_le32(&prcm_base->clksel1_emu,
  211. 0x1F000000, (PER_M6X2 + 1) << 24);
  212. clrsetbits_le32(&prcm_base->clksel1_emu,
  213. 0x1F000000, PER_M6X2 << 24);
  214. /* M5 */
  215. clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, (PER_M5X2 + 1));
  216. clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, PER_M5X2);
  217. /* M4 */
  218. clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, (PER_M4X2 + 1));
  219. clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, PER_M4X2);
  220. /* M3 */
  221. clrsetbits_le32(&prcm_base->clksel_dss,
  222. 0x00001F00, (PER_M3X2 + 1) << 8);
  223. clrsetbits_le32(&prcm_base->clksel_dss,
  224. 0x00001F00, PER_M3X2 << 8);
  225. /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
  226. clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, (ptr->m2 + 1));
  227. clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);
  228. /* Workaround end */
  229. /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */
  230. clrsetbits_le32(&prcm_base->clksel2_pll,
  231. 0x0007FF00, ptr->m << 8);
  232. /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
  233. clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);
  234. /* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */
  235. clrsetbits_le32(&prcm_base->clken_pll, 0x00F00000, ptr->fsel << 20);
  236. /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
  237. clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
  238. wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
  239. }
  240. static void dpll5_init_34xx(u32 sil_index, u32 clk_index)
  241. {
  242. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  243. dpll_param *ptr = (dpll_param *) get_per2_dpll_param();
  244. /* Moving it to the right sysclk base */
  245. ptr = ptr + clk_index;
  246. /* PER2 DPLL (DPLL5) */
  247. clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP);
  248. wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
  249. /* set M2 (usbtll_fck) */
  250. clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);
  251. /* set m (11-bit multiplier) */
  252. clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8);
  253. /* set n (7-bit divider)*/
  254. clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n);
  255. /* FREQSEL */
  256. clrsetbits_le32(&prcm_base->clken_pll, 0x000000F0, ptr->fsel << 4);
  257. /* lock mode */
  258. clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK);
  259. wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
  260. }
  261. static void mpu_init_34xx(u32 sil_index, u32 clk_index)
  262. {
  263. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  264. dpll_param *ptr = (dpll_param *) get_mpu_dpll_param();
  265. /* Moving to the right sysclk and ES rev base */
  266. ptr = ptr + (3 * clk_index) + sil_index;
  267. /* MPU DPLL (unlocked already) */
  268. /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
  269. clrsetbits_le32(&prcm_base->clksel2_pll_mpu,
  270. 0x0000001F, ptr->m2);
  271. /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
  272. clrsetbits_le32(&prcm_base->clksel1_pll_mpu,
  273. 0x0007FF00, ptr->m << 8);
  274. /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
  275. clrsetbits_le32(&prcm_base->clksel1_pll_mpu,
  276. 0x0000007F, ptr->n);
  277. /* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
  278. clrsetbits_le32(&prcm_base->clken_pll_mpu,
  279. 0x000000F0, ptr->fsel << 4);
  280. }
  281. static void iva_init_34xx(u32 sil_index, u32 clk_index)
  282. {
  283. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  284. dpll_param *ptr = (dpll_param *) get_iva_dpll_param();
  285. /* Moving to the right sysclk and ES rev base */
  286. ptr = ptr + (3 * clk_index) + sil_index;
  287. /* IVA DPLL */
  288. /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
  289. clrsetbits_le32(&prcm_base->clken_pll_iva2,
  290. 0x00000007, PLL_STOP);
  291. wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
  292. /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
  293. clrsetbits_le32(&prcm_base->clksel2_pll_iva2,
  294. 0x0000001F, ptr->m2);
  295. /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
  296. clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
  297. 0x0007FF00, ptr->m << 8);
  298. /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
  299. clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
  300. 0x0000007F, ptr->n);
  301. /* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
  302. clrsetbits_le32(&prcm_base->clken_pll_iva2,
  303. 0x000000F0, ptr->fsel << 4);
  304. /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
  305. clrsetbits_le32(&prcm_base->clken_pll_iva2,
  306. 0x00000007, PLL_LOCK);
  307. wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
  308. }
  309. /*
  310. * OMAP3630 specific functions
  311. */
  312. static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
  313. {
  314. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  315. dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param();
  316. void (*f_lock_pll) (u32, u32, u32, u32);
  317. int xip_safe, p0, p1, p2, p3;
  318. xip_safe = is_running_in_sram();
  319. /* Moving it to the right sysclk base */
  320. ptr += clk_index;
  321. if (xip_safe) {
  322. /* CORE DPLL */
  323. /* Select relock bypass: CM_CLKEN_PLL[0:2] */
  324. clrsetbits_le32(&prcm_base->clken_pll,
  325. 0x00000007, PLL_FAST_RELOCK_BYPASS);
  326. wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
  327. LDELAY);
  328. /* CM_CLKSEL1_EMU[DIV_DPLL3] */
  329. clrsetbits_le32(&prcm_base->clksel1_emu,
  330. 0x001F0000, CORE_M3X2 << 16);
  331. /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
  332. clrsetbits_le32(&prcm_base->clksel1_pll,
  333. 0xF8000000, ptr->m2 << 27);
  334. /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
  335. clrsetbits_le32(&prcm_base->clksel1_pll,
  336. 0x07FF0000, ptr->m << 16);
  337. /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
  338. clrsetbits_le32(&prcm_base->clksel1_pll,
  339. 0x00007F00, ptr->n << 8);
  340. /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
  341. clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
  342. /* SSI */
  343. clrsetbits_le32(&prcm_base->clksel_core,
  344. 0x00000F00, CORE_SSI_DIV << 8);
  345. /* FSUSB */
  346. clrsetbits_le32(&prcm_base->clksel_core,
  347. 0x00000030, CORE_FUSB_DIV << 4);
  348. /* L4 */
  349. clrsetbits_le32(&prcm_base->clksel_core,
  350. 0x0000000C, CORE_L4_DIV << 2);
  351. /* L3 */
  352. clrsetbits_le32(&prcm_base->clksel_core,
  353. 0x00000003, CORE_L3_DIV);
  354. /* GFX */
  355. clrsetbits_le32(&prcm_base->clksel_gfx,
  356. 0x00000007, GFX_DIV_36X);
  357. /* RESET MGR */
  358. clrsetbits_le32(&prcm_base->clksel_wkup,
  359. 0x00000006, WKUP_RSM << 1);
  360. /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
  361. clrsetbits_le32(&prcm_base->clken_pll,
  362. 0x000000F0, ptr->fsel << 4);
  363. /* LOCK MODE */
  364. clrsetbits_le32(&prcm_base->clken_pll,
  365. 0x00000007, PLL_LOCK);
  366. wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
  367. LDELAY);
  368. } else if (is_running_in_flash()) {
  369. /*
  370. * if running from flash, jump to small relocated code
  371. * area in SRAM.
  372. */
  373. f_lock_pll = (void *) (SRAM_CLK_CODE);
  374. p0 = readl(&prcm_base->clken_pll);
  375. clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
  376. /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
  377. clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
  378. p1 = readl(&prcm_base->clksel1_pll);
  379. /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
  380. clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
  381. /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
  382. clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
  383. /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
  384. clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
  385. /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
  386. clrbits_le32(&p1, 0x00000040);
  387. p2 = readl(&prcm_base->clksel_core);
  388. /* SSI */
  389. clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
  390. /* FSUSB */
  391. clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
  392. /* L4 */
  393. clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
  394. /* L3 */
  395. clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
  396. p3 = (u32)&prcm_base->idlest_ckgen;
  397. (*f_lock_pll) (p0, p1, p2, p3);
  398. }
  399. }
  400. static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
  401. {
  402. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  403. struct dpll_per_36x_param *ptr;
  404. ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();
  405. /* Moving it to the right sysclk base */
  406. ptr += clk_index;
  407. /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
  408. clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
  409. wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
  410. /* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
  411. clrsetbits_le32(&prcm_base->clksel1_emu, 0x3F000000, ptr->m6 << 24);
  412. /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
  413. clrsetbits_le32(&prcm_base->clksel_cam, 0x0000003F, ptr->m5);
  414. /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
  415. clrsetbits_le32(&prcm_base->clksel_dss, 0x0000003F, ptr->m4);
  416. /* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
  417. clrsetbits_le32(&prcm_base->clksel_dss, 0x00003F00, ptr->m3 << 8);
  418. /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
  419. clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);
  420. /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
  421. clrsetbits_le32(&prcm_base->clksel2_pll, 0x000FFF00, ptr->m << 8);
  422. /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
  423. clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);
  424. /* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
  425. clrsetbits_le32(&prcm_base->clksel_core, 0x00003000, ptr->m2div << 12);
  426. /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
  427. clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
  428. wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
  429. }
  430. static void dpll5_init_36xx(u32 sil_index, u32 clk_index)
  431. {
  432. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  433. dpll_param *ptr = (dpll_param *) get_36x_per2_dpll_param();
  434. /* Moving it to the right sysclk base */
  435. ptr = ptr + clk_index;
  436. /* PER2 DPLL (DPLL5) */
  437. clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP);
  438. wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
  439. /* set M2 (usbtll_fck) */
  440. clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);
  441. /* set m (11-bit multiplier) */
  442. clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8);
  443. /* set n (7-bit divider)*/
  444. clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n);
  445. /* lock mode */
  446. clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK);
  447. wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
  448. }
  449. static void mpu_init_36xx(u32 sil_index, u32 clk_index)
  450. {
  451. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  452. dpll_param *ptr = (dpll_param *) get_36x_mpu_dpll_param();
  453. /* Moving to the right sysclk */
  454. ptr += clk_index;
  455. /* MPU DPLL (unlocked already */
  456. /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
  457. clrsetbits_le32(&prcm_base->clksel2_pll_mpu, 0x0000001F, ptr->m2);
  458. /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
  459. clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0007FF00, ptr->m << 8);
  460. /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
  461. clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0000007F, ptr->n);
  462. }
  463. static void iva_init_36xx(u32 sil_index, u32 clk_index)
  464. {
  465. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  466. dpll_param *ptr = (dpll_param *)get_36x_iva_dpll_param();
  467. /* Moving to the right sysclk */
  468. ptr += clk_index;
  469. /* IVA DPLL */
  470. /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
  471. clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_STOP);
  472. wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
  473. /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
  474. clrsetbits_le32(&prcm_base->clksel2_pll_iva2, 0x0000001F, ptr->m2);
  475. /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
  476. clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0007FF00, ptr->m << 8);
  477. /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
  478. clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0000007F, ptr->n);
  479. /* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
  480. clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_LOCK);
  481. wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
  482. }
  483. /******************************************************************************
  484. * prcm_init() - inits clocks for PRCM as defined in clocks.h
  485. * called from SRAM, or Flash (using temp SRAM stack).
  486. *****************************************************************************/
  487. void prcm_init(void)
  488. {
  489. u32 osc_clk = 0, sys_clkin_sel;
  490. u32 clk_index, sil_index = 0;
  491. struct prm *prm_base = (struct prm *)PRM_BASE;
  492. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  493. /*
  494. * Gauge the input clock speed and find out the sys_clkin_sel
  495. * value corresponding to the input clock.
  496. */
  497. osc_clk = get_osc_clk_speed();
  498. get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
  499. /* set input crystal speed */
  500. clrsetbits_le32(&prm_base->clksel, 0x00000007, sys_clkin_sel);
  501. /* If the input clock is greater than 19.2M always divide/2 */
  502. if (sys_clkin_sel > 2) {
  503. /* input clock divider */
  504. clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 2 << 6);
  505. clk_index = sys_clkin_sel / 2;
  506. } else {
  507. /* input clock divider */
  508. clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 1 << 6);
  509. clk_index = sys_clkin_sel;
  510. }
  511. if (get_cpu_family() == CPU_OMAP36XX) {
  512. /*
  513. * In warm reset conditions on OMAP36xx/AM/DM37xx
  514. * the rom code incorrectly sets the DPLL4 clock
  515. * input divider to /6.5. Section 3.5.3.3.3.2.1 of
  516. * the AM/DM37x TRM explains that the /6.5 divider
  517. * is used only when the input clock is 13MHz.
  518. *
  519. * If the part is in this cpu family *and* the input
  520. * clock *is not* 13 MHz, then reset the DPLL4 clock
  521. * input divider to /1 as it should never set to /6.5
  522. * in this case.
  523. */
  524. if (sys_clkin_sel != 1) { /* 13 MHz */
  525. /* Bit 8: DPLL4_CLKINP_DIV */
  526. clrbits_le32(&prm_base->clksrc_ctrl, 0x00000100);
  527. }
  528. /* Unlock MPU DPLL (slows things down, and needed later) */
  529. clrsetbits_le32(&prcm_base->clken_pll_mpu,
  530. 0x00000007, PLL_LOW_POWER_BYPASS);
  531. wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
  532. LDELAY);
  533. dpll3_init_36xx(0, clk_index);
  534. dpll4_init_36xx(0, clk_index);
  535. dpll5_init_36xx(0, clk_index);
  536. iva_init_36xx(0, clk_index);
  537. mpu_init_36xx(0, clk_index);
  538. /* Lock MPU DPLL to set frequency */
  539. clrsetbits_le32(&prcm_base->clken_pll_mpu,
  540. 0x00000007, PLL_LOCK);
  541. wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
  542. LDELAY);
  543. } else {
  544. /*
  545. * The DPLL tables are defined according to sysclk value and
  546. * silicon revision. The clk_index value will be used to get
  547. * the values for that input sysclk from the DPLL param table
  548. * and sil_index will get the values for that SysClk for the
  549. * appropriate silicon rev.
  550. */
  551. if (((get_cpu_family() == CPU_OMAP34XX)
  552. && (get_cpu_rev() >= CPU_3XX_ES20)) ||
  553. (get_cpu_family() == CPU_AM35XX))
  554. sil_index = 1;
  555. /* Unlock MPU DPLL (slows things down, and needed later) */
  556. clrsetbits_le32(&prcm_base->clken_pll_mpu,
  557. 0x00000007, PLL_LOW_POWER_BYPASS);
  558. wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
  559. LDELAY);
  560. dpll3_init_34xx(sil_index, clk_index);
  561. dpll4_init_34xx(sil_index, clk_index);
  562. dpll5_init_34xx(sil_index, clk_index);
  563. if (get_cpu_family() != CPU_AM35XX)
  564. iva_init_34xx(sil_index, clk_index);
  565. mpu_init_34xx(sil_index, clk_index);
  566. /* Lock MPU DPLL to set frequency */
  567. clrsetbits_le32(&prcm_base->clken_pll_mpu,
  568. 0x00000007, PLL_LOCK);
  569. wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
  570. LDELAY);
  571. }
  572. /* Set up GPTimers to sys_clk source only */
  573. setbits_le32(&prcm_base->clksel_per, 0x000000FF);
  574. setbits_le32(&prcm_base->clksel_wkup, 1);
  575. sdelay(5000);
  576. }
  577. /*
  578. * Enable usb ehci uhh, tll clocks
  579. */
  580. void ehci_clocks_enable(void)
  581. {
  582. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  583. /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
  584. setbits_le32(&prcm_base->iclken_usbhost, 1);
  585. /*
  586. * Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
  587. * and USBHOST_120M_FCLK (USBHOST_FCLK2)
  588. */
  589. setbits_le32(&prcm_base->fclken_usbhost, 0x00000003);
  590. /* Enable USBTTL_ICLK */
  591. setbits_le32(&prcm_base->iclken3_core, 0x00000004);
  592. /* Enable USBTTL_FCLK */
  593. setbits_le32(&prcm_base->fclken3_core, 0x00000004);
  594. }
  595. /******************************************************************************
  596. * peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...)
  597. *****************************************************************************/
  598. void per_clocks_enable(void)
  599. {
  600. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  601. /* Enable GP2 timer. */
  602. setbits_le32(&prcm_base->clksel_per, 0x01); /* GPT2 = sys clk */
  603. setbits_le32(&prcm_base->iclken_per, 0x08); /* ICKen GPT2 */
  604. setbits_le32(&prcm_base->fclken_per, 0x08); /* FCKen GPT2 */
  605. /* Enable GP9 timer. */
  606. setbits_le32(&prcm_base->clksel_per, 0x80); /* GPT9 = 32kHz clk */
  607. setbits_le32(&prcm_base->iclken_per, 0x400); /* ICKen GPT9 */
  608. setbits_le32(&prcm_base->fclken_per, 0x400); /* FCKen GPT9 */
  609. #ifdef CONFIG_SYS_NS16550
  610. /* Enable UART1 clocks */
  611. setbits_le32(&prcm_base->fclken1_core, 0x00002000);
  612. setbits_le32(&prcm_base->iclken1_core, 0x00002000);
  613. /* Enable UART2 clocks */
  614. setbits_le32(&prcm_base->fclken1_core, 0x00004000);
  615. setbits_le32(&prcm_base->iclken1_core, 0x00004000);
  616. /* UART 3 Clocks */
  617. setbits_le32(&prcm_base->fclken_per, 0x00000800);
  618. setbits_le32(&prcm_base->iclken_per, 0x00000800);
  619. #endif
  620. #if defined(CONFIG_OMAP3_GPIO_2)
  621. setbits_le32(&prcm_base->fclken_per, 0x00002000);
  622. setbits_le32(&prcm_base->iclken_per, 0x00002000);
  623. #endif
  624. #if defined(CONFIG_OMAP3_GPIO_3)
  625. setbits_le32(&prcm_base->fclken_per, 0x00004000);
  626. setbits_le32(&prcm_base->iclken_per, 0x00004000);
  627. #endif
  628. #if defined(CONFIG_OMAP3_GPIO_4)
  629. setbits_le32(&prcm_base->fclken_per, 0x00008000);
  630. setbits_le32(&prcm_base->iclken_per, 0x00008000);
  631. #endif
  632. #if defined(CONFIG_OMAP3_GPIO_5)
  633. setbits_le32(&prcm_base->fclken_per, 0x00010000);
  634. setbits_le32(&prcm_base->iclken_per, 0x00010000);
  635. #endif
  636. #if defined(CONFIG_OMAP3_GPIO_6)
  637. setbits_le32(&prcm_base->fclken_per, 0x00020000);
  638. setbits_le32(&prcm_base->iclken_per, 0x00020000);
  639. #endif
  640. #ifdef CONFIG_SYS_I2C_OMAP24XX
  641. /* Turn on all 3 I2C clocks */
  642. setbits_le32(&prcm_base->fclken1_core, 0x00038000);
  643. setbits_le32(&prcm_base->iclken1_core, 0x00038000); /* I2C1,2,3 = on */
  644. #endif
  645. /* Enable the ICLK for 32K Sync Timer as its used in udelay */
  646. setbits_le32(&prcm_base->iclken_wkup, 0x00000004);
  647. if (get_cpu_family() != CPU_AM35XX)
  648. out_le32(&prcm_base->fclken_iva2, FCK_IVA2_ON);
  649. out_le32(&prcm_base->fclken1_core, FCK_CORE1_ON);
  650. out_le32(&prcm_base->iclken1_core, ICK_CORE1_ON);
  651. out_le32(&prcm_base->iclken2_core, ICK_CORE2_ON);
  652. out_le32(&prcm_base->fclken_wkup, FCK_WKUP_ON);
  653. out_le32(&prcm_base->iclken_wkup, ICK_WKUP_ON);
  654. out_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
  655. out_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
  656. if (get_cpu_family() != CPU_AM35XX) {
  657. out_le32(&prcm_base->fclken_cam, FCK_CAM_ON);
  658. out_le32(&prcm_base->iclken_cam, ICK_CAM_ON);
  659. }
  660. sdelay(1000);
  661. }