Kconfig 10 KB

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  1. menu "RISC-V architecture"
  2. depends on RISCV
  3. config SYS_ARCH
  4. default "riscv"
  5. choice
  6. prompt "Target select"
  7. optional
  8. config TARGET_AX25_AE350
  9. bool "Support ax25-ae350"
  10. config TARGET_MICROCHIP_ICICLE
  11. bool "Support Microchip PolarFire-SoC Icicle Board"
  12. config TARGET_QEMU_VIRT
  13. bool "Support QEMU Virt Board"
  14. config TARGET_SIFIVE_UNLEASHED
  15. bool "Support SiFive Unleashed Board"
  16. config TARGET_SIFIVE_UNMATCHED
  17. bool "Support SiFive Unmatched Board"
  18. config TARGET_STARFIVE_DEVKITS
  19. bool "Support StarFive DevKits Board"
  20. config TARGET_STARFIVE_VISIONFIVE2
  21. bool "Support StarFive VisionFive2 Board"
  22. config TARGET_STARFIVE_EVB
  23. bool "Support StarFive Evb Board"
  24. config TARGET_SIPEED_MAIX
  25. bool "Support Sipeed Maix Board"
  26. config TARGET_OPENPITON_RISCV64
  27. bool "Support RISC-V cores on OpenPiton SoC"
  28. endchoice
  29. config SYS_ICACHE_OFF
  30. bool "Do not enable icache"
  31. default n
  32. help
  33. Do not enable instruction cache in U-Boot.
  34. config SPL_SYS_ICACHE_OFF
  35. bool "Do not enable icache in SPL"
  36. depends on SPL
  37. default SYS_ICACHE_OFF
  38. help
  39. Do not enable instruction cache in SPL.
  40. config SYS_DCACHE_OFF
  41. bool "Do not enable dcache"
  42. default n
  43. help
  44. Do not enable data cache in U-Boot.
  45. config SPL_SYS_DCACHE_OFF
  46. bool "Do not enable dcache in SPL"
  47. depends on SPL
  48. default SYS_DCACHE_OFF
  49. help
  50. Do not enable data cache in SPL.
  51. # board-specific options below
  52. source "board/AndesTech/ax25-ae350/Kconfig"
  53. source "board/emulation/qemu-riscv/Kconfig"
  54. source "board/microchip/mpfs_icicle/Kconfig"
  55. source "board/sifive/unleashed/Kconfig"
  56. source "board/sifive/unmatched/Kconfig"
  57. source "board/openpiton/riscv64/Kconfig"
  58. source "board/sipeed/maix/Kconfig"
  59. source "board/starfive/devkits/Kconfig"
  60. source "board/starfive/visionfive2/Kconfig"
  61. source "board/starfive/evb/Kconfig"
  62. # platform-specific options below
  63. source "arch/riscv/cpu/ax25/Kconfig"
  64. source "arch/riscv/cpu/fu540/Kconfig"
  65. source "arch/riscv/cpu/fu740/Kconfig"
  66. source "arch/riscv/cpu/generic/Kconfig"
  67. source "arch/riscv/cpu/jh7110/Kconfig"
  68. # architecture-specific options below
  69. choice
  70. prompt "Base ISA"
  71. default ARCH_RV32I
  72. config ARCH_RV32I
  73. bool "RV32I"
  74. select 32BIT
  75. help
  76. Choose this option to target the RV32I base integer instruction set.
  77. config ARCH_RV64I
  78. bool "RV64I"
  79. select 64BIT
  80. select PHYS_64BIT
  81. help
  82. Choose this option to target the RV64I base integer instruction set.
  83. endchoice
  84. choice
  85. prompt "Code Model"
  86. default CMODEL_MEDLOW
  87. config CMODEL_MEDLOW
  88. bool "medium low code model"
  89. help
  90. U-Boot and its statically defined symbols must lie within a single 2 GiB
  91. address range and must lie between absolute addresses -2 GiB and +2 GiB.
  92. config CMODEL_MEDANY
  93. bool "medium any code model"
  94. help
  95. U-Boot and its statically defined symbols must be within any single 2 GiB
  96. address range.
  97. endchoice
  98. choice
  99. prompt "Run Mode"
  100. default RISCV_MMODE
  101. config RISCV_MMODE
  102. bool "Machine"
  103. help
  104. Choose this option to build U-Boot for RISC-V M-Mode.
  105. config RISCV_SMODE
  106. bool "Supervisor"
  107. help
  108. Choose this option to build U-Boot for RISC-V S-Mode.
  109. endchoice
  110. choice
  111. prompt "SPL Run Mode"
  112. default SPL_RISCV_MMODE
  113. depends on SPL
  114. config SPL_RISCV_MMODE
  115. bool "Machine"
  116. help
  117. Choose this option to build U-Boot SPL for RISC-V M-Mode.
  118. config SPL_RISCV_SMODE
  119. bool "Supervisor"
  120. help
  121. Choose this option to build U-Boot SPL for RISC-V S-Mode.
  122. endchoice
  123. config RISCV_ISA_C
  124. bool "Emit compressed instructions"
  125. default y
  126. help
  127. Adds "C" to the ISA subsets that the toolchain is allowed to emit
  128. when building U-Boot, which results in compressed instructions in the
  129. U-Boot binary.
  130. config RISCV_ISA_F
  131. bool "Standard extension for Single-Precision Floating Point"
  132. default y
  133. help
  134. Adds "F" to the ISA string passed to the compiler.
  135. config RISCV_ISA_D
  136. bool "Standard extension for Double-Precision Floating Point"
  137. depends on RISCV_ISA_F
  138. default y
  139. help
  140. Adds "D" to the ISA string passed to the compiler and changes the
  141. riscv32 ABI from ilp32 to ilp32d and the riscv64 ABI from lp64 to
  142. lp64d.
  143. config RISCV_ISA_A
  144. def_bool y
  145. config 32BIT
  146. bool
  147. config 64BIT
  148. bool
  149. config DMA_ADDR_T_64BIT
  150. bool
  151. default y if 64BIT
  152. config SIFIVE_CLINT
  153. bool
  154. depends on RISCV_MMODE
  155. help
  156. The SiFive CLINT block holds memory-mapped control and status registers
  157. associated with software and timer interrupts.
  158. config SPL_SIFIVE_CLINT
  159. bool
  160. depends on SPL_RISCV_MMODE
  161. help
  162. The SiFive CLINT block holds memory-mapped control and status registers
  163. associated with software and timer interrupts.
  164. config SIFIVE_CACHE
  165. bool
  166. help
  167. This enables the operations to configure SiFive cache
  168. config ANDES_PLIC
  169. bool
  170. depends on RISCV_MMODE || SPL_RISCV_MMODE
  171. select REGMAP
  172. select SYSCON
  173. select SPL_REGMAP if SPL
  174. select SPL_SYSCON if SPL
  175. help
  176. The Andes PLIC block holds memory-mapped claim and pending registers
  177. associated with software interrupt.
  178. config SYS_MALLOC_F_LEN
  179. default 0x1000
  180. config SMP
  181. bool "Symmetric Multi-Processing"
  182. depends on SBI_V01 || !RISCV_SMODE
  183. help
  184. This enables support for systems with more than one CPU. If
  185. you say N here, U-Boot will run on single and multiprocessor
  186. machines, but will use only one CPU of a multiprocessor
  187. machine. If you say Y here, U-Boot will run on many, but not
  188. all, single processor machines.
  189. config SPL_SMP
  190. bool "Symmetric Multi-Processing in SPL"
  191. depends on SPL && SPL_RISCV_MMODE
  192. default y
  193. help
  194. This enables support for systems with more than one CPU in SPL.
  195. If you say N here, U-Boot SPL will run on single and multiprocessor
  196. machines, but will use only one CPU of a multiprocessor
  197. machine. If you say Y here, U-Boot SPL will run on many, but not
  198. all, single processor machines.
  199. config NR_CPUS
  200. int "Maximum number of CPUs (2-32)"
  201. range 2 32
  202. depends on SMP || SPL_SMP
  203. default 8
  204. help
  205. On multiprocessor machines, U-Boot sets up a stack for each CPU.
  206. Stack memory is pre-allocated. U-Boot must therefore know the
  207. maximum number of CPUs that may be present.
  208. config SBI
  209. bool
  210. default y if RISCV_SMODE || SPL_RISCV_SMODE
  211. choice
  212. prompt "SBI support"
  213. default SBI_V02
  214. config SBI_V01
  215. bool "SBI v0.1 support"
  216. depends on SBI
  217. help
  218. This config allows kernel to use SBI v0.1 APIs. This will be
  219. deprecated in future once legacy M-mode software are no longer in use.
  220. config SBI_V02
  221. bool "SBI v0.2 support"
  222. depends on SBI
  223. help
  224. This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
  225. scalable and extendable to handle future needs for RISC-V supervisor
  226. interfaces. For example, with SBI v0.2 HSM extension, only a single
  227. hart need to boot and enter operating system. The booting hart can
  228. bring up secondary harts one by one afterwards.
  229. Choose this option if OpenSBI v0.7 or above release is used together
  230. with U-Boot.
  231. endchoice
  232. config SBI_IPI
  233. bool
  234. depends on SBI
  235. default y if RISCV_SMODE || SPL_RISCV_SMODE
  236. depends on SMP
  237. config XIP
  238. bool "XIP mode"
  239. help
  240. XIP (eXecute In Place) is a method for executing code directly
  241. from a NOR flash memory without copying the code to ram.
  242. Say yes here if U-Boot boots from flash directly.
  243. config SHOW_REGS
  244. bool "Show registers on unhandled exception"
  245. config RISCV_PRIV_1_9
  246. bool "Use version 1.9 of the RISC-V priviledged specification"
  247. help
  248. Older versions of the RISC-V priviledged specification had
  249. separate counter enable CSRs for each privilege mode. Writing
  250. to the unified mcounteren CSR on a processor implementing the
  251. old specification will result in an illegal instruction
  252. exception. In addition to counter CSR changes, the way virtual
  253. memory is configured was also changed.
  254. config STACK_SIZE_SHIFT
  255. int
  256. default 14
  257. config OF_BOARD_FIXUP
  258. default y if OF_SEPARATE && RISCV_SMODE
  259. menu "Use assembly optimized implementation of memory routines"
  260. config USE_ARCH_MEMCPY
  261. bool "Use an assembly optimized implementation of memcpy"
  262. default y
  263. help
  264. Enable the generation of an optimized version of memcpy.
  265. Such an implementation may be faster under some conditions
  266. but may increase the binary size.
  267. config SPL_USE_ARCH_MEMCPY
  268. bool "Use an assembly optimized implementation of memcpy for SPL"
  269. default y if USE_ARCH_MEMCPY
  270. depends on SPL
  271. help
  272. Enable the generation of an optimized version of memcpy.
  273. Such an implementation may be faster under some conditions
  274. but may increase the binary size.
  275. config TPL_USE_ARCH_MEMCPY
  276. bool "Use an assembly optimized implementation of memcpy for TPL"
  277. default y if USE_ARCH_MEMCPY
  278. depends on TPL
  279. help
  280. Enable the generation of an optimized version of memcpy.
  281. Such an implementation may be faster under some conditions
  282. but may increase the binary size.
  283. config USE_ARCH_MEMMOVE
  284. bool "Use an assembly optimized implementation of memmove"
  285. default y
  286. help
  287. Enable the generation of an optimized version of memmove.
  288. Such an implementation may be faster under some conditions
  289. but may increase the binary size.
  290. config SPL_USE_ARCH_MEMMOVE
  291. bool "Use an assembly optimized implementation of memmove for SPL"
  292. default y if USE_ARCH_MEMCPY
  293. depends on SPL
  294. help
  295. Enable the generation of an optimized version of memmove.
  296. Such an implementation may be faster under some conditions
  297. but may increase the binary size.
  298. config TPL_USE_ARCH_MEMMOVE
  299. bool "Use an assembly optimized implementation of memmove for TPL"
  300. default y if USE_ARCH_MEMCPY
  301. depends on TPL
  302. help
  303. Enable the generation of an optimized version of memmove.
  304. Such an implementation may be faster under some conditions
  305. but may increase the binary size.
  306. config USE_ARCH_MEMSET
  307. bool "Use an assembly optimized implementation of memset"
  308. default y
  309. help
  310. Enable the generation of an optimized version of memset.
  311. Such an implementation may be faster under some conditions
  312. but may increase the binary size.
  313. config SPL_USE_ARCH_MEMSET
  314. bool "Use an assembly optimized implementation of memset for SPL"
  315. default y if USE_ARCH_MEMSET
  316. depends on SPL
  317. help
  318. Enable the generation of an optimized version of memset.
  319. Such an implementation may be faster under some conditions
  320. but may increase the binary size.
  321. config TPL_USE_ARCH_MEMSET
  322. bool "Use an assembly optimized implementation of memset for TPL"
  323. default y if USE_ARCH_MEMSET
  324. depends on TPL
  325. help
  326. Enable the generation of an optimized version of memset.
  327. Such an implementation may be faster under some conditions
  328. but may increase the binary size.
  329. endmenu
  330. endmenu