MPC8555CDS.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2004, 2011 Freescale Semiconductor.
  4. */
  5. /*
  6. * mpc8555cds board configuration file
  7. *
  8. * Please refer to doc/README.mpc85xxcds for more info.
  9. *
  10. */
  11. #ifndef __CONFIG_H
  12. #define __CONFIG_H
  13. /* High Level Configuration Options */
  14. #define CONFIG_CPM2 1 /* has CPM2 */
  15. #define CONFIG_PCI_INDIRECT_BRIDGE
  16. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  17. #ifndef __ASSEMBLY__
  18. extern unsigned long get_clock_freq(void);
  19. #endif
  20. #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
  21. /*
  22. * These can be toggled for performance analysis, otherwise use default.
  23. */
  24. #define CONFIG_L2_CACHE /* toggle L2 cache */
  25. #define CONFIG_BTB /* toggle branch predition */
  26. #define CONFIG_SYS_CCSRBAR 0xe0000000
  27. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  28. /* DDR Setup */
  29. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
  30. #define CONFIG_DDR_SPD
  31. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  32. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  33. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  34. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  35. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  36. /* I2C addresses of SPD EEPROMs */
  37. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  38. /* Make sure required options are set */
  39. #ifndef CONFIG_SPD_EEPROM
  40. #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
  41. #endif
  42. /*
  43. * Local Bus Definitions
  44. */
  45. /*
  46. * FLASH on the Local Bus
  47. * Two banks, 8M each, using the CFI driver.
  48. * Boot from BR0/OR0 bank at 0xff00_0000
  49. * Alternate BR1/OR1 bank at 0xff80_0000
  50. *
  51. * BR0, BR1:
  52. * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
  53. * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
  54. * Port Size = 16 bits = BRx[19:20] = 10
  55. * Use GPCM = BRx[24:26] = 000
  56. * Valid = BRx[31] = 1
  57. *
  58. * 0 4 8 12 16 20 24 28
  59. * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
  60. * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
  61. *
  62. * OR0, OR1:
  63. * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
  64. * Reserved ORx[17:18] = 11, confusion here?
  65. * CSNT = ORx[20] = 1
  66. * ACS = half cycle delay = ORx[21:22] = 11
  67. * SCY = 6 = ORx[24:27] = 0110
  68. * TRLX = use relaxed timing = ORx[29] = 1
  69. * EAD = use external address latch delay = OR[31] = 1
  70. *
  71. * 0 4 8 12 16 20 24 28
  72. * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
  73. */
  74. #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */
  75. #define CONFIG_SYS_BR0_PRELIM 0xff801001
  76. #define CONFIG_SYS_BR1_PRELIM 0xff001001
  77. #define CONFIG_SYS_OR0_PRELIM 0xff806e65
  78. #define CONFIG_SYS_OR1_PRELIM 0xff806e65
  79. #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
  80. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  81. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
  82. #undef CONFIG_SYS_FLASH_CHECKSUM
  83. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  84. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  85. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  86. #define CONFIG_SYS_FLASH_EMPTY_INFO
  87. /*
  88. * SDRAM on the Local Bus
  89. */
  90. #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
  91. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  92. /*
  93. * Base Register 2 and Option Register 2 configure SDRAM.
  94. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  95. *
  96. * For BR2, need:
  97. * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  98. * port-size = 32-bits = BR2[19:20] = 11
  99. * no parity checking = BR2[21:22] = 00
  100. * SDRAM for MSEL = BR2[24:26] = 011
  101. * Valid = BR[31] = 1
  102. *
  103. * 0 4 8 12 16 20 24 28
  104. * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  105. *
  106. * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  107. * FIXME: the top 17 bits of BR2.
  108. */
  109. #define CONFIG_SYS_BR2_PRELIM 0xf0001861
  110. /*
  111. * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  112. *
  113. * For OR2, need:
  114. * 64MB mask for AM, OR2[0:7] = 1111 1100
  115. * XAM, OR2[17:18] = 11
  116. * 9 columns OR2[19-21] = 010
  117. * 13 rows OR2[23-25] = 100
  118. * EAD set for extra time OR[31] = 1
  119. *
  120. * 0 4 8 12 16 20 24 28
  121. * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  122. */
  123. #define CONFIG_SYS_OR2_PRELIM 0xfc006901
  124. #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
  125. #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
  126. #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  127. #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
  128. /*
  129. * Common settings for all Local Bus SDRAM commands.
  130. * At run time, either BSMA1516 (for CPU 1.1)
  131. * or BSMA1617 (for CPU 1.0) (old)
  132. * is OR'ed in too.
  133. */
  134. #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
  135. | LSDMR_PRETOACT7 \
  136. | LSDMR_ACTTORW7 \
  137. | LSDMR_BL8 \
  138. | LSDMR_WRC4 \
  139. | LSDMR_CL3 \
  140. | LSDMR_RFEN \
  141. )
  142. /*
  143. * The CADMUS registers are connected to CS3 on CDS.
  144. * The new memory map places CADMUS at 0xf8000000.
  145. *
  146. * For BR3, need:
  147. * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
  148. * port-size = 8-bits = BR[19:20] = 01
  149. * no parity checking = BR[21:22] = 00
  150. * GPMC for MSEL = BR[24:26] = 000
  151. * Valid = BR[31] = 1
  152. *
  153. * 0 4 8 12 16 20 24 28
  154. * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
  155. *
  156. * For OR3, need:
  157. * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
  158. * disable buffer ctrl OR[19] = 0
  159. * CSNT OR[20] = 1
  160. * ACS OR[21:22] = 11
  161. * XACS OR[23] = 1
  162. * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
  163. * SETA OR[28] = 0
  164. * TRLX OR[29] = 1
  165. * EHTR OR[30] = 1
  166. * EAD extra time OR[31] = 1
  167. *
  168. * 0 4 8 12 16 20 24 28
  169. * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  170. */
  171. #define CONFIG_FSL_CADMUS
  172. #define CADMUS_BASE_ADDR 0xf8000000
  173. #define CONFIG_SYS_BR3_PRELIM 0xf8000801
  174. #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
  175. #define CONFIG_SYS_INIT_RAM_LOCK 1
  176. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  177. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
  178. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  179. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  180. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  181. #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
  182. /* Serial Port */
  183. #define CONFIG_SYS_NS16550_SERIAL
  184. #define CONFIG_SYS_NS16550_REG_SIZE 1
  185. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  186. #define CONFIG_SYS_BAUDRATE_TABLE \
  187. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  188. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  189. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  190. /*
  191. * I2C
  192. */
  193. #define CONFIG_SYS_I2C
  194. #define CONFIG_SYS_I2C_FSL
  195. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  196. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  197. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  198. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  199. /* EEPROM */
  200. #define CONFIG_ID_EEPROM
  201. #define CONFIG_SYS_I2C_EEPROM_CCID
  202. #define CONFIG_SYS_ID_EEPROM
  203. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  204. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  205. /*
  206. * General PCI
  207. * Addresses are mapped 1-1.
  208. */
  209. #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  210. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  211. #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
  212. #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
  213. #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
  214. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  215. #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
  216. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  217. #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
  218. #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
  219. #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
  220. #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
  221. #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
  222. #define CONFIG_SYS_PCI2_IO_BUS 0x00000000
  223. #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
  224. #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
  225. #ifdef CONFIG_LEGACY
  226. #define BRIDGE_ID 17
  227. #define VIA_ID 2
  228. #else
  229. #define BRIDGE_ID 28
  230. #define VIA_ID 4
  231. #endif
  232. #if defined(CONFIG_PCI)
  233. #define CONFIG_MPC85XX_PCI2
  234. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  235. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  236. #endif /* CONFIG_PCI */
  237. #if defined(CONFIG_TSEC_ENET)
  238. #define CONFIG_TSEC1 1
  239. #define CONFIG_TSEC1_NAME "TSEC0"
  240. #define CONFIG_TSEC2 1
  241. #define CONFIG_TSEC2_NAME "TSEC1"
  242. #define TSEC1_PHY_ADDR 0
  243. #define TSEC2_PHY_ADDR 1
  244. #define TSEC1_PHYIDX 0
  245. #define TSEC2_PHYIDX 0
  246. #define TSEC1_FLAGS TSEC_GIGABIT
  247. #define TSEC2_FLAGS TSEC_GIGABIT
  248. /* Options are: TSEC[0-1] */
  249. #define CONFIG_ETHPRIME "TSEC0"
  250. #endif /* CONFIG_TSEC_ENET */
  251. /*
  252. * Environment
  253. */
  254. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  255. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  256. /*
  257. * BOOTP options
  258. */
  259. #define CONFIG_BOOTP_BOOTFILESIZE
  260. #undef CONFIG_WATCHDOG /* watchdog disabled */
  261. /*
  262. * Miscellaneous configurable options
  263. */
  264. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  265. /*
  266. * For booting Linux, the board info and command line data
  267. * have to be in the first 64 MB of memory, since this is
  268. * the maximum mapped by the Linux kernel during initialization.
  269. */
  270. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
  271. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  272. #if defined(CONFIG_CMD_KGDB)
  273. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  274. #endif
  275. /*
  276. * Environment Configuration
  277. */
  278. #if defined(CONFIG_TSEC_ENET)
  279. #define CONFIG_HAS_ETH0
  280. #define CONFIG_HAS_ETH1
  281. #define CONFIG_HAS_ETH2
  282. #endif
  283. #define CONFIG_IPADDR 192.168.1.253
  284. #define CONFIG_HOSTNAME "unknown"
  285. #define CONFIG_ROOTPATH "/nfsroot"
  286. #define CONFIG_BOOTFILE "your.uImage"
  287. #define CONFIG_SERVERIP 192.168.1.1
  288. #define CONFIG_GATEWAYIP 192.168.1.1
  289. #define CONFIG_NETMASK 255.255.255.0
  290. #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
  291. #define CONFIG_EXTRA_ENV_SETTINGS \
  292. "netdev=eth0\0" \
  293. "consoledev=ttyS1\0" \
  294. "ramdiskaddr=600000\0" \
  295. "ramdiskfile=your.ramdisk.u-boot\0" \
  296. "fdtaddr=400000\0" \
  297. "fdtfile=your.fdt.dtb\0"
  298. #define CONFIG_NFSBOOTCOMMAND \
  299. "setenv bootargs root=/dev/nfs rw " \
  300. "nfsroot=$serverip:$rootpath " \
  301. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  302. "console=$consoledev,$baudrate $othbootargs;" \
  303. "tftp $loadaddr $bootfile;" \
  304. "tftp $fdtaddr $fdtfile;" \
  305. "bootm $loadaddr - $fdtaddr"
  306. #define CONFIG_RAMBOOTCOMMAND \
  307. "setenv bootargs root=/dev/ram rw " \
  308. "console=$consoledev,$baudrate $othbootargs;" \
  309. "tftp $ramdiskaddr $ramdiskfile;" \
  310. "tftp $loadaddr $bootfile;" \
  311. "bootm $loadaddr $ramdiskaddr"
  312. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  313. #endif /* __CONFIG_H */