ls2080ardb.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Freescale Semiconductor
  4. * Copyright 2017 NXP
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <init.h>
  9. #include <malloc.h>
  10. #include <errno.h>
  11. #include <netdev.h>
  12. #include <fsl_ifc.h>
  13. #include <fsl_ddr.h>
  14. #include <asm/global_data.h>
  15. #include <asm/io.h>
  16. #include <hwconfig.h>
  17. #include <fdt_support.h>
  18. #include <linux/libfdt.h>
  19. #include <fsl-mc/fsl_mc.h>
  20. #include <env_internal.h>
  21. #include <efi_loader.h>
  22. #include <i2c.h>
  23. #include <asm/arch/mmu.h>
  24. #include <asm/arch/soc.h>
  25. #include <asm/arch/ppa.h>
  26. #include <fsl_sec.h>
  27. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  28. #ifdef CONFIG_FSL_QIXIS
  29. #include "../common/qixis.h"
  30. #include "ls2080ardb_qixis.h"
  31. #endif
  32. #include "../common/vid.h"
  33. #define PIN_MUX_SEL_SDHC 0x00
  34. #define PIN_MUX_SEL_DSPI 0x0a
  35. #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
  36. DECLARE_GLOBAL_DATA_PTR;
  37. enum {
  38. MUX_TYPE_SDHC,
  39. MUX_TYPE_DSPI,
  40. };
  41. #ifdef CONFIG_VID
  42. u16 soc_get_fuse_vid(int vid_index)
  43. {
  44. static const u16 vdd[32] = {
  45. 10500,
  46. 0, /* reserved */
  47. 9750,
  48. 0, /* reserved */
  49. 9500,
  50. 0, /* reserved */
  51. 0, /* reserved */
  52. 0, /* reserved */
  53. 9000, /* reserved */
  54. 0, /* reserved */
  55. 0, /* reserved */
  56. 0, /* reserved */
  57. 0, /* reserved */
  58. 0, /* reserved */
  59. 0, /* reserved */
  60. 0, /* reserved */
  61. 10000, /* 1.0000V */
  62. 0, /* reserved */
  63. 10250,
  64. 0, /* reserved */
  65. 10500,
  66. 0, /* reserved */
  67. 0, /* reserved */
  68. 0, /* reserved */
  69. 0, /* reserved */
  70. 0, /* reserved */
  71. 0, /* reserved */
  72. 0, /* reserved */
  73. 0, /* reserved */
  74. 0, /* reserved */
  75. 0, /* reserved */
  76. 0, /* reserved */
  77. };
  78. return vdd[vid_index];
  79. };
  80. #endif
  81. unsigned long long get_qixis_addr(void)
  82. {
  83. unsigned long long addr;
  84. if (gd->flags & GD_FLG_RELOC)
  85. addr = QIXIS_BASE_PHYS;
  86. else
  87. addr = QIXIS_BASE_PHYS_EARLY;
  88. /*
  89. * IFC address under 256MB is mapped to 0x30000000, any address above
  90. * is mapped to 0x5_10000000 up to 4GB.
  91. */
  92. addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
  93. return addr;
  94. }
  95. int checkboard(void)
  96. {
  97. #ifdef CONFIG_FSL_QIXIS
  98. u8 sw;
  99. #endif
  100. char buf[15];
  101. cpu_name(buf);
  102. printf("Board: %s-RDB, ", buf);
  103. #ifdef CONFIG_TARGET_LS2081ARDB
  104. #ifdef CONFIG_FSL_QIXIS
  105. sw = QIXIS_READ(arch);
  106. printf("Board version: %c, ", (sw & 0xf) + 'A');
  107. sw = QIXIS_READ(brdcfg[0]);
  108. sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK;
  109. switch (sw) {
  110. case 0:
  111. puts("boot from QSPI DEV#0\n");
  112. puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
  113. break;
  114. case 1:
  115. puts("boot from QSPI DEV#1\n");
  116. puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
  117. break;
  118. case 2:
  119. puts("boot from QSPI EMU\n");
  120. puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
  121. break;
  122. case 3:
  123. puts("boot from QSPI EMU\n");
  124. puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
  125. break;
  126. case 4:
  127. puts("boot from QSPI DEV#0\n");
  128. puts("QSPI_CSA_1 mapped to QSPI EMU\n");
  129. break;
  130. default:
  131. printf("invalid setting of SW%u\n", sw);
  132. break;
  133. }
  134. printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
  135. #endif
  136. puts("SERDES1 Reference : ");
  137. printf("Clock1 = 100MHz ");
  138. printf("Clock2 = 161.13MHz");
  139. #else
  140. #ifdef CONFIG_FSL_QIXIS
  141. sw = QIXIS_READ(arch);
  142. printf("Board Arch: V%d, ", sw >> 4);
  143. printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
  144. sw = QIXIS_READ(brdcfg[0]);
  145. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  146. if (sw < 0x8)
  147. printf("vBank: %d\n", sw);
  148. else if (sw == 0x9)
  149. puts("NAND\n");
  150. else
  151. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  152. printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
  153. #endif
  154. puts("SERDES1 Reference : ");
  155. printf("Clock1 = 156.25MHz ");
  156. printf("Clock2 = 156.25MHz");
  157. #endif
  158. puts("\nSERDES2 Reference : ");
  159. printf("Clock1 = 100MHz ");
  160. printf("Clock2 = 100MHz\n");
  161. return 0;
  162. }
  163. unsigned long get_board_sys_clk(void)
  164. {
  165. #ifdef CONFIG_FSL_QIXIS
  166. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  167. switch (sysclk_conf & 0x0F) {
  168. case QIXIS_SYSCLK_83:
  169. return 83333333;
  170. case QIXIS_SYSCLK_100:
  171. return 100000000;
  172. case QIXIS_SYSCLK_125:
  173. return 125000000;
  174. case QIXIS_SYSCLK_133:
  175. return 133333333;
  176. case QIXIS_SYSCLK_150:
  177. return 150000000;
  178. case QIXIS_SYSCLK_160:
  179. return 160000000;
  180. case QIXIS_SYSCLK_166:
  181. return 166666666;
  182. }
  183. #endif
  184. return 100000000;
  185. }
  186. int select_i2c_ch_pca9547(u8 ch)
  187. {
  188. int ret;
  189. #if !CONFIG_IS_ENABLED(DM_I2C)
  190. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  191. #else
  192. struct udevice *dev;
  193. ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  194. if (!ret)
  195. ret = dm_i2c_write(dev, 0, &ch, 1);
  196. #endif
  197. if (ret) {
  198. puts("PCA: failed to select proper channel\n");
  199. return ret;
  200. }
  201. return 0;
  202. }
  203. int i2c_multiplexer_select_vid_channel(u8 channel)
  204. {
  205. return select_i2c_ch_pca9547(channel);
  206. }
  207. int config_board_mux(int ctrl_type)
  208. {
  209. #ifdef CONFIG_FSL_QIXIS
  210. u8 reg5;
  211. reg5 = QIXIS_READ(brdcfg[5]);
  212. switch (ctrl_type) {
  213. case MUX_TYPE_SDHC:
  214. reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
  215. break;
  216. case MUX_TYPE_DSPI:
  217. reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
  218. break;
  219. default:
  220. printf("Wrong mux interface type\n");
  221. return -1;
  222. }
  223. QIXIS_WRITE(brdcfg[5], reg5);
  224. #endif
  225. return 0;
  226. }
  227. int board_init(void)
  228. {
  229. #ifdef CONFIG_FSL_MC_ENET
  230. u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
  231. #endif
  232. init_final_memctl_regs();
  233. #ifdef CONFIG_ENV_IS_NOWHERE
  234. gd->env_addr = (ulong)&default_environment[0];
  235. #endif
  236. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  237. #ifdef CONFIG_FSL_QIXIS
  238. QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
  239. #endif
  240. #ifdef CONFIG_FSL_CAAM
  241. sec_init();
  242. #endif
  243. #ifdef CONFIG_FSL_LS_PPA
  244. ppa_init();
  245. #endif
  246. #ifdef CONFIG_FSL_MC_ENET
  247. /* invert AQR405 IRQ pins polarity */
  248. out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
  249. #endif
  250. #ifdef CONFIG_FSL_CAAM
  251. sec_init();
  252. #endif
  253. #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
  254. pci_init();
  255. #endif
  256. return 0;
  257. }
  258. int board_early_init_f(void)
  259. {
  260. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  261. i2c_early_init_f();
  262. #endif
  263. fsl_lsch3_early_init_f();
  264. return 0;
  265. }
  266. int misc_init_r(void)
  267. {
  268. char *env_hwconfig;
  269. u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  270. u32 val;
  271. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  272. u32 svr = gur_in32(&gur->svr);
  273. val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
  274. env_hwconfig = env_get("hwconfig");
  275. if (hwconfig_f("dspi", env_hwconfig) &&
  276. DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
  277. config_board_mux(MUX_TYPE_DSPI);
  278. else
  279. config_board_mux(MUX_TYPE_SDHC);
  280. /*
  281. * LS2081ARDB RevF board has smart voltage translator
  282. * which needs to be programmed to enable high speed SD interface
  283. * by setting GPIO4_10 output to zero
  284. */
  285. #ifdef CONFIG_TARGET_LS2081ARDB
  286. out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
  287. in_le32(GPIO4_GPDIR_ADDR)));
  288. out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
  289. in_le32(GPIO4_GPDAT_ADDR)));
  290. #endif
  291. if (hwconfig("sdhc"))
  292. config_board_mux(MUX_TYPE_SDHC);
  293. if (adjust_vdd(0))
  294. printf("Warning: Adjusting core voltage failed.\n");
  295. /*
  296. * Default value of board env is based on filename which is
  297. * ls2080ardb. Modify board env for other supported SoCs
  298. */
  299. if ((SVR_SOC_VER(svr) == SVR_LS2088A) ||
  300. (SVR_SOC_VER(svr) == SVR_LS2048A))
  301. env_set("board", "ls2088ardb");
  302. else if ((SVR_SOC_VER(svr) == SVR_LS2081A) ||
  303. (SVR_SOC_VER(svr) == SVR_LS2041A))
  304. env_set("board", "ls2081ardb");
  305. return 0;
  306. }
  307. void detail_board_ddr_info(void)
  308. {
  309. puts("\nDDR ");
  310. print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
  311. print_ddr_info(0);
  312. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  313. if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
  314. puts("\nDP-DDR ");
  315. print_size(gd->bd->bi_dram[2].size, "");
  316. print_ddr_info(CONFIG_DP_DDR_CTRL);
  317. }
  318. #endif
  319. }
  320. #ifdef CONFIG_FSL_MC_ENET
  321. void fdt_fixup_board_enet(void *fdt)
  322. {
  323. int offset;
  324. offset = fdt_path_offset(fdt, "/soc/fsl-mc");
  325. if (offset < 0)
  326. offset = fdt_path_offset(fdt, "/fsl-mc");
  327. if (offset < 0) {
  328. printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
  329. __func__, offset);
  330. return;
  331. }
  332. if (get_mc_boot_status() == 0 &&
  333. (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
  334. fdt_status_okay(fdt, offset);
  335. else
  336. fdt_status_fail(fdt, offset);
  337. }
  338. void board_quiesce_devices(void)
  339. {
  340. fsl_mc_ldpaa_exit(gd->bd);
  341. }
  342. #endif
  343. #ifdef CONFIG_OF_BOARD_SETUP
  344. void fsl_fdt_fixup_flash(void *fdt)
  345. {
  346. int offset;
  347. #ifdef CONFIG_TFABOOT
  348. u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  349. u32 val;
  350. #endif
  351. /*
  352. * IFC and QSPI are muxed on board.
  353. * So disable IFC node in dts if QSPI is enabled or
  354. * disable QSPI node in dts in case QSPI is not enabled.
  355. */
  356. #ifdef CONFIG_TFABOOT
  357. enum boot_src src = get_boot_src();
  358. bool disable_ifc = false;
  359. switch (src) {
  360. case BOOT_SOURCE_IFC_NOR:
  361. disable_ifc = false;
  362. break;
  363. case BOOT_SOURCE_QSPI_NOR:
  364. disable_ifc = true;
  365. break;
  366. default:
  367. val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
  368. if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
  369. disable_ifc = true;
  370. break;
  371. }
  372. if (disable_ifc) {
  373. offset = fdt_path_offset(fdt, "/soc/ifc");
  374. if (offset < 0)
  375. offset = fdt_path_offset(fdt, "/ifc");
  376. } else {
  377. offset = fdt_path_offset(fdt, "/soc/quadspi");
  378. if (offset < 0)
  379. offset = fdt_path_offset(fdt, "/quadspi");
  380. }
  381. #else
  382. #ifdef CONFIG_FSL_QSPI
  383. offset = fdt_path_offset(fdt, "/soc/ifc");
  384. if (offset < 0)
  385. offset = fdt_path_offset(fdt, "/ifc");
  386. #else
  387. offset = fdt_path_offset(fdt, "/soc/quadspi");
  388. if (offset < 0)
  389. offset = fdt_path_offset(fdt, "/quadspi");
  390. #endif
  391. #endif
  392. if (offset < 0)
  393. return;
  394. fdt_status_disabled(fdt, offset);
  395. }
  396. int ft_board_setup(void *blob, struct bd_info *bd)
  397. {
  398. int i;
  399. u16 mc_memory_bank = 0;
  400. u64 *base;
  401. u64 *size;
  402. u64 mc_memory_base = 0;
  403. u64 mc_memory_size = 0;
  404. u16 total_memory_banks;
  405. ft_cpu_setup(blob, bd);
  406. fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
  407. if (mc_memory_base != 0)
  408. mc_memory_bank++;
  409. total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
  410. base = calloc(total_memory_banks, sizeof(u64));
  411. size = calloc(total_memory_banks, sizeof(u64));
  412. /* fixup DT for the two GPP DDR banks */
  413. base[0] = gd->bd->bi_dram[0].start;
  414. size[0] = gd->bd->bi_dram[0].size;
  415. base[1] = gd->bd->bi_dram[1].start;
  416. size[1] = gd->bd->bi_dram[1].size;
  417. #ifdef CONFIG_RESV_RAM
  418. /* reduce size if reserved memory is within this bank */
  419. if (gd->arch.resv_ram >= base[0] &&
  420. gd->arch.resv_ram < base[0] + size[0])
  421. size[0] = gd->arch.resv_ram - base[0];
  422. else if (gd->arch.resv_ram >= base[1] &&
  423. gd->arch.resv_ram < base[1] + size[1])
  424. size[1] = gd->arch.resv_ram - base[1];
  425. #endif
  426. if (mc_memory_base != 0) {
  427. for (i = 0; i <= total_memory_banks; i++) {
  428. if (base[i] == 0 && size[i] == 0) {
  429. base[i] = mc_memory_base;
  430. size[i] = mc_memory_size;
  431. break;
  432. }
  433. }
  434. }
  435. fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
  436. fdt_fsl_mc_fixup_iommu_map_entry(blob);
  437. fsl_fdt_fixup_dr_usb(blob, bd);
  438. fsl_fdt_fixup_flash(blob);
  439. #ifdef CONFIG_FSL_MC_ENET
  440. fdt_fixup_board_enet(blob);
  441. #endif
  442. fdt_fixup_icid(blob);
  443. return 0;
  444. }
  445. #endif
  446. void qixis_dump_switch(void)
  447. {
  448. #ifdef CONFIG_FSL_QIXIS
  449. int i, nr_of_cfgsw;
  450. QIXIS_WRITE(cms[0], 0x00);
  451. nr_of_cfgsw = QIXIS_READ(cms[1]);
  452. puts("DIP switch settings dump:\n");
  453. for (i = 1; i <= nr_of_cfgsw; i++) {
  454. QIXIS_WRITE(cms[0], i);
  455. printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
  456. }
  457. #endif
  458. }
  459. /*
  460. * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
  461. * Both slots has 0x54, resulting 2nd slot unusable.
  462. */
  463. void update_spd_address(unsigned int ctrl_num,
  464. unsigned int slot,
  465. unsigned int *addr)
  466. {
  467. #ifndef CONFIG_TARGET_LS2081ARDB
  468. #ifdef CONFIG_FSL_QIXIS
  469. u8 sw;
  470. sw = QIXIS_READ(arch);
  471. if ((sw & 0xf) < 0x3) {
  472. if (ctrl_num == 1 && slot == 0)
  473. *addr = SPD_EEPROM_ADDRESS4;
  474. else if (ctrl_num == 1 && slot == 1)
  475. *addr = SPD_EEPROM_ADDRESS3;
  476. }
  477. #endif
  478. #endif
  479. }