cpu_init_early.c 5.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2012 Freescale Semiconductor, Inc
  4. */
  5. #include <common.h>
  6. #include <asm-offsets.h>
  7. #include <asm/global_data.h>
  8. #include <asm/processor.h>
  9. #include <asm/mmu.h>
  10. #include <asm/fsl_law.h>
  11. #include <asm/io.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. #ifdef CONFIG_A003399_NOR_WORKAROUND
  14. void setup_ifc(void)
  15. {
  16. struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
  17. u32 _mas0, _mas1, _mas2, _mas3, _mas7;
  18. phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS;
  19. /*
  20. * Adjust the TLB we were running out of to match the phys addr of the
  21. * chip select we are adjusting and will return to.
  22. */
  23. flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024;
  24. _mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15);
  25. _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT |
  26. MAS1_TSIZE(BOOKE_PAGESZ_4M);
  27. _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
  28. _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
  29. _mas7 = FSL_BOOKE_MAS7(flash_phys);
  30. mtspr(MAS0, _mas0);
  31. mtspr(MAS1, _mas1);
  32. mtspr(MAS2, _mas2);
  33. mtspr(MAS3, _mas3);
  34. mtspr(MAS7, _mas7);
  35. asm volatile("isync;msync;tlbwe;isync");
  36. #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB)
  37. /*
  38. * TLB entry for debuggging in AS1
  39. * Create temporary TLB entry in AS0 to handle debug exception
  40. * As on debug exception MSR is cleared i.e. Address space is changed
  41. * to 0. A TLB entry (in AS0) is required to handle debug exception generated
  42. * in AS1.
  43. *
  44. * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
  45. * bacause flash's physical address is going to change as
  46. * CONFIG_SYS_FLASH_BASE_PHYS.
  47. */
  48. _mas0 = MAS0_TLBSEL(1) |
  49. MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB);
  50. _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_IPROT |
  51. MAS1_TSIZE(BOOKE_PAGESZ_4M);
  52. _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
  53. _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
  54. _mas7 = FSL_BOOKE_MAS7(flash_phys);
  55. mtspr(MAS0, _mas0);
  56. mtspr(MAS1, _mas1);
  57. mtspr(MAS2, _mas2);
  58. mtspr(MAS3, _mas3);
  59. mtspr(MAS7, _mas7);
  60. asm volatile("isync;msync;tlbwe;isync");
  61. #endif
  62. /* Change flash's physical address */
  63. ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
  64. ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
  65. ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
  66. return ;
  67. }
  68. #endif
  69. /* We run cpu_init_early_f in AS = 1 */
  70. void cpu_init_early_f(void *fdt)
  71. {
  72. u32 mas0, mas1, mas2, mas3, mas7;
  73. #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
  74. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  75. #endif
  76. #ifdef CONFIG_A003399_NOR_WORKAROUND
  77. ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
  78. u32 *dst, *src;
  79. void (*setup_ifc_sram)(void);
  80. int i;
  81. #endif
  82. /* Pointer is writable since we allocated a register for it */
  83. gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
  84. /* gd area was zeroed during startup */
  85. #ifdef CONFIG_ARCH_QEMU_E500
  86. /*
  87. * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
  88. * so we need to populate it before it accesses it.
  89. */
  90. gd->fdt_blob = fdt;
  91. #endif
  92. mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
  93. mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
  94. mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
  95. mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
  96. mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
  97. write_tlb(mas0, mas1, mas2, mas3, mas7);
  98. /*
  99. * Work Around for IFC Erratum A-003549. This issue is P1010
  100. * specific. LCLK(a free running clk signal) is muxed with IFC_CS3 on P1010 SOC
  101. * Hence specifically selecting CS3.
  102. */
  103. #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
  104. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3);
  105. #endif
  106. #ifdef CONFIG_FSL_LAW
  107. init_laws();
  108. #endif
  109. /*
  110. * Work Around for IFC Erratum A003399, issue will hit only when execution
  111. * from NOR Flash
  112. */
  113. #ifdef CONFIG_A003399_NOR_WORKAROUND
  114. #define SRAM_BASE_ADDR (0x00000000)
  115. /* TLB for SRAM */
  116. mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9);
  117. mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS |
  118. MAS1_TSIZE(BOOKE_PAGESZ_1M);
  119. mas2 = FSL_BOOKE_MAS2(SRAM_BASE_ADDR, MAS2_I);
  120. mas3 = FSL_BOOKE_MAS3(SRAM_BASE_ADDR, 0, MAS3_SX|MAS3_SW|MAS3_SR);
  121. mas7 = FSL_BOOKE_MAS7(0);
  122. write_tlb(mas0, mas1, mas2, mas3, mas7);
  123. out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR);
  124. out_be32(&l2cache->l2errdis,
  125. (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
  126. out_be32(&l2cache->l2ctl,
  127. (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
  128. /*
  129. * Copy the code in setup_ifc to L2SRAM. Do a word copy
  130. * because NOR Flash on P1010 does not support byte
  131. * access (Erratum IFC-A002769)
  132. */
  133. setup_ifc_sram = (void *)SRAM_BASE_ADDR;
  134. dst = (u32 *) SRAM_BASE_ADDR;
  135. src = (u32 *) setup_ifc;
  136. for (i = 0; i < 1024; i++) {
  137. /* cppcheck-suppress nullPointer */
  138. *dst++ = *src++;
  139. }
  140. /* cppcheck-suppress nullPointer */
  141. setup_ifc_sram();
  142. /* CLEANUP */
  143. clrbits_be32(&l2cache->l2ctl,
  144. (MPC85xx_L2CTL_L2E |
  145. MPC85xx_L2CTL_L2SRAM_ENTIRE));
  146. out_be32(&l2cache->l2srbar0, 0x0);
  147. #endif
  148. invalidate_tlb(1);
  149. #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && \
  150. !(defined(CONFIG_SPL_INIT_MINIMAL) && defined(CONFIG_SPL_BUILD)) && \
  151. !defined(CONFIG_NAND_SPL)
  152. disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB);
  153. #endif
  154. init_tlbs();
  155. }