Kconfig 30 KB

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  1. menu "mpc85xx CPU"
  2. depends on MPC85xx
  3. config SYS_CPU
  4. default "mpc85xx"
  5. config CMD_ERRATA
  6. bool "Enable the 'errata' command"
  7. depends on MPC85xx
  8. default y
  9. help
  10. This enables the 'errata' command which displays a list of errata
  11. work-arounds which are enabled for the current board.
  12. choice
  13. prompt "Target select"
  14. optional
  15. config TARGET_SBC8548
  16. bool "Support sbc8548"
  17. select ARCH_MPC8548
  18. config TARGET_SOCRATES
  19. bool "Support socrates"
  20. select ARCH_MPC8544
  21. config TARGET_P3041DS
  22. bool "Support P3041DS"
  23. select PHYS_64BIT
  24. select ARCH_P3041
  25. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  26. imply CMD_SATA
  27. imply PANIC_HANG
  28. config TARGET_P4080DS
  29. bool "Support P4080DS"
  30. select PHYS_64BIT
  31. select ARCH_P4080
  32. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  33. imply CMD_SATA
  34. imply PANIC_HANG
  35. config TARGET_P5040DS
  36. bool "Support P5040DS"
  37. select PHYS_64BIT
  38. select ARCH_P5040
  39. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  40. imply CMD_SATA
  41. imply PANIC_HANG
  42. config TARGET_MPC8541CDS
  43. bool "Support MPC8541CDS"
  44. select ARCH_MPC8541
  45. select FSL_VIA
  46. config TARGET_MPC8548CDS
  47. bool "Support MPC8548CDS"
  48. select ARCH_MPC8548
  49. select FSL_VIA
  50. config TARGET_MPC8555CDS
  51. bool "Support MPC8555CDS"
  52. select ARCH_MPC8555
  53. select FSL_VIA
  54. config TARGET_MPC8568MDS
  55. bool "Support MPC8568MDS"
  56. select ARCH_MPC8568
  57. config TARGET_P1010RDB_PA
  58. bool "Support P1010RDB_PA"
  59. select ARCH_P1010
  60. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  61. select SUPPORT_SPL
  62. select SUPPORT_TPL
  63. imply CMD_EEPROM
  64. imply CMD_SATA
  65. imply PANIC_HANG
  66. config TARGET_P1010RDB_PB
  67. bool "Support P1010RDB_PB"
  68. select ARCH_P1010
  69. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  70. select SUPPORT_SPL
  71. select SUPPORT_TPL
  72. imply CMD_EEPROM
  73. imply CMD_SATA
  74. imply PANIC_HANG
  75. config TARGET_P1020RDB_PC
  76. bool "Support P1020RDB-PC"
  77. select SUPPORT_SPL
  78. select SUPPORT_TPL
  79. select ARCH_P1020
  80. imply CMD_EEPROM
  81. imply CMD_SATA
  82. imply PANIC_HANG
  83. config TARGET_P1020RDB_PD
  84. bool "Support P1020RDB-PD"
  85. select SUPPORT_SPL
  86. select SUPPORT_TPL
  87. select ARCH_P1020
  88. imply CMD_EEPROM
  89. imply CMD_SATA
  90. imply PANIC_HANG
  91. config TARGET_P2020RDB
  92. bool "Support P2020RDB-PC"
  93. select SUPPORT_SPL
  94. select SUPPORT_TPL
  95. select ARCH_P2020
  96. imply CMD_EEPROM
  97. imply CMD_SATA
  98. imply SATA_SIL
  99. config TARGET_P2041RDB
  100. bool "Support P2041RDB"
  101. select ARCH_P2041
  102. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  103. select PHYS_64BIT
  104. imply CMD_SATA
  105. imply FSL_SATA
  106. config TARGET_QEMU_PPCE500
  107. bool "Support qemu-ppce500"
  108. select ARCH_QEMU_E500
  109. select PHYS_64BIT
  110. config TARGET_T1023RDB
  111. bool "Support T1023RDB"
  112. select ARCH_T1023
  113. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  114. select SUPPORT_SPL
  115. select PHYS_64BIT
  116. select FSL_DDR_INTERACTIVE
  117. imply CMD_EEPROM
  118. imply PANIC_HANG
  119. config TARGET_T1024RDB
  120. bool "Support T1024RDB"
  121. select ARCH_T1024
  122. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  123. select SUPPORT_SPL
  124. select PHYS_64BIT
  125. select FSL_DDR_INTERACTIVE
  126. imply CMD_EEPROM
  127. imply PANIC_HANG
  128. config TARGET_T1040RDB
  129. bool "Support T1040RDB"
  130. select ARCH_T1040
  131. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  132. select SUPPORT_SPL
  133. select PHYS_64BIT
  134. imply CMD_SATA
  135. imply PANIC_HANG
  136. config TARGET_T1040D4RDB
  137. bool "Support T1040D4RDB"
  138. select ARCH_T1040
  139. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  140. select SUPPORT_SPL
  141. select PHYS_64BIT
  142. imply CMD_SATA
  143. imply PANIC_HANG
  144. config TARGET_T1042RDB
  145. bool "Support T1042RDB"
  146. select ARCH_T1042
  147. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  148. select SUPPORT_SPL
  149. select PHYS_64BIT
  150. imply CMD_SATA
  151. config TARGET_T1042D4RDB
  152. bool "Support T1042D4RDB"
  153. select ARCH_T1042
  154. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  155. select SUPPORT_SPL
  156. select PHYS_64BIT
  157. imply CMD_SATA
  158. imply PANIC_HANG
  159. config TARGET_T1042RDB_PI
  160. bool "Support T1042RDB_PI"
  161. select ARCH_T1042
  162. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  163. select SUPPORT_SPL
  164. select PHYS_64BIT
  165. imply CMD_SATA
  166. imply PANIC_HANG
  167. config TARGET_T2080QDS
  168. bool "Support T2080QDS"
  169. select ARCH_T2080
  170. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  171. select SUPPORT_SPL
  172. select PHYS_64BIT
  173. select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  174. select FSL_DDR_INTERACTIVE
  175. imply CMD_SATA
  176. config TARGET_T2080RDB
  177. bool "Support T2080RDB"
  178. select ARCH_T2080
  179. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  180. select SUPPORT_SPL
  181. select PHYS_64BIT
  182. imply CMD_SATA
  183. imply PANIC_HANG
  184. config TARGET_T2081QDS
  185. bool "Support T2081QDS"
  186. select ARCH_T2081
  187. select SUPPORT_SPL
  188. select PHYS_64BIT
  189. select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  190. select FSL_DDR_INTERACTIVE
  191. config TARGET_T4160RDB
  192. bool "Support T4160RDB"
  193. select ARCH_T4160
  194. select SUPPORT_SPL
  195. select PHYS_64BIT
  196. imply PANIC_HANG
  197. config TARGET_T4240RDB
  198. bool "Support T4240RDB"
  199. select ARCH_T4240
  200. select SUPPORT_SPL
  201. select PHYS_64BIT
  202. select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  203. imply CMD_SATA
  204. imply PANIC_HANG
  205. config TARGET_CONTROLCENTERD
  206. bool "Support controlcenterd"
  207. select ARCH_P1022
  208. config TARGET_KMP204X
  209. bool "Support kmp204x"
  210. select VENDOR_KM
  211. config TARGET_KMCENT2
  212. bool "Support kmcent2"
  213. select VENDOR_KM
  214. config TARGET_XPEDITE520X
  215. bool "Support xpedite520x"
  216. select ARCH_MPC8548
  217. config TARGET_XPEDITE537X
  218. bool "Support xpedite537x"
  219. select ARCH_MPC8572
  220. # Use DDR3 controller with DDR2 DIMMs on this board
  221. select SYS_FSL_DDRC_GEN3
  222. config TARGET_XPEDITE550X
  223. bool "Support xpedite550x"
  224. select ARCH_P2020
  225. config TARGET_UCP1020
  226. bool "Support uCP1020"
  227. select ARCH_P1020
  228. imply CMD_SATA
  229. imply PANIC_HANG
  230. config TARGET_CYRUS_P5020
  231. bool "Support Varisys Cyrus P5020"
  232. select ARCH_P5020
  233. select PHYS_64BIT
  234. imply PANIC_HANG
  235. config TARGET_CYRUS_P5040
  236. bool "Support Varisys Cyrus P5040"
  237. select ARCH_P5040
  238. select PHYS_64BIT
  239. imply PANIC_HANG
  240. endchoice
  241. config ARCH_B4420
  242. bool
  243. select E500MC
  244. select E6500
  245. select FSL_LAW
  246. select SYS_FSL_DDR_VER_47
  247. select SYS_FSL_ERRATUM_A004477
  248. select SYS_FSL_ERRATUM_A005871
  249. select SYS_FSL_ERRATUM_A006379
  250. select SYS_FSL_ERRATUM_A006384
  251. select SYS_FSL_ERRATUM_A006475
  252. select SYS_FSL_ERRATUM_A006593
  253. select SYS_FSL_ERRATUM_A007075
  254. select SYS_FSL_ERRATUM_A007186
  255. select SYS_FSL_ERRATUM_A007212
  256. select SYS_FSL_ERRATUM_A009942
  257. select SYS_FSL_HAS_DDR3
  258. select SYS_FSL_HAS_SEC
  259. select SYS_FSL_QORIQ_CHASSIS2
  260. select SYS_FSL_SEC_BE
  261. select SYS_FSL_SEC_COMPAT_4
  262. select SYS_PPC64
  263. select FSL_IFC
  264. imply CMD_EEPROM
  265. imply CMD_NAND
  266. imply CMD_REGINFO
  267. config ARCH_B4860
  268. bool
  269. select E500MC
  270. select E6500
  271. select FSL_LAW
  272. select SYS_FSL_DDR_VER_47
  273. select SYS_FSL_ERRATUM_A004477
  274. select SYS_FSL_ERRATUM_A005871
  275. select SYS_FSL_ERRATUM_A006379
  276. select SYS_FSL_ERRATUM_A006384
  277. select SYS_FSL_ERRATUM_A006475
  278. select SYS_FSL_ERRATUM_A006593
  279. select SYS_FSL_ERRATUM_A007075
  280. select SYS_FSL_ERRATUM_A007186
  281. select SYS_FSL_ERRATUM_A007212
  282. select SYS_FSL_ERRATUM_A007907
  283. select SYS_FSL_ERRATUM_A009942
  284. select SYS_FSL_HAS_DDR3
  285. select SYS_FSL_HAS_SEC
  286. select SYS_FSL_QORIQ_CHASSIS2
  287. select SYS_FSL_SEC_BE
  288. select SYS_FSL_SEC_COMPAT_4
  289. select SYS_PPC64
  290. select FSL_IFC
  291. imply CMD_EEPROM
  292. imply CMD_NAND
  293. imply CMD_REGINFO
  294. config ARCH_BSC9131
  295. bool
  296. select FSL_LAW
  297. select SYS_FSL_DDR_VER_44
  298. select SYS_FSL_ERRATUM_A004477
  299. select SYS_FSL_ERRATUM_A005125
  300. select SYS_FSL_ERRATUM_ESDHC111
  301. select SYS_FSL_HAS_DDR3
  302. select SYS_FSL_HAS_SEC
  303. select SYS_FSL_SEC_BE
  304. select SYS_FSL_SEC_COMPAT_4
  305. select FSL_IFC
  306. imply CMD_EEPROM
  307. imply CMD_NAND
  308. imply CMD_REGINFO
  309. config ARCH_BSC9132
  310. bool
  311. select FSL_LAW
  312. select SYS_FSL_DDR_VER_46
  313. select SYS_FSL_ERRATUM_A004477
  314. select SYS_FSL_ERRATUM_A005125
  315. select SYS_FSL_ERRATUM_A005434
  316. select SYS_FSL_ERRATUM_ESDHC111
  317. select SYS_FSL_ERRATUM_I2C_A004447
  318. select SYS_FSL_ERRATUM_IFC_A002769
  319. select FSL_PCIE_RESET
  320. select SYS_FSL_HAS_DDR3
  321. select SYS_FSL_HAS_SEC
  322. select SYS_FSL_SEC_BE
  323. select SYS_FSL_SEC_COMPAT_4
  324. select SYS_PPC_E500_USE_DEBUG_TLB
  325. select FSL_IFC
  326. imply CMD_EEPROM
  327. imply CMD_MTDPARTS
  328. imply CMD_NAND
  329. imply CMD_PCI
  330. imply CMD_REGINFO
  331. config ARCH_C29X
  332. bool
  333. select FSL_LAW
  334. select SYS_FSL_DDR_VER_46
  335. select SYS_FSL_ERRATUM_A005125
  336. select SYS_FSL_ERRATUM_ESDHC111
  337. select FSL_PCIE_RESET
  338. select SYS_FSL_HAS_DDR3
  339. select SYS_FSL_HAS_SEC
  340. select SYS_FSL_SEC_BE
  341. select SYS_FSL_SEC_COMPAT_6
  342. select SYS_PPC_E500_USE_DEBUG_TLB
  343. select FSL_IFC
  344. imply CMD_NAND
  345. imply CMD_PCI
  346. imply CMD_REGINFO
  347. config ARCH_MPC8536
  348. bool
  349. select FSL_LAW
  350. select SYS_FSL_ERRATUM_A004508
  351. select SYS_FSL_ERRATUM_A005125
  352. select FSL_PCIE_RESET
  353. select SYS_FSL_HAS_DDR2
  354. select SYS_FSL_HAS_DDR3
  355. select SYS_FSL_HAS_SEC
  356. select SYS_FSL_SEC_BE
  357. select SYS_FSL_SEC_COMPAT_2
  358. select SYS_PPC_E500_USE_DEBUG_TLB
  359. select FSL_ELBC
  360. imply CMD_NAND
  361. imply CMD_SATA
  362. imply CMD_REGINFO
  363. config ARCH_MPC8540
  364. bool
  365. select FSL_LAW
  366. select SYS_FSL_HAS_DDR1
  367. config ARCH_MPC8541
  368. bool
  369. select FSL_LAW
  370. select SYS_FSL_HAS_DDR1
  371. select SYS_FSL_HAS_SEC
  372. select SYS_FSL_SEC_BE
  373. select SYS_FSL_SEC_COMPAT_2
  374. config ARCH_MPC8544
  375. bool
  376. select FSL_LAW
  377. select SYS_FSL_ERRATUM_A005125
  378. select FSL_PCIE_RESET
  379. select SYS_FSL_HAS_DDR2
  380. select SYS_FSL_HAS_SEC
  381. select SYS_FSL_SEC_BE
  382. select SYS_FSL_SEC_COMPAT_2
  383. select SYS_PPC_E500_USE_DEBUG_TLB
  384. select FSL_ELBC
  385. config ARCH_MPC8548
  386. bool
  387. select FSL_LAW
  388. select SYS_FSL_ERRATUM_A005125
  389. select SYS_FSL_ERRATUM_NMG_DDR120
  390. select SYS_FSL_ERRATUM_NMG_LBC103
  391. select SYS_FSL_ERRATUM_NMG_ETSEC129
  392. select SYS_FSL_ERRATUM_I2C_A004447
  393. select FSL_PCIE_RESET
  394. select SYS_FSL_HAS_DDR2
  395. select SYS_FSL_HAS_DDR1
  396. select SYS_FSL_HAS_SEC
  397. select SYS_FSL_SEC_BE
  398. select SYS_FSL_SEC_COMPAT_2
  399. select SYS_PPC_E500_USE_DEBUG_TLB
  400. imply CMD_REGINFO
  401. config ARCH_MPC8555
  402. bool
  403. select FSL_LAW
  404. select SYS_FSL_HAS_DDR1
  405. select SYS_FSL_HAS_SEC
  406. select SYS_FSL_SEC_BE
  407. select SYS_FSL_SEC_COMPAT_2
  408. config ARCH_MPC8560
  409. bool
  410. select FSL_LAW
  411. select SYS_FSL_HAS_DDR1
  412. config ARCH_MPC8568
  413. bool
  414. select FSL_LAW
  415. select FSL_PCIE_RESET
  416. select SYS_FSL_HAS_DDR2
  417. select SYS_FSL_HAS_SEC
  418. select SYS_FSL_SEC_BE
  419. select SYS_FSL_SEC_COMPAT_2
  420. config ARCH_MPC8572
  421. bool
  422. select FSL_LAW
  423. select SYS_FSL_ERRATUM_A004508
  424. select SYS_FSL_ERRATUM_A005125
  425. select SYS_FSL_ERRATUM_DDR_115
  426. select SYS_FSL_ERRATUM_DDR111_DDR134
  427. select FSL_PCIE_RESET
  428. select SYS_FSL_HAS_DDR2
  429. select SYS_FSL_HAS_DDR3
  430. select SYS_FSL_HAS_SEC
  431. select SYS_FSL_SEC_BE
  432. select SYS_FSL_SEC_COMPAT_2
  433. select SYS_PPC_E500_USE_DEBUG_TLB
  434. select FSL_ELBC
  435. imply CMD_NAND
  436. config ARCH_P1010
  437. bool
  438. select FSL_LAW
  439. select SYS_FSL_ERRATUM_A004477
  440. select SYS_FSL_ERRATUM_A004508
  441. select SYS_FSL_ERRATUM_A005125
  442. select SYS_FSL_ERRATUM_A005275
  443. select SYS_FSL_ERRATUM_A006261
  444. select SYS_FSL_ERRATUM_A007075
  445. select SYS_FSL_ERRATUM_ESDHC111
  446. select SYS_FSL_ERRATUM_I2C_A004447
  447. select SYS_FSL_ERRATUM_IFC_A002769
  448. select SYS_FSL_ERRATUM_P1010_A003549
  449. select SYS_FSL_ERRATUM_SEC_A003571
  450. select SYS_FSL_ERRATUM_IFC_A003399
  451. select FSL_PCIE_RESET
  452. select SYS_FSL_HAS_DDR3
  453. select SYS_FSL_HAS_SEC
  454. select SYS_FSL_SEC_BE
  455. select SYS_FSL_SEC_COMPAT_4
  456. select SYS_PPC_E500_USE_DEBUG_TLB
  457. select FSL_IFC
  458. imply CMD_EEPROM
  459. imply CMD_MTDPARTS
  460. imply CMD_NAND
  461. imply CMD_SATA
  462. imply CMD_PCI
  463. imply CMD_REGINFO
  464. imply FSL_SATA
  465. config ARCH_P1011
  466. bool
  467. select FSL_LAW
  468. select SYS_FSL_ERRATUM_A004508
  469. select SYS_FSL_ERRATUM_A005125
  470. select SYS_FSL_ERRATUM_ELBC_A001
  471. select SYS_FSL_ERRATUM_ESDHC111
  472. select FSL_PCIE_DISABLE_ASPM
  473. select SYS_FSL_HAS_DDR3
  474. select SYS_FSL_HAS_SEC
  475. select SYS_FSL_SEC_BE
  476. select SYS_FSL_SEC_COMPAT_2
  477. select SYS_PPC_E500_USE_DEBUG_TLB
  478. select FSL_ELBC
  479. config ARCH_P1020
  480. bool
  481. select FSL_LAW
  482. select SYS_FSL_ERRATUM_A004508
  483. select SYS_FSL_ERRATUM_A005125
  484. select SYS_FSL_ERRATUM_ELBC_A001
  485. select SYS_FSL_ERRATUM_ESDHC111
  486. select FSL_PCIE_DISABLE_ASPM
  487. select FSL_PCIE_RESET
  488. select SYS_FSL_HAS_DDR3
  489. select SYS_FSL_HAS_SEC
  490. select SYS_FSL_SEC_BE
  491. select SYS_FSL_SEC_COMPAT_2
  492. select SYS_PPC_E500_USE_DEBUG_TLB
  493. select FSL_ELBC
  494. imply CMD_NAND
  495. imply CMD_SATA
  496. imply CMD_PCI
  497. imply CMD_REGINFO
  498. imply SATA_SIL
  499. config ARCH_P1021
  500. bool
  501. select FSL_LAW
  502. select SYS_FSL_ERRATUM_A004508
  503. select SYS_FSL_ERRATUM_A005125
  504. select SYS_FSL_ERRATUM_ELBC_A001
  505. select SYS_FSL_ERRATUM_ESDHC111
  506. select FSL_PCIE_DISABLE_ASPM
  507. select FSL_PCIE_RESET
  508. select SYS_FSL_HAS_DDR3
  509. select SYS_FSL_HAS_SEC
  510. select SYS_FSL_SEC_BE
  511. select SYS_FSL_SEC_COMPAT_2
  512. select SYS_PPC_E500_USE_DEBUG_TLB
  513. select FSL_ELBC
  514. imply CMD_REGINFO
  515. imply CMD_NAND
  516. imply CMD_SATA
  517. imply CMD_REGINFO
  518. imply SATA_SIL
  519. config ARCH_P1022
  520. bool
  521. select FSL_LAW
  522. select SYS_FSL_ERRATUM_A004477
  523. select SYS_FSL_ERRATUM_A004508
  524. select SYS_FSL_ERRATUM_A005125
  525. select SYS_FSL_ERRATUM_ELBC_A001
  526. select SYS_FSL_ERRATUM_ESDHC111
  527. select SYS_FSL_ERRATUM_SATA_A001
  528. select FSL_PCIE_RESET
  529. select SYS_FSL_HAS_DDR3
  530. select SYS_FSL_HAS_SEC
  531. select SYS_FSL_SEC_BE
  532. select SYS_FSL_SEC_COMPAT_2
  533. select SYS_PPC_E500_USE_DEBUG_TLB
  534. select FSL_ELBC
  535. config ARCH_P1023
  536. bool
  537. select FSL_LAW
  538. select SYS_FSL_ERRATUM_A004508
  539. select SYS_FSL_ERRATUM_A005125
  540. select SYS_FSL_ERRATUM_I2C_A004447
  541. select FSL_PCIE_RESET
  542. select SYS_FSL_HAS_DDR3
  543. select SYS_FSL_HAS_SEC
  544. select SYS_FSL_SEC_BE
  545. select SYS_FSL_SEC_COMPAT_4
  546. select FSL_ELBC
  547. config ARCH_P1024
  548. bool
  549. select FSL_LAW
  550. select SYS_FSL_ERRATUM_A004508
  551. select SYS_FSL_ERRATUM_A005125
  552. select SYS_FSL_ERRATUM_ELBC_A001
  553. select SYS_FSL_ERRATUM_ESDHC111
  554. select FSL_PCIE_DISABLE_ASPM
  555. select FSL_PCIE_RESET
  556. select SYS_FSL_HAS_DDR3
  557. select SYS_FSL_HAS_SEC
  558. select SYS_FSL_SEC_BE
  559. select SYS_FSL_SEC_COMPAT_2
  560. select SYS_PPC_E500_USE_DEBUG_TLB
  561. select FSL_ELBC
  562. imply CMD_EEPROM
  563. imply CMD_NAND
  564. imply CMD_SATA
  565. imply CMD_PCI
  566. imply CMD_REGINFO
  567. imply SATA_SIL
  568. config ARCH_P1025
  569. bool
  570. select FSL_LAW
  571. select SYS_FSL_ERRATUM_A004508
  572. select SYS_FSL_ERRATUM_A005125
  573. select SYS_FSL_ERRATUM_ELBC_A001
  574. select SYS_FSL_ERRATUM_ESDHC111
  575. select FSL_PCIE_DISABLE_ASPM
  576. select FSL_PCIE_RESET
  577. select SYS_FSL_HAS_DDR3
  578. select SYS_FSL_HAS_SEC
  579. select SYS_FSL_SEC_BE
  580. select SYS_FSL_SEC_COMPAT_2
  581. select SYS_PPC_E500_USE_DEBUG_TLB
  582. select FSL_ELBC
  583. imply CMD_SATA
  584. imply CMD_REGINFO
  585. config ARCH_P2020
  586. bool
  587. select FSL_LAW
  588. select SYS_FSL_ERRATUM_A004477
  589. select SYS_FSL_ERRATUM_A004508
  590. select SYS_FSL_ERRATUM_A005125
  591. select SYS_FSL_ERRATUM_ESDHC111
  592. select SYS_FSL_ERRATUM_ESDHC_A001
  593. select FSL_PCIE_RESET
  594. select SYS_FSL_HAS_DDR3
  595. select SYS_FSL_HAS_SEC
  596. select SYS_FSL_SEC_BE
  597. select SYS_FSL_SEC_COMPAT_2
  598. select SYS_PPC_E500_USE_DEBUG_TLB
  599. select FSL_ELBC
  600. imply CMD_EEPROM
  601. imply CMD_NAND
  602. imply CMD_REGINFO
  603. config ARCH_P2041
  604. bool
  605. select E500MC
  606. select FSL_LAW
  607. select SYS_FSL_ERRATUM_A004510
  608. select SYS_FSL_ERRATUM_A004849
  609. select SYS_FSL_ERRATUM_A005275
  610. select SYS_FSL_ERRATUM_A006261
  611. select SYS_FSL_ERRATUM_CPU_A003999
  612. select SYS_FSL_ERRATUM_DDR_A003
  613. select SYS_FSL_ERRATUM_DDR_A003474
  614. select SYS_FSL_ERRATUM_ESDHC111
  615. select SYS_FSL_ERRATUM_I2C_A004447
  616. select SYS_FSL_ERRATUM_NMG_CPU_A011
  617. select SYS_FSL_ERRATUM_SRIO_A004034
  618. select SYS_FSL_ERRATUM_USB14
  619. select SYS_FSL_HAS_DDR3
  620. select SYS_FSL_HAS_SEC
  621. select SYS_FSL_QORIQ_CHASSIS1
  622. select SYS_FSL_SEC_BE
  623. select SYS_FSL_SEC_COMPAT_4
  624. select FSL_ELBC
  625. imply CMD_NAND
  626. config ARCH_P3041
  627. bool
  628. select E500MC
  629. select FSL_LAW
  630. select SYS_FSL_DDR_VER_44
  631. select SYS_FSL_ERRATUM_A004510
  632. select SYS_FSL_ERRATUM_A004849
  633. select SYS_FSL_ERRATUM_A005275
  634. select SYS_FSL_ERRATUM_A005812
  635. select SYS_FSL_ERRATUM_A006261
  636. select SYS_FSL_ERRATUM_CPU_A003999
  637. select SYS_FSL_ERRATUM_DDR_A003
  638. select SYS_FSL_ERRATUM_DDR_A003474
  639. select SYS_FSL_ERRATUM_ESDHC111
  640. select SYS_FSL_ERRATUM_I2C_A004447
  641. select SYS_FSL_ERRATUM_NMG_CPU_A011
  642. select SYS_FSL_ERRATUM_SRIO_A004034
  643. select SYS_FSL_ERRATUM_USB14
  644. select SYS_FSL_HAS_DDR3
  645. select SYS_FSL_HAS_SEC
  646. select SYS_FSL_QORIQ_CHASSIS1
  647. select SYS_FSL_SEC_BE
  648. select SYS_FSL_SEC_COMPAT_4
  649. select FSL_ELBC
  650. imply CMD_NAND
  651. imply CMD_SATA
  652. imply CMD_REGINFO
  653. imply FSL_SATA
  654. config ARCH_P4080
  655. bool
  656. select E500MC
  657. select FSL_LAW
  658. select SYS_FSL_DDR_VER_44
  659. select SYS_FSL_ERRATUM_A004510
  660. select SYS_FSL_ERRATUM_A004580
  661. select SYS_FSL_ERRATUM_A004849
  662. select SYS_FSL_ERRATUM_A005812
  663. select SYS_FSL_ERRATUM_A007075
  664. select SYS_FSL_ERRATUM_CPC_A002
  665. select SYS_FSL_ERRATUM_CPC_A003
  666. select SYS_FSL_ERRATUM_CPU_A003999
  667. select SYS_FSL_ERRATUM_DDR_A003
  668. select SYS_FSL_ERRATUM_DDR_A003474
  669. select SYS_FSL_ERRATUM_ELBC_A001
  670. select SYS_FSL_ERRATUM_ESDHC111
  671. select SYS_FSL_ERRATUM_ESDHC13
  672. select SYS_FSL_ERRATUM_ESDHC135
  673. select SYS_FSL_ERRATUM_I2C_A004447
  674. select SYS_FSL_ERRATUM_NMG_CPU_A011
  675. select SYS_FSL_ERRATUM_SRIO_A004034
  676. select SYS_P4080_ERRATUM_CPU22
  677. select SYS_P4080_ERRATUM_PCIE_A003
  678. select SYS_P4080_ERRATUM_SERDES8
  679. select SYS_P4080_ERRATUM_SERDES9
  680. select SYS_P4080_ERRATUM_SERDES_A001
  681. select SYS_P4080_ERRATUM_SERDES_A005
  682. select SYS_FSL_HAS_DDR3
  683. select SYS_FSL_HAS_SEC
  684. select SYS_FSL_QORIQ_CHASSIS1
  685. select SYS_FSL_SEC_BE
  686. select SYS_FSL_SEC_COMPAT_4
  687. select FSL_ELBC
  688. imply CMD_SATA
  689. imply CMD_REGINFO
  690. imply SATA_SIL
  691. config ARCH_P5020
  692. bool
  693. select E500MC
  694. select FSL_LAW
  695. select SYS_FSL_DDR_VER_44
  696. select SYS_FSL_ERRATUM_A004510
  697. select SYS_FSL_ERRATUM_A005275
  698. select SYS_FSL_ERRATUM_A006261
  699. select SYS_FSL_ERRATUM_DDR_A003
  700. select SYS_FSL_ERRATUM_DDR_A003474
  701. select SYS_FSL_ERRATUM_ESDHC111
  702. select SYS_FSL_ERRATUM_I2C_A004447
  703. select SYS_FSL_ERRATUM_SRIO_A004034
  704. select SYS_FSL_ERRATUM_USB14
  705. select SYS_FSL_HAS_DDR3
  706. select SYS_FSL_HAS_SEC
  707. select SYS_FSL_QORIQ_CHASSIS1
  708. select SYS_FSL_SEC_BE
  709. select SYS_FSL_SEC_COMPAT_4
  710. select SYS_PPC64
  711. select FSL_ELBC
  712. imply CMD_SATA
  713. imply CMD_REGINFO
  714. imply FSL_SATA
  715. config ARCH_P5040
  716. bool
  717. select E500MC
  718. select FSL_LAW
  719. select SYS_FSL_DDR_VER_44
  720. select SYS_FSL_ERRATUM_A004510
  721. select SYS_FSL_ERRATUM_A004699
  722. select SYS_FSL_ERRATUM_A005275
  723. select SYS_FSL_ERRATUM_A005812
  724. select SYS_FSL_ERRATUM_A006261
  725. select SYS_FSL_ERRATUM_DDR_A003
  726. select SYS_FSL_ERRATUM_DDR_A003474
  727. select SYS_FSL_ERRATUM_ESDHC111
  728. select SYS_FSL_ERRATUM_USB14
  729. select SYS_FSL_HAS_DDR3
  730. select SYS_FSL_HAS_SEC
  731. select SYS_FSL_QORIQ_CHASSIS1
  732. select SYS_FSL_SEC_BE
  733. select SYS_FSL_SEC_COMPAT_4
  734. select SYS_PPC64
  735. select FSL_ELBC
  736. imply CMD_SATA
  737. imply CMD_REGINFO
  738. imply FSL_SATA
  739. config ARCH_QEMU_E500
  740. bool
  741. config ARCH_T1023
  742. bool
  743. select E500MC
  744. select FSL_LAW
  745. select SYS_FSL_DDR_VER_50
  746. select SYS_FSL_ERRATUM_A008378
  747. select SYS_FSL_ERRATUM_A008109
  748. select SYS_FSL_ERRATUM_A009663
  749. select SYS_FSL_ERRATUM_A009942
  750. select SYS_FSL_ERRATUM_ESDHC111
  751. select SYS_FSL_HAS_DDR3
  752. select SYS_FSL_HAS_DDR4
  753. select SYS_FSL_HAS_SEC
  754. select SYS_FSL_QORIQ_CHASSIS2
  755. select SYS_FSL_SEC_BE
  756. select SYS_FSL_SEC_COMPAT_5
  757. select FSL_IFC
  758. imply CMD_EEPROM
  759. imply CMD_NAND
  760. imply CMD_REGINFO
  761. config ARCH_T1024
  762. bool
  763. select E500MC
  764. select FSL_LAW
  765. select SYS_FSL_DDR_VER_50
  766. select SYS_FSL_ERRATUM_A008378
  767. select SYS_FSL_ERRATUM_A008109
  768. select SYS_FSL_ERRATUM_A009663
  769. select SYS_FSL_ERRATUM_A009942
  770. select SYS_FSL_ERRATUM_ESDHC111
  771. select SYS_FSL_HAS_DDR3
  772. select SYS_FSL_HAS_DDR4
  773. select SYS_FSL_HAS_SEC
  774. select SYS_FSL_QORIQ_CHASSIS2
  775. select SYS_FSL_SEC_BE
  776. select SYS_FSL_SEC_COMPAT_5
  777. select FSL_IFC
  778. imply CMD_EEPROM
  779. imply CMD_NAND
  780. imply CMD_MTDPARTS
  781. imply CMD_REGINFO
  782. config ARCH_T1040
  783. bool
  784. select E500MC
  785. select FSL_LAW
  786. select SYS_FSL_DDR_VER_50
  787. select SYS_FSL_ERRATUM_A008044
  788. select SYS_FSL_ERRATUM_A008378
  789. select SYS_FSL_ERRATUM_A008109
  790. select SYS_FSL_ERRATUM_A009663
  791. select SYS_FSL_ERRATUM_A009942
  792. select SYS_FSL_ERRATUM_ESDHC111
  793. select SYS_FSL_HAS_DDR3
  794. select SYS_FSL_HAS_DDR4
  795. select SYS_FSL_HAS_SEC
  796. select SYS_FSL_QORIQ_CHASSIS2
  797. select SYS_FSL_SEC_BE
  798. select SYS_FSL_SEC_COMPAT_5
  799. select FSL_IFC
  800. imply CMD_MTDPARTS
  801. imply CMD_NAND
  802. imply CMD_SATA
  803. imply CMD_REGINFO
  804. imply FSL_SATA
  805. config ARCH_T1042
  806. bool
  807. select E500MC
  808. select FSL_LAW
  809. select SYS_FSL_DDR_VER_50
  810. select SYS_FSL_ERRATUM_A008044
  811. select SYS_FSL_ERRATUM_A008378
  812. select SYS_FSL_ERRATUM_A008109
  813. select SYS_FSL_ERRATUM_A009663
  814. select SYS_FSL_ERRATUM_A009942
  815. select SYS_FSL_ERRATUM_ESDHC111
  816. select SYS_FSL_HAS_DDR3
  817. select SYS_FSL_HAS_DDR4
  818. select SYS_FSL_HAS_SEC
  819. select SYS_FSL_QORIQ_CHASSIS2
  820. select SYS_FSL_SEC_BE
  821. select SYS_FSL_SEC_COMPAT_5
  822. select FSL_IFC
  823. imply CMD_MTDPARTS
  824. imply CMD_NAND
  825. imply CMD_SATA
  826. imply CMD_REGINFO
  827. imply FSL_SATA
  828. config ARCH_T2080
  829. bool
  830. select E500MC
  831. select E6500
  832. select FSL_LAW
  833. select SYS_FSL_DDR_VER_47
  834. select SYS_FSL_ERRATUM_A006379
  835. select SYS_FSL_ERRATUM_A006593
  836. select SYS_FSL_ERRATUM_A007186
  837. select SYS_FSL_ERRATUM_A007212
  838. select SYS_FSL_ERRATUM_A007815
  839. select SYS_FSL_ERRATUM_A007907
  840. select SYS_FSL_ERRATUM_A008109
  841. select SYS_FSL_ERRATUM_A009942
  842. select SYS_FSL_ERRATUM_ESDHC111
  843. select FSL_PCIE_RESET
  844. select SYS_FSL_HAS_DDR3
  845. select SYS_FSL_HAS_SEC
  846. select SYS_FSL_QORIQ_CHASSIS2
  847. select SYS_FSL_SEC_BE
  848. select SYS_FSL_SEC_COMPAT_4
  849. select SYS_PPC64
  850. select FSL_IFC
  851. imply CMD_SATA
  852. imply CMD_NAND
  853. imply CMD_REGINFO
  854. imply FSL_SATA
  855. config ARCH_T2081
  856. bool
  857. select E500MC
  858. select E6500
  859. select FSL_LAW
  860. select SYS_FSL_DDR_VER_47
  861. select SYS_FSL_ERRATUM_A006379
  862. select SYS_FSL_ERRATUM_A006593
  863. select SYS_FSL_ERRATUM_A007186
  864. select SYS_FSL_ERRATUM_A007212
  865. select SYS_FSL_ERRATUM_A009942
  866. select SYS_FSL_ERRATUM_ESDHC111
  867. select FSL_PCIE_RESET
  868. select SYS_FSL_HAS_DDR3
  869. select SYS_FSL_HAS_SEC
  870. select SYS_FSL_QORIQ_CHASSIS2
  871. select SYS_FSL_SEC_BE
  872. select SYS_FSL_SEC_COMPAT_4
  873. select SYS_PPC64
  874. select FSL_IFC
  875. imply CMD_NAND
  876. imply CMD_REGINFO
  877. config ARCH_T4160
  878. bool
  879. select E500MC
  880. select E6500
  881. select FSL_LAW
  882. select SYS_FSL_DDR_VER_47
  883. select SYS_FSL_ERRATUM_A004468
  884. select SYS_FSL_ERRATUM_A005871
  885. select SYS_FSL_ERRATUM_A006379
  886. select SYS_FSL_ERRATUM_A006593
  887. select SYS_FSL_ERRATUM_A007186
  888. select SYS_FSL_ERRATUM_A007798
  889. select SYS_FSL_ERRATUM_A009942
  890. select SYS_FSL_HAS_DDR3
  891. select SYS_FSL_HAS_SEC
  892. select SYS_FSL_QORIQ_CHASSIS2
  893. select SYS_FSL_SEC_BE
  894. select SYS_FSL_SEC_COMPAT_4
  895. select SYS_PPC64
  896. select FSL_IFC
  897. imply CMD_SATA
  898. imply CMD_NAND
  899. imply CMD_REGINFO
  900. imply FSL_SATA
  901. config ARCH_T4240
  902. bool
  903. select E500MC
  904. select E6500
  905. select FSL_LAW
  906. select SYS_FSL_DDR_VER_47
  907. select SYS_FSL_ERRATUM_A004468
  908. select SYS_FSL_ERRATUM_A005871
  909. select SYS_FSL_ERRATUM_A006261
  910. select SYS_FSL_ERRATUM_A006379
  911. select SYS_FSL_ERRATUM_A006593
  912. select SYS_FSL_ERRATUM_A007186
  913. select SYS_FSL_ERRATUM_A007798
  914. select SYS_FSL_ERRATUM_A007815
  915. select SYS_FSL_ERRATUM_A007907
  916. select SYS_FSL_ERRATUM_A008109
  917. select SYS_FSL_ERRATUM_A009942
  918. select SYS_FSL_HAS_DDR3
  919. select SYS_FSL_HAS_SEC
  920. select SYS_FSL_QORIQ_CHASSIS2
  921. select SYS_FSL_SEC_BE
  922. select SYS_FSL_SEC_COMPAT_4
  923. select SYS_PPC64
  924. select FSL_IFC
  925. imply CMD_SATA
  926. imply CMD_NAND
  927. imply CMD_REGINFO
  928. imply FSL_SATA
  929. config MPC85XX_HAVE_RESET_VECTOR
  930. bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
  931. depends on MPC85xx
  932. config BOOKE
  933. bool
  934. default y
  935. config E500
  936. bool
  937. default y
  938. help
  939. Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
  940. config E500MC
  941. bool
  942. imply CMD_PCI
  943. help
  944. Enble PowerPC E500MC core
  945. config E6500
  946. bool
  947. help
  948. Enable PowerPC E6500 core
  949. config FSL_LAW
  950. bool
  951. help
  952. Use Freescale common code for Local Access Window
  953. config NXP_ESBC
  954. bool "NXP_ESBC"
  955. help
  956. Enable Freescale Secure Boot feature. Normally selected
  957. by defconfig. If unsure, do not change.
  958. config MAX_CPUS
  959. int "Maximum number of CPUs permitted for MPC85xx"
  960. default 12 if ARCH_T4240
  961. default 8 if ARCH_P4080 || \
  962. ARCH_T4160
  963. default 4 if ARCH_B4860 || \
  964. ARCH_P2041 || \
  965. ARCH_P3041 || \
  966. ARCH_P5040 || \
  967. ARCH_T1040 || \
  968. ARCH_T1042 || \
  969. ARCH_T2080 || \
  970. ARCH_T2081
  971. default 2 if ARCH_B4420 || \
  972. ARCH_BSC9132 || \
  973. ARCH_MPC8572 || \
  974. ARCH_P1020 || \
  975. ARCH_P1021 || \
  976. ARCH_P1022 || \
  977. ARCH_P1023 || \
  978. ARCH_P1024 || \
  979. ARCH_P1025 || \
  980. ARCH_P2020 || \
  981. ARCH_P5020 || \
  982. ARCH_T1023 || \
  983. ARCH_T1024
  984. default 1
  985. help
  986. Set this number to the maximum number of possible CPUs in the SoC.
  987. SoCs may have multiple clusters with each cluster may have multiple
  988. ports. If some ports are reserved but higher ports are used for
  989. cores, count the reserved ports. This will allocate enough memory
  990. in spin table to properly handle all cores.
  991. config SYS_CCSRBAR_DEFAULT
  992. hex "Default CCSRBAR address"
  993. default 0xff700000 if ARCH_BSC9131 || \
  994. ARCH_BSC9132 || \
  995. ARCH_C29X || \
  996. ARCH_MPC8536 || \
  997. ARCH_MPC8540 || \
  998. ARCH_MPC8541 || \
  999. ARCH_MPC8544 || \
  1000. ARCH_MPC8548 || \
  1001. ARCH_MPC8555 || \
  1002. ARCH_MPC8560 || \
  1003. ARCH_MPC8568 || \
  1004. ARCH_MPC8572 || \
  1005. ARCH_P1010 || \
  1006. ARCH_P1011 || \
  1007. ARCH_P1020 || \
  1008. ARCH_P1021 || \
  1009. ARCH_P1022 || \
  1010. ARCH_P1024 || \
  1011. ARCH_P1025 || \
  1012. ARCH_P2020
  1013. default 0xff600000 if ARCH_P1023
  1014. default 0xfe000000 if ARCH_B4420 || \
  1015. ARCH_B4860 || \
  1016. ARCH_P2041 || \
  1017. ARCH_P3041 || \
  1018. ARCH_P4080 || \
  1019. ARCH_P5020 || \
  1020. ARCH_P5040 || \
  1021. ARCH_T1023 || \
  1022. ARCH_T1024 || \
  1023. ARCH_T1040 || \
  1024. ARCH_T1042 || \
  1025. ARCH_T2080 || \
  1026. ARCH_T2081 || \
  1027. ARCH_T4160 || \
  1028. ARCH_T4240
  1029. default 0xe0000000 if ARCH_QEMU_E500
  1030. help
  1031. Default value of CCSRBAR comes from power-on-reset. It
  1032. is fixed on each SoC. Some SoCs can have different value
  1033. if changed by pre-boot regime. The value here must match
  1034. the current value in SoC. If not sure, do not change.
  1035. config SYS_FSL_ERRATUM_A004468
  1036. bool
  1037. config SYS_FSL_ERRATUM_A004477
  1038. bool
  1039. config SYS_FSL_ERRATUM_A004508
  1040. bool
  1041. config SYS_FSL_ERRATUM_A004580
  1042. bool
  1043. config SYS_FSL_ERRATUM_A004699
  1044. bool
  1045. config SYS_FSL_ERRATUM_A004849
  1046. bool
  1047. config SYS_FSL_ERRATUM_A004510
  1048. bool
  1049. config SYS_FSL_ERRATUM_A004510_SVR_REV
  1050. hex
  1051. depends on SYS_FSL_ERRATUM_A004510
  1052. default 0x20 if ARCH_P4080
  1053. default 0x10
  1054. config SYS_FSL_ERRATUM_A004510_SVR_REV2
  1055. hex
  1056. depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
  1057. default 0x11
  1058. config SYS_FSL_ERRATUM_A005125
  1059. bool
  1060. config SYS_FSL_ERRATUM_A005434
  1061. bool
  1062. config SYS_FSL_ERRATUM_A005812
  1063. bool
  1064. config SYS_FSL_ERRATUM_A005871
  1065. bool
  1066. config SYS_FSL_ERRATUM_A005275
  1067. bool
  1068. config SYS_FSL_ERRATUM_A006261
  1069. bool
  1070. config SYS_FSL_ERRATUM_A006379
  1071. bool
  1072. config SYS_FSL_ERRATUM_A006384
  1073. bool
  1074. config SYS_FSL_ERRATUM_A006475
  1075. bool
  1076. config SYS_FSL_ERRATUM_A006593
  1077. bool
  1078. config SYS_FSL_ERRATUM_A007075
  1079. bool
  1080. config SYS_FSL_ERRATUM_A007186
  1081. bool
  1082. config SYS_FSL_ERRATUM_A007212
  1083. bool
  1084. config SYS_FSL_ERRATUM_A007815
  1085. bool
  1086. config SYS_FSL_ERRATUM_A007798
  1087. bool
  1088. config SYS_FSL_ERRATUM_A007907
  1089. bool
  1090. config SYS_FSL_ERRATUM_A008044
  1091. bool
  1092. config SYS_FSL_ERRATUM_CPC_A002
  1093. bool
  1094. config SYS_FSL_ERRATUM_CPC_A003
  1095. bool
  1096. config SYS_FSL_ERRATUM_CPU_A003999
  1097. bool
  1098. config SYS_FSL_ERRATUM_ELBC_A001
  1099. bool
  1100. config SYS_FSL_ERRATUM_I2C_A004447
  1101. bool
  1102. config SYS_FSL_A004447_SVR_REV
  1103. hex
  1104. depends on SYS_FSL_ERRATUM_I2C_A004447
  1105. default 0x00 if ARCH_MPC8548
  1106. default 0x10 if ARCH_P1010
  1107. default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
  1108. default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
  1109. config SYS_FSL_ERRATUM_IFC_A002769
  1110. bool
  1111. config SYS_FSL_ERRATUM_IFC_A003399
  1112. bool
  1113. config SYS_FSL_ERRATUM_NMG_CPU_A011
  1114. bool
  1115. config SYS_FSL_ERRATUM_NMG_ETSEC129
  1116. bool
  1117. config SYS_FSL_ERRATUM_NMG_LBC103
  1118. bool
  1119. config SYS_FSL_ERRATUM_P1010_A003549
  1120. bool
  1121. config SYS_FSL_ERRATUM_SATA_A001
  1122. bool
  1123. config SYS_FSL_ERRATUM_SEC_A003571
  1124. bool
  1125. config SYS_FSL_ERRATUM_SRIO_A004034
  1126. bool
  1127. config SYS_FSL_ERRATUM_USB14
  1128. bool
  1129. config SYS_P4080_ERRATUM_CPU22
  1130. bool
  1131. config SYS_P4080_ERRATUM_PCIE_A003
  1132. bool
  1133. config SYS_P4080_ERRATUM_SERDES8
  1134. bool
  1135. config SYS_P4080_ERRATUM_SERDES9
  1136. bool
  1137. config SYS_P4080_ERRATUM_SERDES_A001
  1138. bool
  1139. config SYS_P4080_ERRATUM_SERDES_A005
  1140. bool
  1141. config FSL_PCIE_DISABLE_ASPM
  1142. bool
  1143. config FSL_PCIE_RESET
  1144. bool
  1145. config SYS_FSL_QORIQ_CHASSIS1
  1146. bool
  1147. config SYS_FSL_QORIQ_CHASSIS2
  1148. bool
  1149. config SYS_FSL_NUM_LAWS
  1150. int "Number of local access windows"
  1151. depends on FSL_LAW
  1152. default 32 if ARCH_B4420 || \
  1153. ARCH_B4860 || \
  1154. ARCH_P2041 || \
  1155. ARCH_P3041 || \
  1156. ARCH_P4080 || \
  1157. ARCH_P5020 || \
  1158. ARCH_P5040 || \
  1159. ARCH_T2080 || \
  1160. ARCH_T2081 || \
  1161. ARCH_T4160 || \
  1162. ARCH_T4240
  1163. default 16 if ARCH_T1023 || \
  1164. ARCH_T1024 || \
  1165. ARCH_T1040 || \
  1166. ARCH_T1042
  1167. default 12 if ARCH_BSC9131 || \
  1168. ARCH_BSC9132 || \
  1169. ARCH_C29X || \
  1170. ARCH_MPC8536 || \
  1171. ARCH_MPC8572 || \
  1172. ARCH_P1010 || \
  1173. ARCH_P1011 || \
  1174. ARCH_P1020 || \
  1175. ARCH_P1021 || \
  1176. ARCH_P1022 || \
  1177. ARCH_P1023 || \
  1178. ARCH_P1024 || \
  1179. ARCH_P1025 || \
  1180. ARCH_P2020
  1181. default 10 if ARCH_MPC8544 || \
  1182. ARCH_MPC8548 || \
  1183. ARCH_MPC8568
  1184. default 8 if ARCH_MPC8540 || \
  1185. ARCH_MPC8541 || \
  1186. ARCH_MPC8555 || \
  1187. ARCH_MPC8560
  1188. help
  1189. Number of local access windows. This is fixed per SoC.
  1190. If not sure, do not change.
  1191. config SYS_FSL_THREADS_PER_CORE
  1192. int
  1193. default 2 if E6500
  1194. default 1
  1195. config SYS_NUM_TLBCAMS
  1196. int "Number of TLB CAM entries"
  1197. default 64 if E500MC
  1198. default 16
  1199. help
  1200. Number of TLB CAM entries for Book-E chips. 64 for E500MC,
  1201. 16 for other E500 SoCs.
  1202. config SYS_PPC64
  1203. bool
  1204. config SYS_PPC_E500_USE_DEBUG_TLB
  1205. bool
  1206. config FSL_IFC
  1207. bool
  1208. config FSL_ELBC
  1209. bool
  1210. config SYS_PPC_E500_DEBUG_TLB
  1211. int "Temporary TLB entry for external debugger"
  1212. depends on SYS_PPC_E500_USE_DEBUG_TLB
  1213. default 0 if ARCH_MPC8544 || ARCH_MPC8548
  1214. default 1 if ARCH_MPC8536
  1215. default 2 if ARCH_MPC8572 || \
  1216. ARCH_P1011 || \
  1217. ARCH_P1020 || \
  1218. ARCH_P1021 || \
  1219. ARCH_P1022 || \
  1220. ARCH_P1024 || \
  1221. ARCH_P1025 || \
  1222. ARCH_P2020
  1223. default 3 if ARCH_P1010 || \
  1224. ARCH_BSC9132 || \
  1225. ARCH_C29X
  1226. help
  1227. Select a temporary TLB entry to be used during boot to work
  1228. around limitations in e500v1 and e500v2 external debugger
  1229. support. This reduces the portions of the boot code where
  1230. breakpoints and single stepping do not work. The value of this
  1231. symbol should be set to the TLB1 entry to be used for this
  1232. purpose. If unsure, do not change.
  1233. config SYS_FSL_IFC_CLK_DIV
  1234. int "Divider of platform clock"
  1235. depends on FSL_IFC
  1236. default 2 if ARCH_B4420 || \
  1237. ARCH_B4860 || \
  1238. ARCH_T1024 || \
  1239. ARCH_T1023 || \
  1240. ARCH_T1040 || \
  1241. ARCH_T1042 || \
  1242. ARCH_T4160 || \
  1243. ARCH_T4240
  1244. default 1
  1245. help
  1246. Defines divider of platform clock(clock input to
  1247. IFC controller).
  1248. config SYS_FSL_LBC_CLK_DIV
  1249. int "Divider of platform clock"
  1250. depends on FSL_ELBC || ARCH_MPC8540 || \
  1251. ARCH_MPC8548 || ARCH_MPC8541 || \
  1252. ARCH_MPC8555 || ARCH_MPC8560 || \
  1253. ARCH_MPC8568
  1254. default 2 if ARCH_P2041 || \
  1255. ARCH_P3041 || \
  1256. ARCH_P4080 || \
  1257. ARCH_P5020 || \
  1258. ARCH_P5040
  1259. default 1
  1260. help
  1261. Defines divider of platform clock(clock input to
  1262. eLBC controller).
  1263. config FSL_VIA
  1264. bool
  1265. source "board/emulation/qemu-ppce500/Kconfig"
  1266. source "board/freescale/corenet_ds/Kconfig"
  1267. source "board/freescale/mpc8541cds/Kconfig"
  1268. source "board/freescale/mpc8548cds/Kconfig"
  1269. source "board/freescale/mpc8555cds/Kconfig"
  1270. source "board/freescale/mpc8568mds/Kconfig"
  1271. source "board/freescale/p1010rdb/Kconfig"
  1272. source "board/freescale/p1_p2_rdb_pc/Kconfig"
  1273. source "board/freescale/p2041rdb/Kconfig"
  1274. source "board/freescale/t102xrdb/Kconfig"
  1275. source "board/freescale/t104xrdb/Kconfig"
  1276. source "board/freescale/t208xqds/Kconfig"
  1277. source "board/freescale/t208xrdb/Kconfig"
  1278. source "board/freescale/t4rdb/Kconfig"
  1279. source "board/gdsys/p1022/Kconfig"
  1280. source "board/keymile/Kconfig"
  1281. source "board/sbc8548/Kconfig"
  1282. source "board/socrates/Kconfig"
  1283. source "board/varisys/cyrus/Kconfig"
  1284. source "board/xes/xpedite520x/Kconfig"
  1285. source "board/xes/xpedite537x/Kconfig"
  1286. source "board/xes/xpedite550x/Kconfig"
  1287. source "board/Arcturus/ucp1020/Kconfig"
  1288. endmenu