Kconfig 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652
  1. config ARCH_LS1012A
  2. bool
  3. select ARMV8_SET_SMPEN
  4. select ARM_ERRATA_855873 if !TFABOOT
  5. select FSL_LAYERSCAPE
  6. select FSL_LSCH2
  7. select SYS_FSL_SRDS_1
  8. select SYS_HAS_SERDES
  9. select SYS_FSL_DDR_BE
  10. select SYS_FSL_MMDC
  11. select SYS_FSL_ERRATUM_A010315
  12. select SYS_FSL_ERRATUM_A009798
  13. select SYS_FSL_ERRATUM_A008997
  14. select SYS_FSL_ERRATUM_A009007
  15. select SYS_FSL_ERRATUM_A009008
  16. select ARCH_EARLY_INIT_R
  17. select BOARD_EARLY_INIT_F
  18. select SYS_I2C_MXC
  19. select SYS_I2C_MXC_I2C1 if !DM_I2C
  20. select SYS_I2C_MXC_I2C2 if !DM_I2C
  21. imply PANIC_HANG
  22. config ARCH_LS1028A
  23. bool
  24. select ARMV8_SET_SMPEN
  25. select FSL_LAYERSCAPE
  26. select FSL_LSCH3
  27. select NXP_LSCH3_2
  28. select SYS_FSL_HAS_CCI400
  29. select SYS_FSL_SRDS_1
  30. select SYS_HAS_SERDES
  31. select SYS_FSL_DDR
  32. select SYS_FSL_DDR_LE
  33. select SYS_FSL_DDR_VER_50
  34. select SYS_FSL_HAS_DDR3
  35. select SYS_FSL_HAS_DDR4
  36. select SYS_FSL_HAS_SEC
  37. select SYS_FSL_SEC_COMPAT_5
  38. select SYS_FSL_SEC_LE
  39. select FSL_TZASC_1
  40. select ARCH_EARLY_INIT_R
  41. select BOARD_EARLY_INIT_F
  42. select SYS_I2C_MXC
  43. select SYS_FSL_ERRATUM_A008997
  44. select SYS_FSL_ERRATUM_A009007
  45. select SYS_FSL_ERRATUM_A008514 if !TFABOOT
  46. select SYS_FSL_ERRATUM_A009663 if !TFABOOT
  47. select SYS_FSL_ERRATUM_A009942 if !TFABOOT
  48. select SYS_FSL_ERRATUM_A050382
  49. select RESV_RAM if GIC_V3_ITS
  50. imply PANIC_HANG
  51. config ARCH_LS1043A
  52. bool
  53. select ARMV8_SET_SMPEN
  54. select ARM_ERRATA_855873 if !TFABOOT
  55. select FSL_LAYERSCAPE
  56. select FSL_LSCH2
  57. select SYS_FSL_SRDS_1
  58. select SYS_HAS_SERDES
  59. select SYS_FSL_DDR
  60. select SYS_FSL_DDR_BE
  61. select SYS_FSL_DDR_VER_50
  62. select SYS_FSL_ERRATUM_A008850 if !TFABOOT
  63. select SYS_FSL_ERRATUM_A008997
  64. select SYS_FSL_ERRATUM_A009007
  65. select SYS_FSL_ERRATUM_A009008
  66. select SYS_FSL_ERRATUM_A009660 if !TFABOOT
  67. select SYS_FSL_ERRATUM_A009663 if !TFABOOT
  68. select SYS_FSL_ERRATUM_A009798
  69. select SYS_FSL_ERRATUM_A009942 if !TFABOOT
  70. select SYS_FSL_ERRATUM_A010315
  71. select SYS_FSL_ERRATUM_A010539
  72. select SYS_FSL_HAS_DDR3
  73. select SYS_FSL_HAS_DDR4
  74. select ARCH_EARLY_INIT_R
  75. select BOARD_EARLY_INIT_F
  76. select SYS_I2C_MXC
  77. select SYS_I2C_MXC_I2C1 if !DM_I2C
  78. select SYS_I2C_MXC_I2C2 if !DM_I2C
  79. select SYS_I2C_MXC_I2C3 if !DM_I2C
  80. select SYS_I2C_MXC_I2C4 if !DM_I2C
  81. imply CMD_PCI
  82. config ARCH_LS1046A
  83. bool
  84. select ARMV8_SET_SMPEN
  85. select FSL_LAYERSCAPE
  86. select FSL_LSCH2
  87. select SYS_FSL_SRDS_1
  88. select SYS_HAS_SERDES
  89. select SYS_FSL_DDR
  90. select SYS_FSL_DDR_BE
  91. select SYS_FSL_DDR_VER_50
  92. select SYS_FSL_ERRATUM_A008336 if !TFABOOT
  93. select SYS_FSL_ERRATUM_A008511 if !TFABOOT
  94. select SYS_FSL_ERRATUM_A008850 if !TFABOOT
  95. select SYS_FSL_ERRATUM_A008997
  96. select SYS_FSL_ERRATUM_A009007
  97. select SYS_FSL_ERRATUM_A009008
  98. select SYS_FSL_ERRATUM_A009798
  99. select SYS_FSL_ERRATUM_A009801
  100. select SYS_FSL_ERRATUM_A009803 if !TFABOOT
  101. select SYS_FSL_ERRATUM_A009942 if !TFABOOT
  102. select SYS_FSL_ERRATUM_A010165 if !TFABOOT
  103. select SYS_FSL_ERRATUM_A010539
  104. select SYS_FSL_HAS_DDR4
  105. select SYS_FSL_SRDS_2
  106. select ARCH_EARLY_INIT_R
  107. select BOARD_EARLY_INIT_F
  108. select SYS_I2C_MXC
  109. select SYS_I2C_MXC_I2C1 if !DM_I2C
  110. select SYS_I2C_MXC_I2C2 if !DM_I2C
  111. select SYS_I2C_MXC_I2C3 if !DM_I2C
  112. select SYS_I2C_MXC_I2C4 if !DM_I2C
  113. imply SCSI
  114. imply SCSI_AHCI
  115. config ARCH_LS1088A
  116. bool
  117. select ARMV8_SET_SMPEN
  118. select ARM_ERRATA_855873 if !TFABOOT
  119. select FSL_LAYERSCAPE
  120. select FSL_LSCH3
  121. select SYS_FSL_SRDS_1
  122. select SYS_HAS_SERDES
  123. select SYS_FSL_DDR
  124. select SYS_FSL_DDR_LE
  125. select SYS_FSL_DDR_VER_50
  126. select SYS_FSL_EC1
  127. select SYS_FSL_EC2
  128. select SYS_FSL_ERRATUM_A009803 if !TFABOOT
  129. select SYS_FSL_ERRATUM_A009942 if !TFABOOT
  130. select SYS_FSL_ERRATUM_A010165 if !TFABOOT
  131. select SYS_FSL_ERRATUM_A008511 if !TFABOOT
  132. select SYS_FSL_ERRATUM_A008850 if !TFABOOT
  133. select SYS_FSL_ERRATUM_A009007
  134. select SYS_FSL_HAS_CCI400
  135. select SYS_FSL_HAS_DDR4
  136. select SYS_FSL_HAS_RGMII
  137. select SYS_FSL_HAS_SEC
  138. select SYS_FSL_SEC_COMPAT_5
  139. select SYS_FSL_SEC_LE
  140. select SYS_FSL_SRDS_1
  141. select SYS_FSL_SRDS_2
  142. select FSL_TZASC_1
  143. select FSL_TZASC_400
  144. select FSL_TZPC_BP147
  145. select ARCH_EARLY_INIT_R
  146. select BOARD_EARLY_INIT_F
  147. select SYS_I2C_MXC
  148. select SYS_I2C_MXC_I2C1 if !TFABOOT
  149. select SYS_I2C_MXC_I2C2 if !TFABOOT
  150. select SYS_I2C_MXC_I2C3 if !TFABOOT
  151. select SYS_I2C_MXC_I2C4 if !TFABOOT
  152. select RESV_RAM if GIC_V3_ITS
  153. imply SCSI
  154. imply PANIC_HANG
  155. config ARCH_LS2080A
  156. bool
  157. select ARMV8_SET_SMPEN
  158. select ARM_ERRATA_826974
  159. select ARM_ERRATA_828024
  160. select ARM_ERRATA_829520
  161. select ARM_ERRATA_833471
  162. select FSL_LAYERSCAPE
  163. select FSL_LSCH3
  164. select SYS_FSL_SRDS_1
  165. select SYS_HAS_SERDES
  166. select SYS_FSL_DDR
  167. select SYS_FSL_DDR_LE
  168. select SYS_FSL_DDR_VER_50
  169. select SYS_FSL_HAS_CCN504
  170. select SYS_FSL_HAS_DP_DDR
  171. select SYS_FSL_HAS_SEC
  172. select SYS_FSL_HAS_DDR4
  173. select SYS_FSL_SEC_COMPAT_5
  174. select SYS_FSL_SEC_LE
  175. select SYS_FSL_SRDS_2
  176. select FSL_TZASC_1
  177. select FSL_TZASC_2
  178. select FSL_TZASC_400
  179. select FSL_TZPC_BP147
  180. select SYS_FSL_ERRATUM_A008336 if !TFABOOT
  181. select SYS_FSL_ERRATUM_A008511 if !TFABOOT
  182. select SYS_FSL_ERRATUM_A008514 if !TFABOOT
  183. select SYS_FSL_ERRATUM_A008585
  184. select SYS_FSL_ERRATUM_A008997
  185. select SYS_FSL_ERRATUM_A009007
  186. select SYS_FSL_ERRATUM_A009008
  187. select SYS_FSL_ERRATUM_A009635
  188. select SYS_FSL_ERRATUM_A009663 if !TFABOOT
  189. select SYS_FSL_ERRATUM_A009798
  190. select SYS_FSL_ERRATUM_A009801
  191. select SYS_FSL_ERRATUM_A009803 if !TFABOOT
  192. select SYS_FSL_ERRATUM_A009942 if !TFABOOT
  193. select SYS_FSL_ERRATUM_A010165 if !TFABOOT
  194. select SYS_FSL_ERRATUM_A009203
  195. select ARCH_EARLY_INIT_R
  196. select BOARD_EARLY_INIT_F
  197. select SYS_I2C_MXC
  198. select SYS_I2C_MXC_I2C1 if !TFABOOT
  199. select SYS_I2C_MXC_I2C2 if !TFABOOT
  200. select SYS_I2C_MXC_I2C3 if !TFABOOT
  201. select SYS_I2C_MXC_I2C4 if !TFABOOT
  202. select RESV_RAM if GIC_V3_ITS
  203. imply DISTRO_DEFAULTS
  204. imply PANIC_HANG
  205. config ARCH_LX2162A
  206. bool
  207. select ARMV8_SET_SMPEN
  208. select FSL_LSCH3
  209. select NXP_LSCH3_2
  210. select SYS_HAS_SERDES
  211. select SYS_FSL_SRDS_1
  212. select SYS_FSL_SRDS_2
  213. select SYS_FSL_DDR
  214. select SYS_FSL_DDR_LE
  215. select SYS_FSL_DDR_VER_50
  216. select SYS_FSL_EC1
  217. select SYS_FSL_EC2
  218. select SYS_FSL_ERRATUM_A050106
  219. select SYS_FSL_HAS_RGMII
  220. select SYS_FSL_HAS_SEC
  221. select SYS_FSL_HAS_CCN508
  222. select SYS_FSL_HAS_DDR4
  223. select SYS_FSL_SEC_COMPAT_5
  224. select SYS_FSL_SEC_LE
  225. select ARCH_EARLY_INIT_R
  226. select BOARD_EARLY_INIT_F
  227. select SYS_I2C_MXC
  228. select RESV_RAM if GIC_V3_ITS
  229. imply DISTRO_DEFAULTS
  230. imply PANIC_HANG
  231. imply SCSI
  232. imply SCSI_AHCI
  233. config ARCH_LX2160A
  234. bool
  235. select ARMV8_SET_SMPEN
  236. select FSL_LSCH3
  237. select NXP_LSCH3_2
  238. select SYS_HAS_SERDES
  239. select SYS_FSL_SRDS_1
  240. select SYS_FSL_SRDS_2
  241. select SYS_NXP_SRDS_3
  242. select SYS_FSL_DDR
  243. select SYS_FSL_DDR_LE
  244. select SYS_FSL_DDR_VER_50
  245. select SYS_FSL_EC1
  246. select SYS_FSL_EC2
  247. select SYS_FSL_ERRATUM_A050106
  248. select SYS_FSL_HAS_RGMII
  249. select SYS_FSL_HAS_SEC
  250. select SYS_FSL_HAS_CCN508
  251. select SYS_FSL_HAS_DDR4
  252. select SYS_FSL_SEC_COMPAT_5
  253. select SYS_FSL_SEC_LE
  254. select ARCH_EARLY_INIT_R
  255. select BOARD_EARLY_INIT_F
  256. select SYS_I2C_MXC
  257. select RESV_RAM if GIC_V3_ITS
  258. imply DISTRO_DEFAULTS
  259. imply PANIC_HANG
  260. imply SCSI
  261. imply SCSI_AHCI
  262. config FSL_LSCH2
  263. bool
  264. select SYS_FSL_HAS_CCI400
  265. select SYS_FSL_HAS_SEC
  266. select SYS_FSL_SEC_COMPAT_5
  267. select SYS_FSL_SEC_BE
  268. config FSL_LSCH3
  269. select ARCH_MISC_INIT
  270. bool
  271. config NXP_LSCH3_2
  272. bool
  273. menu "Layerscape architecture"
  274. depends on FSL_LSCH2 || FSL_LSCH3
  275. config FSL_LAYERSCAPE
  276. bool
  277. config HAS_FEATURE_GIC64K_ALIGN
  278. bool
  279. default y if ARCH_LS1043A
  280. config HAS_FEATURE_ENHANCED_MSI
  281. bool
  282. default y if ARCH_LS1043A
  283. menu "Layerscape PPA"
  284. config FSL_LS_PPA
  285. bool "FSL Layerscape PPA firmware support"
  286. depends on !ARMV8_PSCI
  287. select ARMV8_SEC_FIRMWARE_SUPPORT
  288. select SEC_FIRMWARE_ARMV8_PSCI
  289. select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
  290. help
  291. The FSL Primary Protected Application (PPA) is a software component
  292. which is loaded during boot stage, and then remains resident in RAM
  293. and runs in the TrustZone after boot.
  294. Say y to enable it.
  295. config SPL_FSL_LS_PPA
  296. bool "FSL Layerscape PPA firmware support for SPL build"
  297. depends on !ARMV8_PSCI
  298. select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
  299. select SEC_FIRMWARE_ARMV8_PSCI
  300. select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
  301. help
  302. The FSL Primary Protected Application (PPA) is a software component
  303. which is loaded during boot stage, and then remains resident in RAM
  304. and runs in the TrustZone after boot. This is to load PPA during SPL
  305. stage instead of the RAM version of U-Boot. Once PPA is initialized,
  306. the rest of U-Boot (including RAM version) runs at EL2.
  307. choice
  308. prompt "FSL Layerscape PPA firmware loading-media select"
  309. depends on FSL_LS_PPA
  310. default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
  311. default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
  312. default SYS_LS_PPA_FW_IN_XIP
  313. config SYS_LS_PPA_FW_IN_XIP
  314. bool "XIP"
  315. help
  316. Say Y here if the PPA firmware locate at XIP flash, such
  317. as NOR or QSPI flash.
  318. config SYS_LS_PPA_FW_IN_MMC
  319. bool "eMMC or SD Card"
  320. help
  321. Say Y here if the PPA firmware locate at eMMC/SD card.
  322. config SYS_LS_PPA_FW_IN_NAND
  323. bool "NAND"
  324. help
  325. Say Y here if the PPA firmware locate at NAND flash.
  326. endchoice
  327. config LS_PPA_ESBC_HDR_SIZE
  328. hex "Length of PPA ESBC header"
  329. depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
  330. default 0x2000
  331. help
  332. Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
  333. NAND to memory to validate PPA image.
  334. endmenu
  335. config SYS_FSL_ERRATUM_A008997
  336. bool "Workaround for USB PHY erratum A008997"
  337. config SYS_FSL_ERRATUM_A009007
  338. bool
  339. help
  340. Workaround for USB PHY erratum A009007
  341. config SYS_FSL_ERRATUM_A009008
  342. bool "Workaround for USB PHY erratum A009008"
  343. config SYS_FSL_ERRATUM_A009798
  344. bool "Workaround for USB PHY erratum A009798"
  345. config SYS_FSL_ERRATUM_A050106
  346. bool "Workaround for USB PHY erratum A050106"
  347. help
  348. USB3.0 Receiver needs to enable fixed equalization
  349. for each of PHY instances in an SOC. This is similar
  350. to erratum A-009007, but this one is for LX2160A and LX2162A,
  351. and the register value is different.
  352. config SYS_FSL_ERRATUM_A010315
  353. bool "Workaround for PCIe erratum A010315"
  354. config SYS_FSL_ERRATUM_A010539
  355. bool "Workaround for PIN MUX erratum A010539"
  356. config MAX_CPUS
  357. int "Maximum number of CPUs permitted for Layerscape"
  358. default 2 if ARCH_LS1028A
  359. default 4 if ARCH_LS1043A
  360. default 4 if ARCH_LS1046A
  361. default 16 if ARCH_LS2080A
  362. default 8 if ARCH_LS1088A
  363. default 16 if ARCH_LX2160A
  364. default 16 if ARCH_LX2162A
  365. default 1
  366. help
  367. Set this number to the maximum number of possible CPUs in the SoC.
  368. SoCs may have multiple clusters with each cluster may have multiple
  369. ports. If some ports are reserved but higher ports are used for
  370. cores, count the reserved ports. This will allocate enough memory
  371. in spin table to properly handle all cores.
  372. config EMC2305
  373. bool "Fan controller"
  374. help
  375. Enable the EMC2305 fan controller for configuration of fan
  376. speed.
  377. config NXP_ESBC
  378. bool "NXP_ESBC"
  379. help
  380. Enable Freescale Secure Boot feature
  381. config QSPI_AHB_INIT
  382. bool "Init the QSPI AHB bus"
  383. help
  384. The default setting for QSPI AHB bus just support 3bytes addressing.
  385. But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
  386. bus for those flashes to support the full QSPI flash size.
  387. config FSPI_AHB_EN_4BYTE
  388. bool "Enable 4-byte Fast Read command for AHB mode"
  389. default n
  390. help
  391. The default setting for FlexSPI AHB bus just supports 3-byte addressing.
  392. But some FlexSPI flash sizes are up to 64MBytes.
  393. This flag enables fast read command for AHB mode and modifies required
  394. LUT to support full FlexSPI flash.
  395. config SYS_CCI400_OFFSET
  396. hex "Offset for CCI400 base"
  397. depends on SYS_FSL_HAS_CCI400
  398. default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
  399. default 0x180000 if FSL_LSCH2
  400. help
  401. Offset for CCI400 base
  402. CCI400 base addr = CCSRBAR + CCI400_OFFSET
  403. config SYS_FSL_IFC_BANK_COUNT
  404. int "Maximum banks of Integrated flash controller"
  405. depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
  406. default 4 if ARCH_LS1043A
  407. default 4 if ARCH_LS1046A
  408. default 8 if ARCH_LS2080A || ARCH_LS1088A
  409. config SYS_FSL_HAS_CCI400
  410. bool
  411. config SYS_FSL_HAS_CCN504
  412. bool
  413. config SYS_FSL_HAS_CCN508
  414. bool
  415. config SYS_FSL_HAS_DP_DDR
  416. bool
  417. config SYS_FSL_SRDS_1
  418. bool
  419. config SYS_FSL_SRDS_2
  420. bool
  421. config SYS_NXP_SRDS_3
  422. bool
  423. config SYS_HAS_SERDES
  424. bool
  425. config FSL_TZASC_1
  426. bool
  427. config FSL_TZASC_2
  428. bool
  429. config FSL_TZASC_400
  430. bool
  431. config FSL_TZPC_BP147
  432. bool
  433. endmenu
  434. menu "Layerscape clock tree configuration"
  435. depends on FSL_LSCH2 || FSL_LSCH3
  436. config SYS_FSL_CLK
  437. bool "Enable clock tree initialization"
  438. default y
  439. config CLUSTER_CLK_FREQ
  440. int "Reference clock of core cluster"
  441. depends on ARCH_LS1012A
  442. default 100000000
  443. help
  444. This number is the reference clock frequency of core PLL.
  445. For most platforms, the core PLL and Platform PLL have the same
  446. reference clock, but for some platforms, LS1012A for instance,
  447. they are provided sepatately.
  448. config SYS_FSL_PCLK_DIV
  449. int "Platform clock divider"
  450. default 1 if ARCH_LS1028A
  451. default 1 if ARCH_LS1043A
  452. default 1 if ARCH_LS1046A
  453. default 1 if ARCH_LS1088A
  454. default 2
  455. help
  456. This is the divider that is used to derive Platform clock from
  457. Platform PLL, in another word:
  458. Platform_clk = Platform_PLL_freq / this_divider
  459. config SYS_FSL_DSPI_CLK_DIV
  460. int "DSPI clock divider"
  461. default 1 if ARCH_LS1043A
  462. default 2
  463. help
  464. This is the divider that is used to derive DSPI clock from Platform
  465. clock, in another word DSPI_clk = Platform_clk / this_divider.
  466. config SYS_FSL_DUART_CLK_DIV
  467. int "DUART clock divider"
  468. default 1 if ARCH_LS1043A
  469. default 4 if ARCH_LX2160A
  470. default 4 if ARCH_LX2162A
  471. default 2
  472. help
  473. This is the divider that is used to derive DUART clock from Platform
  474. clock, in another word DUART_clk = Platform_clk / this_divider.
  475. config SYS_FSL_I2C_CLK_DIV
  476. int "I2C clock divider"
  477. default 1 if ARCH_LS1043A
  478. default 4 if ARCH_LS1012A
  479. default 4 if ARCH_LS1028A
  480. default 8 if ARCH_LX2160A
  481. default 8 if ARCH_LX2162A
  482. default 8 if ARCH_LS1088A
  483. default 2
  484. help
  485. This is the divider that is used to derive I2C clock from Platform
  486. clock, in another word I2C_clk = Platform_clk / this_divider.
  487. config SYS_FSL_IFC_CLK_DIV
  488. int "IFC clock divider"
  489. default 1 if ARCH_LS1043A
  490. default 4 if ARCH_LS1012A
  491. default 4 if ARCH_LS1028A
  492. default 8 if ARCH_LX2160A
  493. default 8 if ARCH_LX2162A
  494. default 8 if ARCH_LS1088A
  495. default 2
  496. help
  497. This is the divider that is used to derive IFC clock from Platform
  498. clock, in another word IFC_clk = Platform_clk / this_divider.
  499. config SYS_FSL_LPUART_CLK_DIV
  500. int "LPUART clock divider"
  501. default 1 if ARCH_LS1043A
  502. default 2
  503. help
  504. This is the divider that is used to derive LPUART clock from Platform
  505. clock, in another word LPUART_clk = Platform_clk / this_divider.
  506. config SYS_FSL_SDHC_CLK_DIV
  507. int "SDHC clock divider"
  508. default 1 if ARCH_LS1043A
  509. default 1 if ARCH_LS1012A
  510. default 2
  511. help
  512. This is the divider that is used to derive SDHC clock from Platform
  513. clock, in another word SDHC_clk = Platform_clk / this_divider.
  514. config SYS_FSL_QMAN_CLK_DIV
  515. int "QMAN clock divider"
  516. default 1 if ARCH_LS1043A
  517. default 2
  518. help
  519. This is the divider that is used to derive QMAN clock from Platform
  520. clock, in another word QMAN_clk = Platform_clk / this_divider.
  521. endmenu
  522. config RESV_RAM
  523. bool
  524. help
  525. Reserve memory from the top, tracked by gd->arch.resv_ram. This
  526. reserved RAM can be used by special driver that resides in memory
  527. after U-Boot exits. It's up to implementation to allocate and allow
  528. access to this reserved memory. For example, the reserved RAM can
  529. be at the high end of physical memory. The reserve RAM may be
  530. excluded from memory bank(s) passed to OS, or marked as reserved.
  531. config SYS_FSL_EC1
  532. bool
  533. help
  534. Ethernet controller 1, this is connected to
  535. MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs
  536. Provides DPAA2 capabilities
  537. config SYS_FSL_EC2
  538. bool
  539. help
  540. Ethernet controller 2, this is connected to
  541. MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs
  542. Provides DPAA2 capabilities
  543. config SYS_FSL_ERRATUM_A008336
  544. bool
  545. config SYS_FSL_ERRATUM_A008514
  546. bool
  547. config SYS_FSL_ERRATUM_A008585
  548. bool
  549. config SYS_FSL_ERRATUM_A008850
  550. bool
  551. config SYS_FSL_ERRATUM_A009203
  552. bool
  553. config SYS_FSL_ERRATUM_A009635
  554. bool
  555. config SYS_FSL_ERRATUM_A009660
  556. bool
  557. config SYS_FSL_ERRATUM_A050382
  558. bool
  559. config SYS_FSL_HAS_RGMII
  560. bool
  561. depends on SYS_FSL_EC1 || SYS_FSL_EC2
  562. config SPL_LDSCRIPT
  563. default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
  564. config HAS_FSL_XHCI_USB
  565. bool
  566. default y if ARCH_LS1043A || ARCH_LS1046A
  567. help
  568. For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
  569. pins, select it when the pins are assigned to USB.
  570. config SYS_FSL_BOOTROM_BASE
  571. hex
  572. depends on FSL_LSCH2
  573. default 0
  574. config SYS_FSL_BOOTROM_SIZE
  575. hex
  576. depends on FSL_LSCH2
  577. default 0x1000000