lpddr4_init.c 4.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018 NXP
  4. *
  5. */
  6. #include <common.h>
  7. #include <errno.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/ddr.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/ddr.h>
  12. #include <asm/arch/lpddr4_define.h>
  13. #include <asm/arch/sys_proto.h>
  14. void lpddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
  15. {
  16. int i = 0;
  17. for (i = 0; i < num; i++) {
  18. reg32_write(ddrc_cfg->reg, ddrc_cfg->val);
  19. ddrc_cfg++;
  20. }
  21. }
  22. void ddr_init(struct dram_timing_info *dram_timing)
  23. {
  24. unsigned int tmp;
  25. debug("DDRINFO: start lpddr4 ddr init\n");
  26. /* step 1: reset */
  27. if (is_imx8mq()) {
  28. reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F00000F);
  29. reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
  30. reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
  31. } else {
  32. reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00001F);
  33. reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
  34. }
  35. mdelay(100);
  36. debug("DDRINFO: reset done\n");
  37. /*
  38. * change the clock source of dram_apb_clk_root:
  39. * source 4 800MHz /4 = 200MHz
  40. */
  41. clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
  42. CLK_ROOT_SOURCE_SEL(4) |
  43. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
  44. /* disable iso */
  45. reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
  46. reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
  47. debug("DDRINFO: cfg clk\n");
  48. dram_pll_init(MHZ(750));
  49. /*
  50. * release [0]ddr1_preset_n, [1]ddr1_core_reset_n,
  51. * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n
  52. */
  53. reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
  54. /*step2 Configure uMCTL2's registers */
  55. debug("DDRINFO: ddrc config start\n");
  56. lpddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
  57. debug("DDRINFO: ddrc config done\n");
  58. /*
  59. * step3 de-assert all reset
  60. * RESET: <core_ddrc_rstn> DEASSERTED
  61. * RESET: <aresetn> for Port 0 DEASSERT(0)ED
  62. */
  63. reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
  64. reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
  65. reg32_write(DDRC_DBG1(0), 0x00000000);
  66. /* step4 */
  67. /* [0]dis_auto_refresh=1 */
  68. reg32_write(DDRC_RFSHCTL3(0), 0x00000011);
  69. /* [8]--1: lpddr4_sr allowed; [5]--1: software entry to SR */
  70. reg32_write(DDRC_PWRCTL(0), 0x000000a8);
  71. do {
  72. tmp = reg32_read(DDRC_STAT(0));
  73. } while ((tmp & 0x33f) != 0x223);
  74. reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */
  75. /* step5 */
  76. reg32_write(DDRC_SWCTL(0), 0x00000000);
  77. /* step6 */
  78. tmp = reg32_read(DDRC_MSTR2(0));
  79. if (tmp == 0x2)
  80. reg32_write(DDRC_DFIMISC(0), 0x00000210);
  81. else if (tmp == 0x1)
  82. reg32_write(DDRC_DFIMISC(0), 0x00000110);
  83. else
  84. reg32_write(DDRC_DFIMISC(0), 0x00000010);
  85. /* step7 [0]--1: disable quasi-dynamic programming */
  86. reg32_write(DDRC_SWCTL(0), 0x00000001);
  87. /* step8 Configure LPDDR4 PHY's registers */
  88. debug("DDRINFO:ddrphy config start\n");
  89. ddr_cfg_phy(dram_timing);
  90. debug("DDRINFO: ddrphy config done\n");
  91. /*
  92. * step14 CalBusy.0 =1, indicates the calibrator is actively
  93. * calibrating. Wait Calibrating done.
  94. */
  95. do {
  96. tmp = reg32_read(DDRPHY_CalBusy(0));
  97. } while ((tmp & 0x1));
  98. debug("DDRINFO:ddrphy calibration done\n");
  99. /* step15 [0]--0: to enable quasi-dynamic programming */
  100. reg32_write(DDRC_SWCTL(0), 0x00000000);
  101. /* step16 */
  102. tmp = reg32_read(DDRC_MSTR2(0));
  103. if (tmp == 0x2)
  104. reg32_write(DDRC_DFIMISC(0), 0x00000230);
  105. else if (tmp == 0x1)
  106. reg32_write(DDRC_DFIMISC(0), 0x00000130);
  107. else
  108. reg32_write(DDRC_DFIMISC(0), 0x00000030);
  109. /* step17 [0]--1: disable quasi-dynamic programming */
  110. reg32_write(DDRC_SWCTL(0), 0x00000001);
  111. /* step18 wait DFISTAT.dfi_init_complete to 1 */
  112. do {
  113. tmp = reg32_read(DDRC_DFISTAT(0));
  114. } while ((tmp & 0x1) == 0x0);
  115. /* step19 */
  116. reg32_write(DDRC_SWCTL(0), 0x00000000);
  117. /* step20~22 */
  118. tmp = reg32_read(DDRC_MSTR2(0));
  119. if (tmp == 0x2) {
  120. reg32_write(DDRC_DFIMISC(0), 0x00000210);
  121. /* set DFIMISC.dfi_init_complete_en again */
  122. reg32_write(DDRC_DFIMISC(0), 0x00000211);
  123. } else if (tmp == 0x1) {
  124. reg32_write(DDRC_DFIMISC(0), 0x00000110);
  125. /* set DFIMISC.dfi_init_complete_en again */
  126. reg32_write(DDRC_DFIMISC(0), 0x00000111);
  127. } else {
  128. /* clear DFIMISC.dfi_init_complete_en */
  129. reg32_write(DDRC_DFIMISC(0), 0x00000010);
  130. /* set DFIMISC.dfi_init_complete_en again */
  131. reg32_write(DDRC_DFIMISC(0), 0x00000011);
  132. }
  133. /* step23 [5]selfref_sw=0; */
  134. reg32_write(DDRC_PWRCTL(0), 0x00000008);
  135. /* step24 sw_done=1 */
  136. reg32_write(DDRC_SWCTL(0), 0x00000001);
  137. /* step25 wait SWSTAT.sw_done_ack to 1 */
  138. do {
  139. tmp = reg32_read(DDRC_SWSTAT(0));
  140. } while ((tmp & 0x1) == 0x0);
  141. #ifdef DFI_BUG_WR
  142. reg32_write(DDRC_DFIPHYMSTR(0), 0x00000001);
  143. #endif
  144. /* wait STAT.operating_mode([1:0] for ddr3) to normal state */
  145. do {
  146. tmp = reg32_read(DDRC_STAT(0));
  147. } while ((tmp & 0x3) != 0x1);
  148. /* step26 */
  149. reg32_write(DDRC_RFSHCTL3(0), 0x00000010);
  150. /* enable port 0 */
  151. reg32_write(DDRC_PCTRL_0(0), 0x00000001);
  152. debug("DDRINFO: ddrmix config done\n");
  153. /* save the dram timing config into memory */
  154. dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
  155. }