ddrphy_train.c 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018 NXP
  4. */
  5. #include <common.h>
  6. #include <linux/kernel.h>
  7. #include <asm/arch/ddr.h>
  8. #include <asm/arch/lpddr4_define.h>
  9. void ddr_cfg_phy(struct dram_timing_info *dram_timing)
  10. {
  11. struct dram_cfg_param *dram_cfg;
  12. struct dram_fsp_msg *fsp_msg;
  13. unsigned int num;
  14. int i = 0;
  15. int j = 0;
  16. /* initialize PHY configuration */
  17. dram_cfg = dram_timing->ddrphy_cfg;
  18. num = dram_timing->ddrphy_cfg_num;
  19. for (i = 0; i < num; i++) {
  20. /* config phy reg */
  21. dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);
  22. dram_cfg++;
  23. }
  24. /* load the frequency setpoint message block config */
  25. fsp_msg = dram_timing->fsp_msg;
  26. for (i = 0; i < dram_timing->fsp_msg_num; i++) {
  27. debug("DRAM PHY training for %dMTS\n", fsp_msg->drate);
  28. /* set dram PHY input clocks to desired frequency */
  29. ddrphy_init_set_dfi_clk(fsp_msg->drate);
  30. /* load the dram training firmware image */
  31. dwc_ddrphy_apb_wr(0xd0000, 0x0);
  32. ddr_load_train_firmware(fsp_msg->fw_type);
  33. /* load the frequency set point message block parameter */
  34. dram_cfg = fsp_msg->fsp_cfg;
  35. num = fsp_msg->fsp_cfg_num;
  36. for (j = 0; j < num; j++) {
  37. dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);
  38. dram_cfg++;
  39. }
  40. /*
  41. * -------------------- excute the firmware --------------------
  42. * Running the firmware is a simply process to taking the
  43. * PMU out of reset and stall, then the firwmare will be run
  44. * 1. reset the PMU;
  45. * 2. begin the excution;
  46. * 3. wait for the training done;
  47. * 4. read the message block result.
  48. * -------------------------------------------------------------
  49. */
  50. dwc_ddrphy_apb_wr(0xd0000, 0x1);
  51. dwc_ddrphy_apb_wr(0xd0099, 0x9);
  52. dwc_ddrphy_apb_wr(0xd0099, 0x1);
  53. dwc_ddrphy_apb_wr(0xd0099, 0x0);
  54. /* Wait for the training firmware to complete */
  55. wait_ddrphy_training_complete();
  56. /* Halt the microcontroller. */
  57. dwc_ddrphy_apb_wr(0xd0099, 0x1);
  58. /* Read the Message Block results */
  59. dwc_ddrphy_apb_wr(0xd0000, 0x0);
  60. ddrphy_init_read_msg_block(fsp_msg->fw_type);
  61. dwc_ddrphy_apb_wr(0xd0000, 0x1);
  62. fsp_msg++;
  63. }
  64. /* Load PHY Init Engine Image */
  65. dram_cfg = dram_timing->ddrphy_pie;
  66. num = dram_timing->ddrphy_pie_num;
  67. for (i = 0; i < num; i++) {
  68. dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);
  69. dram_cfg++;
  70. }
  71. /* save the ddr PHY trained CSR in memory for low power use */
  72. ddrphy_trained_csr_save(ddrphy_trained_csr, ddrphy_trained_csr_num);
  73. }