PCIPPC2.h 7.7 KB

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  1. /*
  2. * (C) Copyright 2002
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. *
  25. * Configuration settings for the PCIPPC-2 board.
  26. *
  27. */
  28. /* ------------------------------------------------------------------------- */
  29. /*
  30. * board/config.h - configuration options, board specific
  31. */
  32. #ifndef __CONFIG_H
  33. #define __CONFIG_H
  34. /*
  35. * High Level Configuration Options
  36. * (easy to change)
  37. */
  38. #define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */
  39. #define CONFIG_BOARD_PRE_INIT 1
  40. #define CONFIG_MISC_INIT_R 1
  41. #define CONFIG_CONS_INDEX 1
  42. #define CONFIG_BAUDRATE 9600
  43. #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  44. #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passed to Linux in MHz */
  45. #define CONFIG_PREBOOT ""
  46. #define CONFIG_BOOTDELAY 5
  47. #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
  48. CONFIG_BOOTP_BOOTFILESIZE)
  49. #define CONFIG_MAC_PARTITION
  50. #define CONFIG_DOS_PARTITION
  51. #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
  52. CFG_CMD_ASKENV | \
  53. CFG_CMD_BSP | \
  54. CFG_CMD_DATE | \
  55. CFG_CMD_DHCP | \
  56. CFG_CMD_DOC | \
  57. CFG_CMD_ELF | \
  58. CFG_CMD_PCI )
  59. #define CONFIG_PCI 1
  60. #define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
  61. /* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
  62. */
  63. #include <cmd_confdefs.h>
  64. /*
  65. * Miscellaneous configurable options
  66. */
  67. #define CFG_LONGHELP /* undef to save memory */
  68. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  69. #define CFG_HUSH_PARSER 1 /* use "hush" command parser */
  70. #ifdef CFG_HUSH_PARSER
  71. #define CFG_PROMPT_HUSH_PS2 "> "
  72. #endif
  73. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  74. /* Print Buffer Size
  75. */
  76. #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
  77. #define CFG_MAXARGS 64 /* max number of command args */
  78. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  79. #define CFG_LOAD_ADDR 0x00100000 /* Default load address */
  80. /*-----------------------------------------------------------------------
  81. * Start addresses for the final memory configuration
  82. * (Set up by the startup code)
  83. * Please note that CFG_SDRAM_BASE _must_ start at 0
  84. */
  85. #define CFG_SDRAM_BASE 0x00000000
  86. #define CFG_FLASH_BASE 0xFFF00000
  87. #define CFG_FLASH_MAX_SIZE 0x00100000
  88. /* Maximum amount of RAM.
  89. */
  90. #define CFG_MAX_RAM_SIZE 0x20000000 /* 512Mb */
  91. #define CFG_RESET_ADDRESS 0xFFF00100
  92. #define CFG_MONITOR_BASE TEXT_BASE
  93. #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  94. #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  95. #if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \
  96. CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE
  97. #define CFG_RAMBOOT
  98. #else
  99. #undef CFG_RAMBOOT
  100. #endif
  101. #define CFG_MEMTEST_START 0x00004000 /* memtest works on */
  102. #define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
  103. /*-----------------------------------------------------------------------
  104. * Definitions for initial stack pointer and data area
  105. */
  106. /* Size in bytes reserved for initial data
  107. */
  108. #define CFG_GBL_DATA_SIZE 128
  109. #define CFG_INIT_RAM_ADDR 0x40000000
  110. #define CFG_INIT_RAM_END 0x8000
  111. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  112. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  113. #define CFG_INIT_RAM_LOCK
  114. /*
  115. * Temporary buffer for serial data until the real serial driver
  116. * is initialised (memtest will destroy this buffer)
  117. */
  118. #define CFG_SCONSOLE_ADDR CFG_INIT_RAM_ADDR
  119. #define CFG_SCONSOLE_SIZE 0x0002000
  120. /* SDRAM 0 - 256MB
  121. */
  122. #define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
  123. #define CFG_DBAT0U (CFG_SDRAM_BASE | \
  124. BATU_BL_256M | BATU_VS | BATU_VP)
  125. /* SDRAM 1 - 256MB
  126. */
  127. #define CFG_DBAT1L ((CFG_SDRAM_BASE + 0x10000000) | \
  128. BATL_PP_10 | BATL_MEMCOHERENCE)
  129. #define CFG_DBAT1U ((CFG_SDRAM_BASE + 0x10000000) | \
  130. BATU_BL_256M | BATU_VS | BATU_VP)
  131. /* Init RAM in the CPU DCache (no backing memory)
  132. */
  133. #define CFG_DBAT2L (CFG_INIT_RAM_ADDR | \
  134. BATL_PP_10 | BATL_MEMCOHERENCE)
  135. #define CFG_DBAT2U (CFG_INIT_RAM_ADDR | \
  136. BATU_BL_128K | BATU_VS | BATU_VP)
  137. /* I/O and PCI memory at 0xf0000000
  138. */
  139. #define CFG_DBAT3L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
  140. #define CFG_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  141. #define CFG_IBAT0L CFG_DBAT0L
  142. #define CFG_IBAT0U CFG_DBAT0U
  143. #define CFG_IBAT1L CFG_DBAT1L
  144. #define CFG_IBAT1U CFG_DBAT1U
  145. #define CFG_IBAT2L CFG_DBAT2L
  146. #define CFG_IBAT2U CFG_DBAT2U
  147. #define CFG_IBAT3L CFG_DBAT3L
  148. #define CFG_IBAT3U CFG_DBAT3U
  149. /*
  150. * Low Level Configuration Settings
  151. * (address mappings, register initial values, etc.)
  152. * You should know what you are doing if you make changes here.
  153. * For the detail description refer to the PCIPPC2 user's manual.
  154. */
  155. #define CFG_HZ 1000
  156. #define CFG_BUS_HZ 100000000 /* bus speed - 100 mhz */
  157. #define CFG_CPU_CLK 300000000
  158. #define CFG_BUS_CLK 100000000
  159. /*
  160. * For booting Linux, the board info and command line data
  161. * have to be in the first 8 MB of memory, since this is
  162. * the maximum mapped by the Linux kernel during initialization.
  163. */
  164. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  165. /*-----------------------------------------------------------------------
  166. * FLASH organization
  167. */
  168. #define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
  169. #define CFG_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */
  170. #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  171. #define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
  172. /*
  173. * Note: environment is not EMBEDDED in the U-Boot code.
  174. * It's stored in flash separately.
  175. */
  176. #define CFG_ENV_IS_IN_FLASH 1
  177. #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x70000)
  178. #define CFG_ENV_SIZE 0x1000 /* Size of the Environment */
  179. #define CFG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */
  180. /*-----------------------------------------------------------------------
  181. * Cache Configuration
  182. */
  183. #define CFG_CACHELINE_SIZE 32
  184. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  185. # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  186. #endif
  187. /*
  188. * L2 cache
  189. */
  190. #undef CFG_L2
  191. #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
  192. L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
  193. #define L2_ENABLE (L2_INIT | L2CR_L2E)
  194. /*
  195. * Internal Definitions
  196. *
  197. * Boot Flags
  198. */
  199. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  200. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  201. /*-----------------------------------------------------------------------
  202. * Disk-On-Chip configuration
  203. */
  204. #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
  205. #define CFG_DOC_SUPPORT_2000
  206. #undef CFG_DOC_SUPPORT_MILLENNIUM
  207. /*-----------------------------------------------------------------------
  208. RTC m48t59
  209. */
  210. #define CONFIG_RTC_MK48T59
  211. #define CONFIG_WATCHDOG
  212. #define CONFIG_NET_MULTI /* Multi ethernet cards support */
  213. #define CONFIG_EEPRO100
  214. #define CONFIG_TULIP
  215. #endif /* __CONFIG_H */