MHPC.h 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371
  1. /*
  2. * (C) Copyright 2001
  3. * Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de
  4. *
  5. * (C) Copyright 2001
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. *
  8. * Configuation settings for the miniHiPerCam.
  9. *
  10. * -----------------------------------------------------------------
  11. * See file CREDITS for list of people who contributed to this
  12. * project.
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License as
  16. * published by the Free Software Foundation; either version 2 of
  17. * the License, or (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, write to the Free Software
  26. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27. * MA 02111-1307 USA
  28. */
  29. /*
  30. * board/config.h - configuration options, board specific
  31. */
  32. #ifndef __CONFIG_H
  33. #define __CONFIG_H
  34. /*
  35. * High Level Configuration Options
  36. * (easy to change)
  37. */
  38. #define CONFIG_MPC823 1 /* This is a MPC823 CPU */
  39. #define CONFIG_MHPC 1 /* on a miniHiPerCam */
  40. #define CONFIG_BOARD_PRE_INIT 1 /* do special hardware init. */
  41. #define CONFIG_MISC_INIT_R 1
  42. #define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED
  43. #undef CONFIG_8xx_CONS_SMC1
  44. #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
  45. #undef CONFIG_8xx_CONS_NONE
  46. #define CONFIG_BAUDRATE 9600
  47. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  48. #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
  49. #define CONFIG_ENV_OVERWRITE 1
  50. #define CONFIG_ETHADDR 00:00:5b:ee:de:ad
  51. #undef CONFIG_BOOTARGS
  52. #define CONFIG_BOOTCOMMAND \
  53. "bootp;" \
  54. "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
  55. "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
  56. "bootm"
  57. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  58. #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
  59. #undef CONFIG_WATCHDOG /* watchdog disabled */
  60. #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
  61. #undef CONFIG_UCODE_PATCH
  62. /* enable I2C and select the hardware/software driver */
  63. #undef CONFIG_HARD_I2C /* I2C with hardware support */
  64. #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
  65. /*
  66. * Software (bit-bang) I2C driver configuration
  67. */
  68. #define PB_SCL 0x00000020 /* PB 26 */
  69. #define PB_SDA 0x00000010 /* PB 27 */
  70. #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
  71. #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
  72. #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
  73. #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
  74. #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
  75. else immr->im_cpm.cp_pbdat &= ~PB_SDA
  76. #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
  77. else immr->im_cpm.cp_pbdat &= ~PB_SCL
  78. #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
  79. #define CFG_I2C_SPEED 50000
  80. #define CFG_I2C_SLAVE 0xFE
  81. #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C04 */
  82. #define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
  83. /* mask of address bits that overflow into the "EEPROM chip address" */
  84. #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
  85. #define CFG_EEPROM_PAGE_WRITE_BITS 3
  86. #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
  87. #define LCD_VIDEO_ADDR (SDRAM_MAX_SIZE-SDRAM_RES_SIZE)
  88. #define LCD_VIDEO_SIZE SDRAM_RES_SIZE /* 2MB */
  89. #define LCD_VIDEO_COLS 640
  90. #define LCD_VIDEO_ROWS 480
  91. #define LCD_VIDEO_FG 255
  92. #define LCD_VIDEO_BG 0
  93. #undef CONFIG_VIDEO /* test only ! s.a devices.c and 8xx */
  94. #define CONFIG_CFB_CONSOLE /* framebuffer console with std input */
  95. #define CONFIG_VIDEO_LOGO
  96. #define VIDEO_KBD_INIT_FCT 0 /* no KBD dev on MHPC - use serial */
  97. #define VIDEO_TSTC_FCT serial_tstc
  98. #define VIDEO_GETC_FCT serial_getc
  99. #define CONFIG_BR0_WORKAROUND 1
  100. #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
  101. CFG_CMD_DATE | \
  102. CFG_CMD_EEPROM | \
  103. CFG_CMD_ELF | \
  104. CFG_CMD_I2C | \
  105. CFG_CMD_JFFS2 | \
  106. CFG_CMD_REGINFO )
  107. #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
  108. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  109. #include <cmd_confdefs.h>
  110. /*
  111. * Miscellaneous configurable options
  112. */
  113. #define CFG_LONGHELP /* undef to save memory */
  114. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  115. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  116. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  117. #else
  118. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  119. #endif
  120. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  121. #define CFG_MAXARGS 16 /* max number of command args */
  122. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  123. #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
  124. #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  125. #define CFG_LOAD_ADDR 0x300000 /* default load address */
  126. #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  127. #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  128. /*
  129. * Low Level Configuration Settings
  130. * (address mappings, register initial values, etc.)
  131. * You should know what you are doing if you make changes here.
  132. */
  133. /*-----------------------------------------------------------------------
  134. * Physical memory map
  135. */
  136. #define CFG_IMMR 0xFFF00000 /* Internal Memory Mapped Register*/
  137. /*-----------------------------------------------------------------------
  138. * Definitions for initial stack pointer and data area (in DPRAM)
  139. */
  140. #define CFG_INIT_RAM_ADDR CFG_IMMR
  141. #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
  142. #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
  143. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  144. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  145. /*-----------------------------------------------------------------------
  146. * Start addresses for the final memory configuration
  147. * (Set up by the startup code)
  148. * Please note that CFG_SDRAM_BASE _must_ start at 0
  149. */
  150. #define CFG_SDRAM_BASE 0x00000000
  151. #define CFG_FLASH_BASE 0xfe000000
  152. #define CFG_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
  153. #undef CFG_MONITOR_BASE /* to run U-Boot from RAM */
  154. #define CFG_MONITOR_BASE CFG_FLASH_BASE
  155. #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  156. #define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
  157. #define CFG_JFFS2_NUM_BANKS 1 /* one flash only */
  158. /*
  159. * For booting Linux, the board info and command line data
  160. * have to be in the first 8 MB of memory, since this is
  161. * the maximum mapped by the Linux kernel during initialization.
  162. */
  163. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map- for Linux */
  164. /*-----------------------------------------------------------------------
  165. * FLASH organization
  166. */
  167. #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
  168. #define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
  169. #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  170. #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  171. #define CFG_ENV_IS_IN_FLASH 1
  172. #define CFG_ENV_OFFSET CFG_MONITOR_LEN /* Offset of Environment */
  173. #define CFG_ENV_SIZE 0x20000 /* Total Size of Environment */
  174. /*-----------------------------------------------------------------------
  175. * Cache Configuration
  176. */
  177. #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
  178. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  179. #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
  180. #endif
  181. /*-----------------------------------------------------------------------
  182. * SYPCR - System Protection Control 11-9
  183. * SYPCR can only be written once after reset!
  184. *-----------------------------------------------------------------------
  185. * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  186. */
  187. #if defined(CONFIG_WATCHDOG)
  188. #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
  189. SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
  190. #else
  191. #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
  192. SYPCR_SWP)
  193. #endif
  194. /*-----------------------------------------------------------------------
  195. * SIUMCR - SIU Module Configuration 11-6
  196. *-----------------------------------------------------------------------
  197. * PCMCIA config., multi-function pin tri-state
  198. */
  199. #define CFG_SIUMCR (SIUMCR_SEME)
  200. /*-----------------------------------------------------------------------
  201. * TBSCR - Time Base Status and Control 11-26
  202. *-----------------------------------------------------------------------
  203. * Clear Reference Interrupt Status, Timebase freezing enabled
  204. */
  205. #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
  206. /*-----------------------------------------------------------------------
  207. * PISCR - Periodic Interrupt Status and Control 11-31
  208. *-----------------------------------------------------------------------
  209. * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  210. */
  211. #define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
  212. /*-----------------------------------------------------------------------
  213. * RTCSC - Real-Time Clock Status and Control Register 12-18
  214. *-----------------------------------------------------------------------
  215. */
  216. #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
  217. /*-----------------------------------------------------------------------
  218. * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
  219. *-----------------------------------------------------------------------
  220. * Reset PLL lock status sticky bit, timer expired status bit and timer
  221. * interrupt status bit - leave PLL multiplication factor unchanged !
  222. */
  223. #define MPC8XX_SPEED 50000000L
  224. #define MPC8XX_XIN 5000000L /* ref clk */
  225. #define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN)
  226. #define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
  227. PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
  228. /*-----------------------------------------------------------------------
  229. * SCCR - System Clock and reset Control Register 15-27
  230. *-----------------------------------------------------------------------
  231. * Set clock output, timebase and RTC source and divider,
  232. * power management and some other internal clocks
  233. */
  234. #define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) /* SCCR_EBDF11 */
  235. #define CFG_SCCR (SCCR_TBS | SCCR_DFLCD001)
  236. /*-----------------------------------------------------------------------
  237. * MAMR settings for SDRAM - 16-14
  238. * => 0xC080200F
  239. *-----------------------------------------------------------------------
  240. * periodic timer for refresh
  241. */
  242. #define CFG_MAMR_PTA 0xC0
  243. #define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK)
  244. /*
  245. * BR0 and OR0 (FLASH) used to re-map FLASH
  246. */
  247. /* allow for max 8 MB of Flash */
  248. #define FLASH_BASE 0xFE000000 /* FLASH bank #0*/
  249. #define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0*/
  250. #define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */
  251. #define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
  252. #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/
  253. #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
  254. #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
  255. #define CFG_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V )
  256. /*
  257. * BR1 and OR1 (SDRAM)
  258. */
  259. #define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
  260. #define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
  261. #define SDRAM_RES_SIZE 0x00200000 /* 2 MB for framebuffer */
  262. /* SDRAM timing: drive GPL5 high on first cycle */
  263. #define CFG_OR_TIMING_SDRAM (OR_G5LS)
  264. #define CFG_OR1_PRELIM ((~(SDRAM_MAX_SIZE)+1)| CFG_OR_TIMING_SDRAM )
  265. #define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
  266. /*
  267. * BR2/OR2 - DIMM
  268. */
  269. #define CFG_OR2 (OR_ACS_DIV4)
  270. #define CFG_BR2 (BR_MS_UPMA)
  271. /*
  272. * BR3/OR3 - DIMM
  273. */
  274. #define CFG_OR3 (OR_ACS_DIV4)
  275. #define CFG_BR3 (BR_MS_UPMA)
  276. /*
  277. * BR4/OR4
  278. */
  279. #define CFG_OR4 0
  280. #define CFG_BR4 0
  281. /*
  282. * BR5/OR5
  283. */
  284. #define CFG_OR5 0
  285. #define CFG_BR5 0
  286. /*
  287. * BR6/OR6
  288. */
  289. #define CFG_OR6 0
  290. #define CFG_BR6 0
  291. /*
  292. * BR7/OR7
  293. */
  294. #define CFG_OR7 0
  295. #define CFG_BR7 0
  296. /*-----------------------------------------------------------------------
  297. * Debug Entry Mode
  298. *-----------------------------------------------------------------------
  299. *
  300. */
  301. #define CFG_DER 0
  302. /*
  303. * Internal Definitions
  304. *
  305. * Boot Flags
  306. */
  307. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  308. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  309. #endif /* __CONFIG_H */