IPHASE4539.h 13 KB

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  1. /*
  2. * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
  3. *
  4. * This file is based on similar values for other boards found in
  5. * other U-Boot config files, mainly tqm8260.h and mpc8260ads.h.
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. /*
  26. * Config header file for a Interphase 4539 PMC, 64 MB SDRAM, 4MB Flash.
  27. */
  28. #ifndef __CONFIG_H
  29. #define __CONFIG_H
  30. #undef DEBUG /* General debug */
  31. /*-----------------------------------------------------------------------
  32. * High Level Configuration Options
  33. * (easy to change)
  34. */
  35. #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
  36. #define CONFIG_IPHASE4539 1 /* ...on a Interphase 4539 PMC */
  37. /*-----------------------------------------------------------------------
  38. * select serial console configuration
  39. *
  40. * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  41. * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  42. * for SCC).
  43. *
  44. * if CONFIG_CONS_NONE is defined, then the serial console routines must
  45. * defined elsewhere (for example, on the cogent platform, there are serial
  46. * ports on the motherboard which are used for the serial console - see
  47. * cogent/cma101/serial.[ch]).
  48. */
  49. #define CONFIG_CONS_ON_SMC /* define if console on SMC */
  50. #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
  51. #undef CONFIG_CONS_NONE /* define if console on something else */
  52. #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
  53. /*-----------------------------------------------------------------------
  54. * select ethernet configuration
  55. *
  56. * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  57. * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  58. * for FCC)
  59. *
  60. * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  61. * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
  62. * from CONFIG_COMMANDS to remove support for networking.
  63. */
  64. #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
  65. #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
  66. #undef CONFIG_ETHER_NONE /* define if ether on something else */
  67. #define CONFIG_ETHER_INDEX 3 /* which channel for ether */
  68. #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
  69. /*-----------------------------------------------------------------------
  70. * - Rx-CLK is CLK14
  71. * - Tx-CLK is CLK16
  72. * - Select bus for bd/buffers (see 28-13)
  73. * - Half duplex
  74. */
  75. # define CFG_CMXFCR_MASK (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
  76. # define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
  77. # define CFG_CPMFCR_RAMTYPE 0
  78. # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
  79. #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
  80. /* other options */
  81. #define CONFIG_8260_CLKIN 66666666 /* in Hz */
  82. #define CONFIG_BAUDRATE 19200
  83. #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
  84. /*
  85. * select i2c support configuration
  86. *
  87. * Supported configurations are {none, software, hardware} drivers.
  88. * If the software driver is chosen, there are some additional
  89. * configuration items that the driver uses to drive the port pins.
  90. */
  91. #undef CONFIG_HARD_I2C /* I2C with hardware support */
  92. #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
  93. #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
  94. #define CFG_I2C_SLAVE 0x7F
  95. /*
  96. * Software (bit-bang) I2C driver configuration
  97. */
  98. #ifdef CONFIG_SOFT_I2C
  99. #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
  100. #define I2C_ACTIVE (iop->pdir |= 0x00010000)
  101. #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
  102. #define I2C_READ ((iop->pdat & 0x00010000) != 0)
  103. #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
  104. else iop->pdat &= ~0x00010000
  105. #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
  106. else iop->pdat &= ~0x00020000
  107. #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
  108. #endif /* CONFIG_SOFT_I2C */
  109. #define CONFIG_COMMANDS CONFIG_CMD_DFL
  110. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  111. #include <cmd_confdefs.h>
  112. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  113. #define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
  114. #define CONFIG_BOOTARGS "root=/dev/ram rw"
  115. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  116. #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
  117. #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
  118. #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
  119. #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
  120. #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
  121. #endif
  122. #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
  123. /*-----------------------------------------------------------------------
  124. * Miscellaneous configurable options
  125. */
  126. #define CFG_LONGHELP /* undef to save memory */
  127. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  128. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  129. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  130. #else
  131. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  132. #endif
  133. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  134. #define CFG_MAXARGS 16 /* max number of command args */
  135. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  136. #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
  137. #define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15 MB in DRAM */
  138. #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passed to Linux in MHz */
  139. /* for versions < 2.4.5-pre5 */
  140. #define CFG_LOAD_ADDR 0x100000 /* default load address */
  141. #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  142. #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  143. #define CFG_RESET_ADDRESS 0x04400000
  144. #define CONFIG_MISC_INIT_R 1 /* We need misc_init_r() */
  145. /*-----------------------------------------------------------------------
  146. * For booting Linux, the board info and command line data
  147. * have to be in the first 8 MB of memory, since this is
  148. * the maximum mapped by the Linux kernel during initialization.
  149. */
  150. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  151. /*-----------------------------------------------------------------------
  152. * Start addresses for the final memory configuration (Setup by the
  153. * startup code). Please note that CFG_SDRAM_BASE _must_ start at 0.
  154. */
  155. #define CFG_SDRAM_BASE 0x00000000
  156. #define CFG_FLASH_BASE 0xFF800000
  157. #define CFG_MONITOR_BASE TEXT_BASE
  158. #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  159. #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  160. /*-----------------------------------------------------------------------
  161. * FLASH organization
  162. */
  163. #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
  164. #define CFG_MAX_FLASH_SECT 64 /* max num of sects on one chip */
  165. #define CFG_MAX_FLASH_SIZE (CFG_MAX_FLASH_SECT * 0x10000) /* 4 MB */
  166. #define CFG_FLASH_ERASE_TOUT 2400000 /* Flash Erase Timeout (in ms) */
  167. #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
  168. /* Environment in FLASH, there is little space left in Serial EEPROM */
  169. #define CFG_ENV_IS_IN_FLASH 1
  170. #define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
  171. #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x10000) /* 2. sector */
  172. /*-----------------------------------------------------------------------
  173. * Hard Reset Configuration Words
  174. *
  175. * if you change bits in the HRCW, you must also change the CFG_*
  176. * defines for the various registers affected by the HRCW e.g. changing
  177. * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
  178. */
  179. #define CFG_HRCW_MASTER ( ( HRCW_BPS01 | HRCW_EBM ) |\
  180. ( HRCW_L2CPC10 | HRCW_ISB110 ) |\
  181. ( HRCW_MMR11 | HRCW_APPC10 ) |\
  182. ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
  183. ) /* 0x14863245 */
  184. /* no slaves */
  185. #define CFG_HRCW_SLAVE1 0
  186. #define CFG_HRCW_SLAVE2 0
  187. #define CFG_HRCW_SLAVE3 0
  188. #define CFG_HRCW_SLAVE4 0
  189. #define CFG_HRCW_SLAVE5 0
  190. #define CFG_HRCW_SLAVE6 0
  191. #define CFG_HRCW_SLAVE7 0
  192. /*-----------------------------------------------------------------------
  193. * Internal Memory Mapped Register
  194. */
  195. #define CFG_IMMR 0xFF000000 /* We keep original value */
  196. /*-----------------------------------------------------------------------
  197. * Definitions for initial stack pointer and data area (in DPRAM)
  198. */
  199. #define CFG_INIT_RAM_ADDR CFG_IMMR
  200. #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
  201. #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  202. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  203. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  204. /*-----------------------------------------------------------------------
  205. * Internal Definitions
  206. *
  207. * Boot Flags
  208. */
  209. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  210. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  211. /*-----------------------------------------------------------------------
  212. * Cache Configuration
  213. */
  214. #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
  215. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  216. # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  217. #endif
  218. /*-----------------------------------------------------------------------
  219. * HIDx - Hardware Implementation-dependent Registers 2-11
  220. *-----------------------------------------------------------------------
  221. * HID0 also contains cache control.
  222. *
  223. * HID1 has only read-only information - nothing to set.
  224. */
  225. #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
  226. HID0_IFEM|HID0_ABE)
  227. #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
  228. #define CFG_HID2 0
  229. /*-----------------------------------------------------------------------
  230. * RMR - Reset Mode Register 5-5
  231. *-----------------------------------------------------------------------
  232. * turn on Checkstop Reset Enable
  233. */
  234. #define CFG_RMR RMR_CSRE
  235. /*-----------------------------------------------------------------------
  236. * BCR - Bus Configuration 4-25
  237. *-----------------------------------------------------------------------
  238. */
  239. #define CFG_BCR 0xA01C0000
  240. /*-----------------------------------------------------------------------
  241. * SIUMCR - SIU Module Configuration 4-31
  242. *-----------------------------------------------------------------------
  243. */
  244. #define CFG_SIUMCR 0X4205C000
  245. /*-----------------------------------------------------------------------
  246. * SYPCR - System Protection Control 4-35
  247. * SYPCR can only be written once after reset!
  248. *-----------------------------------------------------------------------
  249. * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  250. */
  251. #if defined (CONFIG_WATCHDOG)
  252. #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
  253. SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
  254. #else
  255. #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
  256. SYPCR_SWRI|SYPCR_SWP)
  257. #endif /* CONFIG_WATCHDOG */
  258. /*-----------------------------------------------------------------------
  259. * TMCNTSC - Time Counter Status and Control 4-40
  260. * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  261. * and enable Time Counter
  262. *-----------------------------------------------------------------------
  263. */
  264. #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
  265. /*-----------------------------------------------------------------------
  266. * PISCR - Periodic Interrupt Status and Control 4-42
  267. *-----------------------------------------------------------------------
  268. * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  269. * Periodic timer
  270. */
  271. #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
  272. /*-----------------------------------------------------------------------
  273. * SCCR - System Clock Control 9-8
  274. *-----------------------------------------------------------------------
  275. * Ensure DFBRG is Divide by 16
  276. */
  277. #define CFG_SCCR 0
  278. /*-----------------------------------------------------------------------
  279. * RCCR - RISC Controller Configuration 13-7
  280. *-----------------------------------------------------------------------
  281. */
  282. #define CFG_RCCR 0
  283. /*-----------------------------------------------------------------------
  284. * Init Memory Controller:
  285. *
  286. * Bank Bus Machine PortSz Device
  287. * ---- --- ------- ------ ------
  288. * 0 60x GPCM 64 bit FLASH
  289. * 1 60x SDRAM 64 bit SDRAM
  290. */
  291. #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) | 0x0801)
  292. #define CFG_OR0_PRELIM 0xFF800882
  293. #define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) | 0x0041)
  294. #define CFG_OR1_PRELIM 0xF8002CD0
  295. #define CFG_PSDMR 0x404A241A
  296. #define CFG_MPTPR 0x00007400
  297. #define CFG_PSRT 0x00000007
  298. #endif /* __CONFIG_H */