IP860.h 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459
  1. /*
  2. * (C) Copyright 2000
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * board/config.h - configuration options, board specific
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*
  29. * High Level Configuration Options
  30. * (easy to change)
  31. */
  32. #define CONFIG_MPC860 1 /* This is a MPC860 CPU */
  33. #define CONFIG_IP860 1 /* ...on a IP860 board */
  34. #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
  35. #define CONFIG_BAUDRATE 9600
  36. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  37. #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
  38. #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" \
  39. "\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 $(filesize)\0"
  40. #define CONFIG_ETHADDR 00:30:bf:01:02:d2
  41. #define CONFIG_IPADDR 10.0.0.5
  42. #define CONFIG_SERVERIP 10.0.0.2
  43. #undef CONFIG_BOOTARGS
  44. #define CONFIG_BOOTCOMMAND \
  45. "bootp; " \
  46. "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
  47. "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
  48. "bootm"
  49. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  50. #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
  51. #undef CONFIG_WATCHDOG /* watchdog disabled */
  52. /* enable I2C and select the hardware/software driver */
  53. #undef CONFIG_HARD_I2C /* I2C with hardware support */
  54. #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
  55. /*
  56. * Software (bit-bang) I2C driver configuration
  57. */
  58. #define PB_SCL 0x00000020 /* PB 26 */
  59. #define PB_SDA 0x00000010 /* PB 27 */
  60. #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
  61. #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
  62. #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
  63. #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
  64. #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
  65. else immr->im_cpm.cp_pbdat &= ~PB_SDA
  66. #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
  67. else immr->im_cpm.cp_pbdat &= ~PB_SCL
  68. #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
  69. # define CFG_I2C_SPEED 50000
  70. # define CFG_I2C_SLAVE 0xFE
  71. # define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */
  72. # define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
  73. /* mask of address bits that overflow into the "EEPROM chip address" */
  74. #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
  75. #define CFG_EEPROM_PAGE_WRITE_BITS 4
  76. #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
  77. #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
  78. CFG_CMD_BEDBUG | \
  79. CFG_CMD_I2C | \
  80. CFG_CMD_EEPROM)
  81. #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
  82. /*----------------------------------------------------------------------*/
  83. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  84. #include <cmd_confdefs.h>
  85. /*----------------------------------------------------------------------*/
  86. /*
  87. * Miscellaneous configurable options
  88. */
  89. #define CFG_LONGHELP /* undef to save memory */
  90. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  91. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  92. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  93. #else
  94. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  95. #endif
  96. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  97. #define CFG_MAXARGS 16 /* max number of command args */
  98. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  99. #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
  100. #define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
  101. #define CFG_LOAD_ADDR 0x00100000 /* default load address */
  102. #define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
  103. #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  104. #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  105. /*
  106. * Low Level Configuration Settings
  107. * (address mappings, register initial values, etc.)
  108. * You should know what you are doing if you make changes here.
  109. */
  110. /*-----------------------------------------------------------------------
  111. * Internal Memory Mapped Register
  112. */
  113. #define CFG_IMMR 0xF1000000 /* Non-standard value!! */
  114. /*-----------------------------------------------------------------------
  115. * Definitions for initial stack pointer and data area (in DPRAM)
  116. */
  117. #define CFG_INIT_RAM_ADDR CFG_IMMR
  118. #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
  119. #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
  120. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  121. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  122. /*-----------------------------------------------------------------------
  123. * Start addresses for the final memory configuration
  124. * (Set up by the startup code)
  125. * Please note that CFG_SDRAM_BASE _must_ start at 0
  126. */
  127. #define CFG_SDRAM_BASE 0x00000000
  128. #define CFG_FLASH_BASE 0x10000000
  129. #ifdef DEBUG
  130. #define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
  131. #else
  132. #if 0 /* need more space for I2C tests */
  133. #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
  134. #else
  135. #define CFG_MONITOR_LEN (256 << 10)
  136. #endif
  137. #endif
  138. #define CFG_MONITOR_BASE CFG_FLASH_BASE
  139. #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  140. /*
  141. * For booting Linux, the board info and command line data
  142. * have to be in the first 8 MB of memory, since this is
  143. * the maximum mapped by the Linux kernel during initialization.
  144. */
  145. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  146. /*-----------------------------------------------------------------------
  147. * FLASH organization
  148. */
  149. #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
  150. #define CFG_MAX_FLASH_SECT 124 /* max number of sectors on one chip */
  151. #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  152. #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  153. #undef CFG_ENV_IS_IN_FLASH
  154. #undef CFG_ENV_IS_IN_NVRAM
  155. #undef CFG_ENV_IS_IN_NVRAM
  156. #undef DEBUG_I2C
  157. #define CFG_ENV_IS_IN_EEPROM
  158. #ifdef CFG_ENV_IS_IN_NVRAM
  159. #define CFG_ENV_ADDR 0x20000000 /* use SRAM */
  160. #define CFG_ENV_SIZE (16<<10) /* use 16 kB */
  161. #endif /* CFG_ENV_IS_IN_NVRAM */
  162. #ifdef CFG_ENV_IS_IN_EEPROM
  163. #define CFG_ENV_OFFSET 512 /* Leave 512 bytes free for other data */
  164. #define CFG_ENV_SIZE 1536 /* Use remaining space */
  165. #endif /* CFG_ENV_IS_IN_EEPROM */
  166. /*-----------------------------------------------------------------------
  167. * Cache Configuration
  168. */
  169. #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
  170. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  171. #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
  172. #endif
  173. /*-----------------------------------------------------------------------
  174. * SYPCR - System Protection Control 11-9
  175. * SYPCR can only be written once after reset!
  176. *-----------------------------------------------------------------------
  177. * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  178. * +0x0004
  179. */
  180. #if defined(CONFIG_WATCHDOG)
  181. #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
  182. SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
  183. #else
  184. #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
  185. #endif
  186. /*-----------------------------------------------------------------------
  187. * SIUMCR - SIU Module Configuration 11-6
  188. *-----------------------------------------------------------------------
  189. * +0x0000 => 0x80600800
  190. */
  191. #define CFG_SIUMCR (SIUMCR_EARB | SIUMCR_EARP0 | \
  192. SIUMCR_DBGC11 | SIUMCR_MLRC10)
  193. /*-----------------------------------------------------------------------
  194. * Clock Setting - the IP860 has no 32kHz clock, so automatic detection fails
  195. *-----------------------------------------------------------------------
  196. */
  197. #define CONFIG_8xx_GCLK_FREQ 50000000
  198. /*-----------------------------------------------------------------------
  199. * TBSCR - Time Base Status and Control 11-26
  200. *-----------------------------------------------------------------------
  201. * Clear Reference Interrupt Status, Timebase freezing enabled
  202. * +0x0200 => 0x00C2
  203. */
  204. #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
  205. /*-----------------------------------------------------------------------
  206. * PISCR - Periodic Interrupt Status and Control 11-31
  207. *-----------------------------------------------------------------------
  208. * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  209. * +0x0240 => 0x0082
  210. */
  211. #define CFG_PISCR (PISCR_PS | PISCR_PITF)
  212. /*-----------------------------------------------------------------------
  213. * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
  214. *-----------------------------------------------------------------------
  215. * Reset PLL lock status sticky bit, timer expired status bit and timer
  216. * interrupt status bit, set PLL multiplication factor !
  217. */
  218. /* +0x0286 => was: 0x0000D000 */
  219. #define CFG_PLPRCR \
  220. ( PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
  221. /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
  222. PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
  223. )
  224. /*-----------------------------------------------------------------------
  225. * SCCR - System Clock and reset Control Register 15-27
  226. *-----------------------------------------------------------------------
  227. * Set clock output, timebase and RTC source and divider,
  228. * power management and some other internal clocks
  229. */
  230. #define SCCR_MASK SCCR_EBDF11
  231. #define CFG_SCCR (SCCR_COM00 | SCCR_TBS | \
  232. SCCR_RTDIV | SCCR_RTSEL | \
  233. /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
  234. SCCR_EBDF00 | SCCR_DFSYNC00 | \
  235. SCCR_DFBRG00 | SCCR_DFNL000 | \
  236. SCCR_DFNH000)
  237. /*-----------------------------------------------------------------------
  238. * RTCSC - Real-Time Clock Status and Control Register 11-27
  239. *-----------------------------------------------------------------------
  240. */
  241. /* +0x0220 => 0x00C3 */
  242. #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
  243. /*-----------------------------------------------------------------------
  244. * RCCR - RISC Controller Configuration Register 19-4
  245. *-----------------------------------------------------------------------
  246. */
  247. /* +0x09C4 => TIMEP=1 */
  248. #define CFG_RCCR 0x0100
  249. /*-----------------------------------------------------------------------
  250. * RMDS - RISC Microcode Development Support Control Register
  251. *-----------------------------------------------------------------------
  252. */
  253. #define CFG_RMDS 0
  254. /*-----------------------------------------------------------------------
  255. * DER - Debug Event Register
  256. *-----------------------------------------------------------------------
  257. *
  258. */
  259. /*#define CFG_DER 0x2002000F*/
  260. #define CFG_DER 0
  261. /*
  262. * Init Memory Controller:
  263. */
  264. /*
  265. * MAMR settings for SDRAM - 16-14
  266. * => 0xC3804114
  267. */
  268. /* periodic timer for refresh */
  269. #define CFG_MAMR_PTA 0xC3
  270. #define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  271. MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
  272. MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  273. /*
  274. * BR1 and OR1 (FLASH)
  275. */
  276. #define FLASH_BASE 0x10000000 /* FLASH bank #0 */
  277. /* used to re-map FLASH
  278. * restrict access enough to keep SRAM working (if any)
  279. * but not too much to meddle with FLASH accesses
  280. */
  281. /* allow for max 8 MB of Flash */
  282. #define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */
  283. #define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
  284. #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)
  285. #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
  286. #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
  287. /* 16 bit, bank valid */
  288. #define CFG_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
  289. #define CFG_OR1_PRELIM CFG_OR0_PRELIM
  290. #define CFG_BR1_PRELIM CFG_BR0_PRELIM
  291. /*
  292. * BR2/OR2 - SDRAM
  293. */
  294. #define SDRAM_BASE 0x00000000 /* SDRAM bank */
  295. #define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
  296. #define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
  297. #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
  298. #define CFG_OR2 (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
  299. #define CFG_BR2 ((SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V )
  300. /*
  301. * BR3/OR3 - SRAM (16 bit)
  302. */
  303. #define SRAM_BASE 0x20000000
  304. #define CFG_OR3 0xFFF00130 /* BI/SCY = 5/TRLX (internal) */
  305. #define CFG_BR3 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
  306. #define SRAM_SIZE (1 + (~(CFG_OR3 & BR_BA_MSK)))
  307. #define CFG_OR3_PRELIM CFG_OR3 /* Make sure to map early */
  308. #define CFG_BR3_PRELIM CFG_BR3 /* in case it's used for ENV */
  309. /*
  310. * BR4/OR4 - Board Control & Status (8 bit)
  311. */
  312. #define BCSR_BASE 0xFC000000
  313. #define CFG_OR4 0xFFFF0120 /* BI (internal) */
  314. #define CFG_BR4 ((BCSR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
  315. /*
  316. * BR5/OR5 - IP Slot A/B (16 bit)
  317. */
  318. #define IP_SLOT_BASE 0x40000000
  319. #define CFG_OR5 0xFE00010C /* SETA/TRLX/BI/ SCY=0 (external) */
  320. #define CFG_BR5 ((IP_SLOT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
  321. /*
  322. * BR6/OR6 - VME STD (16 bit)
  323. */
  324. #define VME_STD_BASE 0xFE000000
  325. #define CFG_OR6 0xFF00010C /* SETA/TRLX/BI/SCY=0 (external) */
  326. #define CFG_BR6 ((VME_STD_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
  327. /*
  328. * BR7/OR7 - SHORT I/O + RTC + IACK (16 bit)
  329. */
  330. #define VME_SHORT_BASE 0xFF000000
  331. #define CFG_OR7 0xFF00010C /* SETA/TRLX/BI/ SCY=0 (external) */
  332. #define CFG_BR7 ((VME_SHORT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
  333. /*-----------------------------------------------------------------------
  334. * Board Control and Status Region:
  335. *-----------------------------------------------------------------------
  336. */
  337. #ifndef __ASSEMBLY__
  338. typedef struct ip860_bcsr_s {
  339. unsigned char shmem_addr; /* +00 shared memory address register */
  340. unsigned char reserved0;
  341. unsigned char mbox_addr; /* +02 mailbox address register */
  342. unsigned char reserved1;
  343. unsigned char vme_int_mask; /* +04 VME Bus interrupt mask register */
  344. unsigned char reserved2;
  345. unsigned char vme_int_pend; /* +06 VME interrupt pending register */
  346. unsigned char reserved3;
  347. unsigned char bd_int_mask; /* +08 board interrupt mask register */
  348. unsigned char reserved4;
  349. unsigned char bd_int_pend; /* +0A board interrupt pending register */
  350. unsigned char reserved5;
  351. unsigned char bd_ctrl; /* +0C board control register */
  352. unsigned char reserved6;
  353. unsigned char bd_status; /* +0E board status register */
  354. unsigned char reserved7;
  355. unsigned char vme_irq; /* +10 VME interrupt request register */
  356. unsigned char reserved8;
  357. unsigned char vme_ivec; /* +12 VME interrupt vector register */
  358. unsigned char reserved9;
  359. unsigned char cli_mbox; /* +14 clear mailbox irq */
  360. unsigned char reservedA;
  361. unsigned char rtc; /* +16 RTC control register */
  362. unsigned char reservedB;
  363. unsigned char mbox_data; /* +18 mailbox read/write register */
  364. unsigned char reservedC;
  365. unsigned char wd_trigger; /* +1A Watchdog trigger register */
  366. unsigned char reservedD;
  367. unsigned char rmw_req; /* +1C RMW request register */
  368. } ip860_bcsr_t;
  369. #endif /* __ASSEMBLY__ */
  370. /*-----------------------------------------------------------------------
  371. * Board Control Register: bd_ctrl (Offset 0x0C)
  372. *-----------------------------------------------------------------------
  373. */
  374. #define BD_CTRL_IPLSE 0x80 /* IP Slot Long Select Enable */
  375. #define BD_CTRL_WDOGE 0x40 /* Watchdog Enable */
  376. #define BD_CTRL_FLWE 0x20 /* Flash Write Enable */
  377. #define BD_CTRL_RWDN 0x10 /* VMEBus Requester Release When Done Enable */
  378. /*-----------------------------------------------------------------------
  379. *
  380. *-----------------------------------------------------------------------
  381. *
  382. */
  383. /*
  384. * Internal Definitions
  385. *
  386. * Boot Flags
  387. */
  388. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  389. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  390. #endif /* __CONFIG_H */