ETX094.h 13 KB

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  1. /*
  2. * (C) Copyright 2000
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * board/config.h - configuration options, board specific
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*
  29. * High Level Configuration Options
  30. * (easy to change)
  31. */
  32. #define CONFIG_MPC850 1 /* This is a MPC850 CPU */
  33. #define CONFIG_ETX094 1 /* ...on a ETX_094 board */
  34. #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
  35. #undef CONFIG_8xx_CONS_SMC2
  36. #undef CONFIG_8xx_CONS_NONE
  37. #define CONFIG_BAUDRATE 57600
  38. #if 0
  39. #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
  40. #else
  41. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  42. #endif
  43. #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
  44. #define CONFIG_BOARD_TYPES 1 /* support board types */
  45. #define CONFIG_FLASH_16BIT /* for board with 16bit wide flash */
  46. #undef SB_ETX094 /* only for SB-Board with 16MB SDRAM */
  47. #define CONFIG_BOOTP_RANDOM_DELAY /* graceful BOOTP recovery mode */
  48. #define CONFIG_ETHADDR 08:00:06:00:00:00
  49. #ifdef CONFIG_ETHADDR
  50. #define CONFIG_OVERWRITE_ETHADDR_ONCE 1 /* default MAC can be overwritten once */
  51. #endif
  52. #undef CONFIG_BOOTARGS
  53. #define CONFIG_RAMBOOTCOMMAND \
  54. "bootp; " \
  55. "setenv bootargs root=/dev/ram rw ramdisk_size=4690 " \
  56. "U-Boot_version=U-Boot-1.0.x-Date " \
  57. "panic=1 " \
  58. "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
  59. "bootm"
  60. #define CONFIG_NFSBOOTCOMMAND \
  61. "bootp; " \
  62. "setenv bootargs root=/dev/nfs rw nfsroot=$(nfsip):$(rootpath) " \
  63. "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
  64. "bootm"
  65. #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
  66. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  67. #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
  68. #define CONFIG_WATCHDOG 1 /* watchdog enabled */
  69. #define CONFIG_STATUS_LED 1 /* Status LED enabled */
  70. #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
  71. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  72. #include <cmd_confdefs.h>
  73. /*
  74. * Miscellaneous configurable options
  75. */
  76. #define CFG_LONGHELP /* undef to save memory */
  77. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  78. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  79. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  80. #else
  81. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  82. #endif
  83. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  84. #define CFG_MAXARGS 16 /* max number of command args */
  85. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  86. #define CFG_MEMTEST_START 0x0300000 /* memtest works on */
  87. #define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
  88. #define CFG_LOAD_ADDR 0x100000 /* default load address */
  89. #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  90. #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  91. /*
  92. * Low Level Configuration Settings
  93. * (address mappings, register initial values, etc.)
  94. * You should know what you are doing if you make changes here.
  95. */
  96. /*-----------------------------------------------------------------------
  97. * Internal Memory Mapped Register
  98. */
  99. #define CFG_IMMR 0xFFF00000
  100. /*-----------------------------------------------------------------------
  101. * Definitions for initial stack pointer and data area (in DPRAM)
  102. */
  103. #define CFG_INIT_RAM_ADDR CFG_IMMR
  104. #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
  105. #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
  106. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  107. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  108. /*-----------------------------------------------------------------------
  109. * Start addresses for the final memory configuration
  110. * (Set up by the startup code)
  111. * Please note that CFG_SDRAM_BASE _must_ start at 0
  112. */
  113. #define CFG_SDRAM_BASE 0x00000000
  114. #define CFG_FLASH_BASE 0x40000000
  115. #ifdef DEBUG
  116. #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  117. #else
  118. #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  119. #endif
  120. #define CFG_MONITOR_BASE CFG_FLASH_BASE
  121. #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  122. /*
  123. * For booting Linux, the board info and command line data
  124. * have to be in the first 8 MB of memory, since this is
  125. * the maximum mapped by the Linux kernel during initialization.
  126. */
  127. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  128. /*-----------------------------------------------------------------------
  129. * FLASH organization
  130. */
  131. #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
  132. #define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
  133. #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  134. #define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
  135. #define CFG_ENV_IS_IN_FLASH 1
  136. #ifdef CONFIG_FLASH_16BIT
  137. #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
  138. #define CFG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */
  139. #else
  140. #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
  141. #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
  142. #endif
  143. /*-----------------------------------------------------------------------
  144. * Hardware Information Block
  145. */
  146. #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
  147. #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
  148. #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
  149. /*-----------------------------------------------------------------------
  150. * Cache Configuration
  151. */
  152. #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
  153. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  154. #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
  155. #endif
  156. /*-----------------------------------------------------------------------
  157. * SYPCR - System Protection Control 11-9
  158. * SYPCR can only be written once after reset!
  159. *-----------------------------------------------------------------------
  160. * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  161. */
  162. #if defined(CONFIG_WATCHDOG)
  163. #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
  164. SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
  165. #else
  166. #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
  167. #endif /* CONFIG_WATCHDOG */
  168. /*-----------------------------------------------------------------------
  169. * SIUMCR - SIU Module Configuration 11-6
  170. *-----------------------------------------------------------------------
  171. * PCMCIA config., multi-function pin tri-state
  172. */
  173. #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
  174. /*-----------------------------------------------------------------------
  175. * TBSCR - Time Base Status and Control 11-26
  176. *-----------------------------------------------------------------------
  177. * Clear Reference Interrupt Status, Timebase freezing enabled
  178. */
  179. #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
  180. /*-----------------------------------------------------------------------
  181. * RTCSC - Real-Time Clock Status and Control Register 11-27
  182. *-----------------------------------------------------------------------
  183. */
  184. #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
  185. /*-----------------------------------------------------------------------
  186. * PISCR - Periodic Interrupt Status and Control 11-31
  187. *-----------------------------------------------------------------------
  188. * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  189. */
  190. #define CFG_PISCR (PISCR_PS | PISCR_PITF)
  191. /*-----------------------------------------------------------------------
  192. * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
  193. *-----------------------------------------------------------------------
  194. * Reset PLL lock status sticky bit, timer expired status bit and timer
  195. * interrupt status bit - leave PLL multiplication factor unchanged !
  196. */
  197. #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
  198. /*-----------------------------------------------------------------------
  199. * SCCR - System Clock and reset Control Register 15-27
  200. *-----------------------------------------------------------------------
  201. * Set clock output, timebase and RTC source and divider,
  202. * power management and some other internal clocks
  203. */
  204. #define SCCR_MASK SCCR_EBDF11
  205. #define CFG_SCCR (SCCR_TBS | \
  206. SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
  207. SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
  208. SCCR_DFALCD00)
  209. /*-----------------------------------------------------------------------
  210. * PCMCIA stuff
  211. *-----------------------------------------------------------------------
  212. *
  213. */
  214. #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
  215. #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
  216. #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
  217. #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
  218. #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
  219. #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
  220. #define CFG_PCMCIA_IO_ADDR (0xEC000000)
  221. #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
  222. /*-----------------------------------------------------------------------
  223. *
  224. *-----------------------------------------------------------------------
  225. *
  226. */
  227. /*#define CFG_DER 0x2002000F*/
  228. #define CFG_DER 0
  229. /*
  230. * Init Memory Controller:
  231. *
  232. * BR0/1 and OR0/1 (FLASH)
  233. */
  234. #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
  235. #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
  236. /* used to re-map FLASH both when starting from SRAM or FLASH:
  237. * restrict access enough to keep SRAM working (if any)
  238. * but not too much to meddle with FLASH accesses
  239. */
  240. #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
  241. #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
  242. /* FLASH timing: ACS = 11, TRLX = 1, CSNT = 0, SCY = 2, EHTR = 0 */
  243. #define CFG_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_BI | \
  244. OR_SCY_2_CLK | OR_TRLX )
  245. #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
  246. #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
  247. #ifdef CONFIG_FLASH_16BIT /* 16 bit data port */
  248. #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
  249. #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
  250. #else /* 32 bit data port */
  251. #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32)
  252. #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32)
  253. #endif /* CONFIG_FLASH_16BIT */
  254. #define CFG_OR1_REMAP CFG_OR0_REMAP
  255. #define CFG_OR1_PRELIM CFG_OR0_PRELIM
  256. /*
  257. * BR2/3 and OR2/3 (SDRAM)
  258. *
  259. */
  260. #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
  261. #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
  262. #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
  263. /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
  264. #define CFG_OR_TIMING_SDRAM 0x00000A00
  265. #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
  266. #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
  267. #define CFG_OR3_PRELIM CFG_OR2_PRELIM
  268. #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
  269. /*
  270. * Memory Periodic Timer Prescaler
  271. */
  272. /* periodic timer for refresh */
  273. #define CFG_MAMR_PTA 23 /* start with divider for 100 MHz */
  274. /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
  275. #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
  276. #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
  277. /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
  278. #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
  279. #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
  280. /*
  281. * MAMR settings for SDRAM
  282. */
  283. /* 8 column SDRAM */
  284. #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  285. MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
  286. MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X)
  287. /* 9 column SDRAM */
  288. #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  289. MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
  290. MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X)
  291. /*
  292. * Internal Definitions
  293. *
  294. * Boot Flags
  295. */
  296. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  297. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  298. #endif /* __CONFIG_H */