ERIC.h 15 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * board/config.h - configuration options, board specific
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*
  29. * High Level Configuration Options
  30. * (easy to change)
  31. */
  32. #define CONFIG_405GP 1 /* This is a PPC405 CPU */
  33. #define CONFIG_4xx 1 /* ...member of PPC4xx family */
  34. #define CONFIG_ERIC 1 /* ...on a ERIC board */
  35. #define CONFIG_BOARD_PRE_INIT 1 /* run board_pre_init() */
  36. #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
  37. #if 1
  38. #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
  39. #endif
  40. #if 0
  41. #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
  42. #endif
  43. #if 0
  44. #define CFG_ENV_IS_IN_EEPROM 1 /* use I2C RTC X1240 for environment vars */
  45. #define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
  46. #define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars */
  47. #endif /* total size of a X1240 is 2048 bytes */
  48. #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
  49. #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
  50. #define CFG_I2C_SLAVE 0x7F
  51. #define CFG_I2C_EEPROM_ADDR 0x57 /* X1240 has two I2C slave addresses, one for EEPROM */
  52. #define CFG_I2C_EEPROM_ADDR_LEN 2 /* address length for the eeprom */
  53. #define CONFIG_I2C_RTC 1 /* we have a Xicor X1240 RTC */
  54. #define CFG_I2C_RTC_ADDR 0x6F /* and one for RTC */
  55. #ifdef CFG_ENV_IS_IN_FLASH
  56. #undef CFG_ENV_IS_IN_NVRAM
  57. #undef CFG_ENV_IS_IN_EEPROM
  58. #else
  59. #ifdef CFG_ENV_IS_IN_NVRAM
  60. #undef CFG_ENV_IS_IN_FLASH
  61. #undef CFG_ENV_IS_IN_EEPROM
  62. #else
  63. #ifdef CFG_ENV_IS_IN_EEPROM
  64. #undef CFG_ENV_IS_IN_NVRAM
  65. #undef CFG_ENV_IS_IN_FLASH
  66. #endif
  67. #endif
  68. #endif
  69. #define CONFIG_BAUDRATE 115200
  70. #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
  71. #if 1
  72. #define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
  73. #else
  74. #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
  75. #endif
  76. #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs " \
  77. "nfsroot=192.168.1.2:/eric_root_devel " \
  78. "ip=192.168.1.22:192.168.1.2"
  79. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  80. #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  81. #define CONFIG_MII 1 /* MII PHY management */
  82. #define CONFIG_PHY_ADDR 1 /* PHY address */
  83. #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
  84. CFG_CMD_PCI | \
  85. CFG_CMD_IRQ | \
  86. CFG_CMD_ENV | \
  87. CFG_CMD_FLASH)
  88. /*
  89. * #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | \
  90. * CFG_CMD_KGDB | CFG_CMD_I2C | CFG_CMD_EEPROM | \
  91. * CFG_CMD_ENV | CFG_CMD_FLASH)
  92. */
  93. /* CFG_CMD_ENV est definie */
  94. /* ((CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_KGDB) & ~(CFG_CMD_ENV))
  95. */
  96. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  97. #include <cmd_confdefs.h>
  98. #undef CONFIG_WATCHDOG /* watchdog disabled */
  99. /*
  100. * Miscellaneous configurable options
  101. */
  102. #undef CFG_LONGHELP /* undef to save memory */
  103. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  104. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  105. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  106. #else
  107. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  108. #endif
  109. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  110. #define CFG_MAXARGS 16 /* max number of command args */
  111. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  112. #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
  113. #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  114. #define CFG_EXT_SERIAL_CLOCK 14318180
  115. /* The following table includes the supported baudrates */
  116. #define CFG_BAUDRATE_TABLE \
  117. { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
  118. 57600, 115200, 230400, 460800, 921600 }
  119. #define CFG_LOAD_ADDR 0x100000 /* default load address */
  120. #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
  121. #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  122. /*-----------------------------------------------------------------------
  123. * PCI stuff
  124. *-----------------------------------------------------------------------
  125. */
  126. #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
  127. #define PCI_HOST_FORCE 1 /* configure as pci host */
  128. #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
  129. #define CONFIG_PCI /* include pci support */
  130. #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
  131. #undef CONFIG_PCI_PNP /* no pci plug-and-play */
  132. /* resource configuration */
  133. #define CFG_PCI_SUBSYS_VENDORID 0x1743 /* PCI Vendor ID: Peppercon AG */
  134. #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: 405GP */
  135. #define CFG_PCI_PTM1LA 0xFFFC0000 /* point to flash */
  136. #define CFG_PCI_PTM1MS 0xFFFFF001 /* 4kB, enable hard-wired to 1 */
  137. #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
  138. #define CFG_PCI_PTM2LA 0x00000000 /* disabled */
  139. #define CFG_PCI_PTM2MS 0x00000000 /* disabled */
  140. #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
  141. /*-----------------------------------------------------------------------
  142. * External peripheral base address
  143. *-----------------------------------------------------------------------
  144. */
  145. /* Bank 0 - Flash/SRAM 0xFF000000 16MB 16 Bit */
  146. /* Bank 1 - NVRAM/RTC 0xF0000000 1MB 8 Bit */
  147. /* Bank 2 - A/D converter 0xF0100000 1MB 8 Bit */
  148. /* Bank 3 - Ethernet PHY Reset 0xF0200000 1MB 8 Bit */
  149. /* Bank 4 - PC-MIP PRSNT1# 0xF0300000 1MB 8 Bit */
  150. /* Bank 5 - PC-MIP PRSNT2# 0xF0400000 1MB 8 Bit */
  151. /* Bank 6 - CPU LED0 0xF0500000 1MB 8 Bit */
  152. /* Bank 7 - CPU LED1 0xF0600000 1MB 8 Bit */
  153. /* ----------------------------------------------------------------------- */
  154. /* Memory Bank 0 (Flash) initialization */
  155. /* ----------------------------------------------------------------------- */
  156. #define CS0_AP 0x9B015480
  157. #define CS0_CR 0xFF87A000 /* BAS=0xFF8,BS=(8MB),BU=0x3(R/W), BW=(16 bits) */
  158. /* ----------------------------------------------------------------------- */
  159. /* Memory Bank 1 (NVRAM/RTC) initialization */
  160. /* ----------------------------------------------------------------------- */
  161. #define CS1_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
  162. #define CS1_CR 0xF0018000 /* BAS=0xF00,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
  163. /* ----------------------------------------------------------------------- */
  164. /* Memory Bank 2 (A/D converter) initialization */
  165. /* ----------------------------------------------------------------------- */
  166. #define CS2_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
  167. #define CS2_CR 0xF0118000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
  168. /* ----------------------------------------------------------------------- */
  169. /* Memory Bank 3 (Ethernet PHY Reset) initialization */
  170. /* ----------------------------------------------------------------------- */
  171. #define CS3_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
  172. #define CS3_CR 0xF0218000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
  173. /* ----------------------------------------------------------------------- */
  174. /* Memory Bank 4 (PC-MIP PRSNT1#) initialization */
  175. /* ----------------------------------------------------------------------- */
  176. #define CS4_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
  177. #define CS4_CR 0xF0318000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
  178. /* ----------------------------------------------------------------------- */
  179. /* Memory Bank 5 (PC-MIP PRSNT2#) initialization */
  180. /* ----------------------------------------------------------------------- */
  181. #define CS5_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
  182. #define CS5_CR 0xF0418000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
  183. /* ----------------------------------------------------------------------- */
  184. /* Memory Bank 6 (CPU LED0) initialization */
  185. /* ----------------------------------------------------------------------- */
  186. #define CS6_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
  187. #define CS6_CR 0xF0518000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
  188. /* ----------------------------------------------------------------------- */
  189. /* Memory Bank 7 (CPU LED1) initialization */
  190. /* ----------------------------------------------------------------------- */
  191. #define CS7_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
  192. #define CS7_CR 0xF0618000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
  193. #define CFG_NVRAM_REG_BASE_ADDR 0xF0000000
  194. #define CFG_RTC_REG_BASE_ADDR (0xF0000000 + 0x7F8)
  195. #define CFG_ADC_REG_BASE_ADDR 0xF0100000
  196. #define CFG_PHYRES_REG_BASE_ADDR 0xF0200000
  197. #define CFG_PRSNT1_REG_BASE_ADDR 0xF0300000
  198. #define CFG_PRSNT2_REG_BASE_ADDR 0xF0400000
  199. #define CFG_LED0_REG_BASE_ADDR 0xF0500000
  200. #define CFG_LED1_REG_BASE_ADDR 0xF0600000
  201. /* SDRAM CONFIG */
  202. #define CFG_SDRAM_MANUALLY 1
  203. #define CFG_SDRAM_SINGLE_BANK 1
  204. #ifdef CFG_SDRAM_MANUALLY
  205. /*-----------------------------------------------------------------------
  206. * Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2)
  207. *----------------------------------------------------------------------*/
  208. #define MB0CF 0x00062001 /* 32MB @ 0 */
  209. /*-----------------------------------------------------------------------
  210. * Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2)
  211. *----------------------------------------------------------------------*/
  212. #ifdef CFG_SDRAM_SINGLE_BANK
  213. #define MB1CF 0x0 /* 0MB @ 32MB */
  214. #else
  215. #define MB1CF 0x02062001 /* 32MB @ 32MB */
  216. #endif
  217. /*-----------------------------------------------------------------------
  218. * Set MB2CF for bank 2. off
  219. *----------------------------------------------------------------------*/
  220. #define MB2CF 0x0 /* 0MB */
  221. /*-----------------------------------------------------------------------
  222. * Set MB3CF for bank 3. off
  223. *----------------------------------------------------------------------*/
  224. #define MB3CF 0x0 /* 0MB */
  225. #define SDTR_100 0x0086400D
  226. #define RTR_100 0x05F0
  227. #define SDTR_66 0x00854006 /* orig U-Boot-wallnut says 0x00854006 */
  228. #define RTR_66 0x03f8
  229. #endif /* CFG_SDRAM_MANUALLY */
  230. /*-----------------------------------------------------------------------
  231. * Start addresses for the final memory configuration
  232. * (Set up by the startup code)
  233. * Please note that CFG_SDRAM_BASE _must_ start at 0
  234. */
  235. #define CFG_SDRAM_BASE 0x00000000
  236. #define CFG_SDRAM_SIZE 32
  237. #define CFG_FLASH_BASE 0xFF800000 /* 8 MByte Flash */
  238. #define CFG_MONITOR_BASE 0xFFFE0000 /* last 128kByte within Flash */
  239. /*#define CFG_MONITOR_LEN (192 * 1024)*/ /* Reserve 196 kB for Monitor */
  240. #define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128 kB for Monitor */
  241. #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
  242. /*
  243. * For booting Linux, the board info and command line data
  244. * have to be in the first 8 MB of memory, since this is
  245. * the maximum mapped by the Linux kernel during initialization.
  246. */
  247. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  248. /*-----------------------------------------------------------------------
  249. * FLASH organization
  250. */
  251. #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
  252. #define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
  253. #define CFG_FLASH_16BIT 1 /* Rom 16 bit data bus */
  254. #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  255. #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  256. /* BEG ENVIRONNEMENT FLASH */
  257. #ifdef CFG_ENV_IS_IN_FLASH
  258. #define CFG_ENV_SECT_SIZE (128*1024)
  259. #if 0 /* force ENV to be NOT embedded */
  260. #define CFG_ENV_ADDR 0xfffa0000
  261. #else /* force ENV to be embedded */
  262. #define CFG_ENV_SIZE (2 * 1024) /* Total Size of Environment Sector 2k */
  263. #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN - CFG_ENV_SIZE - 0x10) /* let space for reset vector */
  264. /* #define CFG_ENV_ADDR (CFG_MONITOR_BASE)*/
  265. #define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
  266. #endif
  267. #endif
  268. /* END ENVIRONNEMENT FLASH */
  269. /*-----------------------------------------------------------------------
  270. * NVRAM organization
  271. */
  272. #define CFG_NVRAM_BASE_ADDR CFG_NVRAM_REG_BASE_ADDR /* NVRAM base address */
  273. #define CFG_NVRAM_SIZE 0x7F8 /* NVRAM size 2kByte - 8 Byte for RTC */
  274. #ifdef CFG_ENV_IS_IN_NVRAM
  275. #define CFG_ENV_SIZE 0x7F8 /* Size of Environment vars */
  276. #define CFG_ENV_ADDR \
  277. (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
  278. #endif
  279. /*-----------------------------------------------------------------------
  280. * Cache Configuration
  281. */
  282. #define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
  283. #define CFG_CACHELINE_SIZE 32 /* ... */
  284. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  285. #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  286. #endif
  287. /*
  288. * Init Memory Controller:
  289. *
  290. * BR0/1 and OR0/1 (FLASH)
  291. */
  292. #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 8MB */
  293. #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
  294. /* Configuration Port location */
  295. /* #define CONFIG_PORT_ADDR 0xF0000500 */
  296. /*-----------------------------------------------------------------------
  297. * Definitions for initial stack pointer and data area (in DPRAM)
  298. */
  299. #define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
  300. #define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */
  301. #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
  302. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  303. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  304. /*-----------------------------------------------------------------------
  305. * Definitions for Serial Presence Detect EEPROM address
  306. * (to get SDRAM settings)
  307. */
  308. #define SPD_EEPROM_ADDRESS 0x50
  309. /*
  310. * Internal Definitions
  311. *
  312. * Boot Flags
  313. */
  314. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  315. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  316. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  317. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  318. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  319. #endif
  320. #endif /* __CONFIG_H */