ELPPC.h 10 KB

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  1. /*
  2. * (C) Copyright 2002 ELTEC Elektronik AG
  3. * Frank Gottschling <fgottschling@eltec.de>
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * board/config.h - configuration options, board specific
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. #include <asm/processor.h>
  29. #undef DEBUG
  30. #define GTREGREAD(x) 0xffffffff /* needed for debug */
  31. /*
  32. * High Level Configuration Options
  33. * (easy to change)
  34. */
  35. /* these hardware addresses are pretty bogus, please change them to
  36. suit your needs */
  37. /* first ethernet */
  38. #define CONFIG_ETHADDR 00:00:5b:ee:de:ad
  39. #define CONFIG_IPADDR 192.168.0.105
  40. #define CONFIG_SERVERIP 192.168.0.100
  41. #define CONFIG_ELPPC 1 /* this is an BAB740/BAB750 board */
  42. #define CONFIG_BAUDRATE 9600 /* console baudrate */
  43. #undef CONFIG_WATCHDOG
  44. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  45. #define CONFIG_ZERO_BOOTDELAY_CHECK
  46. #undef CONFIG_BOOTARGS
  47. #define CONFIG_BOOTCOMMAND \
  48. "bootp 1000000; " \
  49. "setenv bootargs root=ramfs console=ttyS00,9600 " \
  50. "ip=$(ipaddr):$(serverip):$(rootpath):$(gatewayip):" \
  51. "$(netmask):$(hostname):eth0:none; " \
  52. "bootm"
  53. #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
  54. #define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
  55. #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
  56. #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2)
  57. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  58. #include <cmd_confdefs.h>
  59. /*
  60. * Miscellaneous configurable options
  61. */
  62. #define CFG_LONGHELP /* undef to save memory */
  63. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  64. /*
  65. * choose between COM1 and COM2 as serial console
  66. */
  67. #define CONFIG_CONS_INDEX 1
  68. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  69. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  70. #else
  71. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  72. #endif
  73. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  74. #define CFG_MAXARGS 16 /* max number of command args */
  75. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  76. #define CFG_MEMTEST_START 0x00000000 /* memtest works on */
  77. #define CFG_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */
  78. #define CFG_LOAD_ADDR 0x1000000 /* default load address */
  79. #define CFG_HZ 1000 /* dec. freq: 1 ms ticks */
  80. #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
  81. /*
  82. * Low Level Configuration Settings
  83. * (address mappings, register initial values, etc.)
  84. * You should know what you are doing if you make changes here.
  85. */
  86. #define CFG_BOARD_ASM_INIT
  87. #define CONFIG_MISC_INIT_R
  88. /*
  89. * Address mapping scheme for the MPC107 mem controller is mapping B (CHRP)
  90. */
  91. #undef CFG_ADDRESS_MAP_A
  92. #define CFG_PCI_MEMORY_BUS 0x00000000
  93. #define CFG_PCI_MEMORY_PHYS 0x00000000
  94. #define CFG_PCI_MEMORY_SIZE 0x40000000
  95. #define CFG_PCI_MEM_BUS 0x80000000
  96. #define CFG_PCI_MEM_PHYS 0x80000000
  97. #define CFG_PCI_MEM_SIZE 0x7d000000
  98. #define CFG_ISA_MEM_BUS 0x00000000
  99. #define CFG_ISA_MEM_PHYS 0xfd000000
  100. #define CFG_ISA_MEM_SIZE 0x01000000
  101. #define CFG_PCI_IO_BUS 0x00800000
  102. #define CFG_PCI_IO_PHYS 0xfe800000
  103. #define CFG_PCI_IO_SIZE 0x00400000
  104. #define CFG_ISA_IO_BUS 0x00000000
  105. #define CFG_ISA_IO_PHYS 0xfe000000
  106. #define CFG_ISA_IO_SIZE 0x00800000
  107. /* driver defines FDC,IDE,... */
  108. #define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
  109. #define CFG_ISA_IO CFG_ISA_IO_PHYS
  110. #define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS
  111. /*
  112. * Start addresses for the final memory configuration
  113. * (Set up by the startup code)
  114. * Please note that CFG_SDRAM_BASE _must_ start at 0
  115. */
  116. #define CFG_SDRAM_BASE 0x00000000
  117. #define CFG_USR_LED_BASE 0x78000000
  118. #define CFG_NVRAM_BASE 0xff000000
  119. #define CFG_UART_BASE 0xff400000
  120. #define CFG_FLASH_BASE 0xfff00000
  121. #define MPC107_EUMB_ADDR 0xfce00000
  122. #define MPC107_EUMB_PI 0xfce41090
  123. #define MPC107_EUMB_GCR 0xfce41020
  124. #define MPC107_EUMB_IACKR 0xfce600a0
  125. #define MPC107_I2C_ADDR 0xfce03000
  126. /*
  127. * Definitions for initial stack pointer and data area
  128. */
  129. #define CFG_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */
  130. #define CFG_INIT_RAM_END 0x4000
  131. #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for init data */
  132. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  133. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  134. /*
  135. * Flash mapping/organization on the MPC10x.
  136. */
  137. #define FLASH_BASE0_PRELIM 0xff800000
  138. #define FLASH_BASE1_PRELIM 0xffc00000
  139. #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
  140. #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
  141. #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  142. #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  143. #define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
  144. #define CFG_JFFS2_NUM_BANKS 2 /* ! second bank contains U-Boot */
  145. #define CFG_MONITOR_BASE CFG_FLASH_BASE
  146. #define CFG_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
  147. #define CFG_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */
  148. #undef CFG_MEMTEST
  149. /*
  150. * Environment settings
  151. */
  152. #define CONFIG_ENV_OVERWRITE
  153. #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
  154. #define CFG_NVRAM_SIZE 0x800 /* NVRAM size (2kB) */
  155. #define CFG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */
  156. #define CFG_ENV_ADDR 0x0
  157. #define CFG_ENV_MAP_ADRS 0xff000000
  158. #define CFG_NV_SROM_COPY_ADDR (CFG_ENV_ADDR + CFG_ENV_SIZE)
  159. #define CFG_NVRAM_ACCESS_ROUTINE /* only byte accsess alowed */
  160. #define CFG_SROM_SIZE 0x100 /* shadow of revision info is in nvram */
  161. /*
  162. * Serial devices
  163. */
  164. #define CFG_NS16550
  165. #define CFG_NS16550_SERIAL
  166. #define CFG_NS16550_REG_SIZE 1
  167. #define CFG_NS16550_CLK 24000000
  168. #define CFG_NS16550_COM1 (CFG_UART_BASE + 0)
  169. #define CFG_NS16550_COM2 (CFG_UART_BASE + 8)
  170. /*
  171. * PCI stuff
  172. */
  173. #define CONFIG_PCI /* include pci support */
  174. #define CONFIG_PCI_PNP /* pci plug-and-play */
  175. #define CONFIG_PCI_HOST PCI_HOST_AUTO
  176. #undef CONFIG_PCI_SCAN_SHOW
  177. /*
  178. * Optional Video console (graphic: SMI LynxEM)
  179. */
  180. #define CONFIG_VIDEO
  181. #define CONFIG_CFB_CONSOLE
  182. #define VIDEO_KBD_INIT_FCT (simple_strtol (getenv("console"), NULL, 10))
  183. #define VIDEO_TSTC_FCT serial_tstc
  184. #define VIDEO_GETC_FCT serial_getc
  185. #define CONFIG_VIDEO_SMI_LYNXEM
  186. #define CONFIG_VIDEO_LOGO
  187. #define CONFIG_CONSOLE_EXTRA_INFO
  188. /*
  189. * Initial BATs
  190. */
  191. #if 1
  192. #define CFG_IBAT0L 0
  193. #define CFG_IBAT0U 0
  194. #define CFG_DBAT0L CFG_IBAT1L
  195. #define CFG_DBAT0U CFG_IBAT1U
  196. #define CFG_IBAT1L 0
  197. #define CFG_IBAT1U 0
  198. #define CFG_DBAT1L CFG_IBAT1L
  199. #define CFG_DBAT1U CFG_IBAT1U
  200. #define CFG_IBAT2L 0
  201. #define CFG_IBAT2U 0
  202. #define CFG_DBAT2L CFG_IBAT2L
  203. #define CFG_DBAT2U CFG_IBAT2U
  204. #define CFG_IBAT3L 0
  205. #define CFG_IBAT3U 0
  206. #define CFG_DBAT3L CFG_IBAT3L
  207. #define CFG_DBAT3U CFG_IBAT3U
  208. #else
  209. /* SDRAM */
  210. #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW)
  211. #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  212. #define CFG_DBAT0L CFG_IBAT1L
  213. #define CFG_DBAT0U CFG_IBAT1U
  214. /* address range for flashes */
  215. #define CFG_IBAT1L (CFG_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
  216. #define CFG_IBAT1U (CFG_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
  217. #define CFG_DBAT1L CFG_IBAT1L
  218. #define CFG_DBAT1U CFG_IBAT1U
  219. /* ISA IO space */
  220. #define CFG_IBAT2L (CFG_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
  221. #define CFG_IBAT2U (CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
  222. #define CFG_DBAT2L CFG_IBAT2L
  223. #define CFG_DBAT2U CFG_IBAT2U
  224. /* ISA memory space */
  225. #define CFG_IBAT3L (CFG_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
  226. #define CFG_IBAT3U (CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
  227. #define CFG_DBAT3L CFG_IBAT3L
  228. #define CFG_DBAT3U CFG_IBAT3U
  229. #endif
  230. /*
  231. * Speed settings are board specific
  232. */
  233. #define CFG_BUS_HZ 100000000
  234. #define CFG_CPU_CLK 400000000
  235. #define CFG_BUS_CLK CFG_BUS_HZ
  236. /*
  237. * For booting Linux, the board info and command line data
  238. * have to be in the first 8 MB of memory, since this is
  239. * the maximum mapped by the Linux kernel during initialization.
  240. */
  241. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  242. /*
  243. * Cache Configuration
  244. */
  245. #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
  246. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  247. #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  248. #endif
  249. /*
  250. * L2CR setup -- make sure this is right for your board!
  251. * look in include/mpc74xx.h for the defines used here
  252. */
  253. #define CFG_L2
  254. #if 1
  255. #define L2_INIT 0 /* cpu 750 CXe*/
  256. #else
  257. #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
  258. L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
  259. #endif
  260. #define L2_ENABLE (L2_INIT | L2CR_L2E)
  261. /*
  262. * Internal Definitions
  263. *
  264. * Boot Flags
  265. */
  266. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  267. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  268. #define CONFIG_NET_MULTI /* Multi ethernet cards support */
  269. #define CONFIG_EEPRO100
  270. #define CONFIG_EEPRO100_SROM_WRITE
  271. #endif /* __CONFIG_H */