BAB7xx.h 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452
  1. /*
  2. * (C) Copyright 2002 ELTEC Elektronik AG
  3. * Frank Gottschling <fgottschling@eltec.de>
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * board/config.h - configuration options, board specific
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. #include <asm/processor.h>
  29. #undef DEBUG
  30. #define GTREGREAD(x) 0xffffffff /* needed for debug */
  31. /*
  32. * High Level Configuration Options
  33. * (easy to change)
  34. */
  35. /* these hardware addresses are pretty bogus, please change them to
  36. suit your needs */
  37. /* first ethernet */
  38. #define CONFIG_ETHADDR 00:00:5b:ee:de:ad
  39. #define CONFIG_IPADDR 192.168.0.105
  40. #define CONFIG_SERVERIP 192.168.0.100
  41. #define CONFIG_BAB7xx 1 /* this is an BAB740/BAB750 board */
  42. #define CONFIG_BAUDRATE 9600 /* console baudrate */
  43. #undef CONFIG_WATCHDOG
  44. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  45. #define CONFIG_ZERO_BOOTDELAY_CHECK
  46. #undef CONFIG_BOOTARGS
  47. #define CONFIG_BOOTCOMMAND \
  48. "bootp 1000000; " \
  49. "setenv bootargs root=ramfs console=ttyS00,9600 " \
  50. "ip=$(ipaddr):$(serverip):$(rootpath):$(gatewayip):" \
  51. "$(netmask):$(hostname):eth0:none; " \
  52. "bootm"
  53. #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
  54. #define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
  55. #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
  56. #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 |\
  57. CFG_CMD_SCSI | CFG_CMD_IDE | CFG_CMD_DATE |\
  58. CFG_CMD_FDC | CFG_CMD_ELF)
  59. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  60. #include <cmd_confdefs.h>
  61. /*
  62. * Miscellaneous configurable options
  63. */
  64. #define CFG_LONGHELP /* undef to save memory */
  65. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  66. /*
  67. * choose between COM1 and COM2 as serial console
  68. */
  69. #define CONFIG_CONS_INDEX 1
  70. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  71. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  72. #else
  73. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  74. #endif
  75. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  76. #define CFG_MAXARGS 16 /* max number of command args */
  77. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  78. #define CFG_MEMTEST_START 0x00000000 /* memtest works on */
  79. #define CFG_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */
  80. #define CFG_LOAD_ADDR 0x1000000 /* default load address */
  81. #define CFG_HZ 1000 /* dec. freq: 1 ms ticks */
  82. #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
  83. /*
  84. * Low Level Configuration Settings
  85. * (address mappings, register initial values, etc.)
  86. * You should know what you are doing if you make changes here.
  87. */
  88. #define CFG_BOARD_ASM_INIT
  89. #define CONFIG_MISC_INIT_R
  90. /*
  91. * Choose the address mapping scheme for the MPC106 mem controller.
  92. * Default is mapping B (CHRP), set this define to choose mapping A (PReP).
  93. */
  94. #define CFG_ADDRESS_MAP_A
  95. #ifdef CFG_ADDRESS_MAP_A
  96. #define CFG_PCI_MEMORY_BUS 0x80000000
  97. #define CFG_PCI_MEMORY_PHYS 0x00000000
  98. #define CFG_PCI_MEMORY_SIZE 0x80000000
  99. #define CFG_PCI_MEM_BUS 0x00000000
  100. #define CFG_PCI_MEM_PHYS 0xc0000000
  101. #define CFG_PCI_MEM_SIZE 0x3f000000
  102. #define CFG_ISA_MEM_BUS 0
  103. #define CFG_ISA_MEM_PHYS 0
  104. #define CFG_ISA_MEM_SIZE 0
  105. #define CFG_PCI_IO_BUS 0x1000
  106. #define CFG_PCI_IO_PHYS 0x81000000
  107. #define CFG_PCI_IO_SIZE 0x01000000-CFG_PCI_IO_BUS
  108. #define CFG_ISA_IO_BUS 0x00000000
  109. #define CFG_ISA_IO_PHYS 0x80000000
  110. #define CFG_ISA_IO_SIZE 0x00800000
  111. #else
  112. #define CFG_PCI_MEMORY_BUS 0x00000000
  113. #define CFG_PCI_MEMORY_PHYS 0x00000000
  114. #define CFG_PCI_MEMORY_SIZE 0x40000000
  115. #define CFG_PCI_MEM_BUS 0x80000000
  116. #define CFG_PCI_MEM_PHYS 0x80000000
  117. #define CFG_PCI_MEM_SIZE 0x7d000000
  118. #define CFG_ISA_MEM_BUS 0x00000000
  119. #define CFG_ISA_MEM_PHYS 0xfd000000
  120. #define CFG_ISA_MEM_SIZE 0x01000000
  121. #define CFG_PCI_IO_BUS 0x00800000
  122. #define CFG_PCI_IO_PHYS 0xfe800000
  123. #define CFG_PCI_IO_SIZE 0x00400000
  124. #define CFG_ISA_IO_BUS 0x00000000
  125. #define CFG_ISA_IO_PHYS 0xfe000000
  126. #define CFG_ISA_IO_SIZE 0x00800000
  127. #endif /*CFG_ADDRESS_MAP_A */
  128. #define CFG_60X_PCI_MEM_OFFSET 0x00000000
  129. /* driver defines FDC,IDE,... */
  130. #define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
  131. #define CFG_ISA_IO CFG_ISA_IO_PHYS
  132. #define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS
  133. /*
  134. * Start addresses for the final memory configuration
  135. * (Set up by the startup code)
  136. * Please note that CFG_SDRAM_BASE _must_ start at 0
  137. */
  138. #define CFG_SDRAM_BASE 0x00000000
  139. #define CFG_FLASH_BASE 0xfff00000
  140. /*
  141. * Definitions for initial stack pointer and data area
  142. */
  143. #define CFG_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */
  144. #define CFG_INIT_RAM_END 0x4000
  145. #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for init data */
  146. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  147. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  148. /*
  149. * Flash mapping/organization on the MPC10x.
  150. */
  151. #define FLASH_BASE0_PRELIM 0xff800000
  152. #define FLASH_BASE1_PRELIM 0xffc00000
  153. #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
  154. #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
  155. #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  156. #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  157. #define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
  158. #define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
  159. #define CFG_MONITOR_BASE CFG_FLASH_BASE
  160. #define CFG_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
  161. #define CFG_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */
  162. #undef CFG_MEMTEST
  163. /*
  164. * Environment settings
  165. */
  166. #define CONFIG_ENV_OVERWRITE
  167. #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
  168. #define CFG_NVRAM_SIZE 0x1ff0 /* NVRAM size (8kB), we must protect the clock data (16 bytes) */
  169. #define CFG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */
  170. /*
  171. * We store the environment and an image of revision eeprom in the upper part of the NVRAM. Thus,
  172. * user applications can use the remaining space for other purposes.
  173. */
  174. #define CFG_ENV_ADDR (CFG_NVRAM_SIZE +0x10 -0x800)
  175. #define CFG_NV_SROM_COPY_ADDR (CFG_NVRAM_SIZE +0x10 -0x400)
  176. #define CFG_NVRAM_ACCESS_ROUTINE /* This board needs a special routine to access the NVRAM */
  177. #define CFG_SROM_SIZE 0x100 /* shadow of revision info is in nvram */
  178. /*
  179. * Serial devices
  180. */
  181. #define CFG_NS16550
  182. #define CFG_NS16550_SERIAL
  183. #define CFG_NS16550_REG_SIZE 1
  184. #define CFG_NS16550_CLK 1843200
  185. #define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE)
  186. #define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE)
  187. /*
  188. * PCI stuff
  189. */
  190. #define CONFIG_PCI /* include pci support */
  191. #define CONFIG_PCI_PNP /* pci plug-and-play */
  192. #define CONFIG_PCI_HOST PCI_HOST_AUTO
  193. #undef CONFIG_PCI_SCAN_SHOW
  194. /*
  195. * Video console (graphic: SMI LynxEM, keyboard: i8042)
  196. */
  197. #define CONFIG_VIDEO
  198. #define CONFIG_CFB_CONSOLE
  199. #define CONFIG_VIDEO_SMI_LYNXEM
  200. #define CONFIG_I8042_KBD
  201. #define CONFIG_VIDEO_LOGO
  202. #define CONFIG_CONSOLE_TIME
  203. #define CONFIG_CONSOLE_EXTRA_INFO
  204. #define CONFIG_CONSOLE_CURSOR
  205. #define CFG_CONSOLE_BLINK_COUNT 30000 /* approx. 2 HZ */
  206. /*
  207. * IDE/SCSI globals
  208. */
  209. #ifndef __ASSEMBLY__
  210. extern unsigned int eltec_board;
  211. extern unsigned int ata_reset_time;
  212. extern unsigned int scsi_reset_time;
  213. extern unsigned short scsi_dev_id;
  214. extern unsigned int scsi_max_scsi_id;
  215. extern unsigned char scsi_sym53c8xx_ccf;
  216. #endif
  217. /*
  218. * ATAPI Support (experimental)
  219. */
  220. #define CONFIG_ATAPI
  221. #define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */
  222. #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
  223. #define CFG_ATA_BASE_ADDR CFG_60X_PCI_IO_OFFSET /* base address */
  224. #define CFG_ATA_IDE0_OFFSET 0x1F0 /* default ide0 offste */
  225. #define CFG_ATA_IDE1_OFFSET 0x170 /* default ide1 offset */
  226. #define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
  227. #define CFG_ATA_REG_OFFSET 0 /* reg offset */
  228. #define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
  229. #define ATA_RESET_TIME (ata_reset_time)
  230. #undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
  231. #undef CONFIG_IDE_LED /* no led for ide supported */
  232. /*
  233. * SCSI support (experimental) only SYM53C8xx supported
  234. */
  235. #define CONFIG_SCSI_SYM53C8XX
  236. #define CONFIG_SCSI_DEV_ID (scsi_dev_id) /* 875 or 860 */
  237. #define CFG_SCSI_SYM53C8XX_CCF (scsi_sym53c8xx_ccf) /* value for none 40 mhz clocks */
  238. #define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */
  239. #define CFG_SCSI_MAX_SCSI_ID (scsi_max_scsi_id) /* max SCSI ID (0-6) */
  240. #define CFG_SCSI_MAX_DEVICE (15 * CFG_SCSI_MAX_LUN) /* max. Target devices */
  241. #define CFG_SCSI_SPIN_UP_TIME (scsi_reset_time)
  242. /*
  243. * Partion suppport
  244. */
  245. #define CONFIG_DOS_PARTITION
  246. #define CONFIG_MAC_PARTITION
  247. #define CONFIG_ISO_PARTITION
  248. /*
  249. * Winbond Configuration
  250. */
  251. #define CFG_WINBOND_83C553 1 /* has a winbond bridge */
  252. #define CFG_USE_WINBOND_IDE 0 /* use winbond 83c553 internal ide */
  253. #define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /* pci-isa bridge config addr */
  254. #define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /* ide config addr */
  255. /*
  256. * NS87308 Configuration
  257. */
  258. #define CFG_NS87308 /* Nat Semi super-io cntr on ISA bus */
  259. #define CFG_NS87308_BADDR_10 1
  260. #define CFG_NS87308_DEVS (CFG_NS87308_UART1 | \
  261. CFG_NS87308_UART2 | \
  262. CFG_NS87308_KBC1 | \
  263. CFG_NS87308_MOUSE | \
  264. CFG_NS87308_FDC | \
  265. CFG_NS87308_RARP | \
  266. CFG_NS87308_GPIO | \
  267. CFG_NS87308_POWRMAN | \
  268. CFG_NS87308_RTC_APC )
  269. #define CFG_NS87308_PS2MOD
  270. #define CFG_NS87308_GPIO_BASE 0x0220
  271. #define CFG_NS87308_PWMAN_BASE 0x0460
  272. #define CFG_NS87308_PMC2 0x00 /* SuperI/O clock source is 24MHz via X1 */
  273. /*
  274. * set up the NVRAM access registers
  275. * NVRAM's controlled by the configurable CS line from the 87308
  276. */
  277. #define CFG_NS87308_CS0_BASE 0x0076
  278. #define CFG_NS87308_CS0_CONF 0x40
  279. #define CFG_NS87308_CS1_BASE 0x0070
  280. #define CFG_NS87308_CS1_CONF 0x1C
  281. #define CFG_NS87308_CS2_BASE 0x0071
  282. #define CFG_NS87308_CS2_CONF 0x1C
  283. #define CONFIG_RTC_MK48T59
  284. /*
  285. * Initial BATs
  286. */
  287. #if 1
  288. #define CFG_IBAT0L 0
  289. #define CFG_IBAT0U 0
  290. #define CFG_DBAT0L CFG_IBAT1L
  291. #define CFG_DBAT0U CFG_IBAT1U
  292. #define CFG_IBAT1L 0
  293. #define CFG_IBAT1U 0
  294. #define CFG_DBAT1L CFG_IBAT1L
  295. #define CFG_DBAT1U CFG_IBAT1U
  296. #define CFG_IBAT2L 0
  297. #define CFG_IBAT2U 0
  298. #define CFG_DBAT2L CFG_IBAT2L
  299. #define CFG_DBAT2U CFG_IBAT2U
  300. #define CFG_IBAT3L 0
  301. #define CFG_IBAT3U 0
  302. #define CFG_DBAT3L CFG_IBAT3L
  303. #define CFG_DBAT3U CFG_IBAT3U
  304. #else
  305. /* SDRAM */
  306. #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW)
  307. #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  308. #define CFG_DBAT0L CFG_IBAT1L
  309. #define CFG_DBAT0U CFG_IBAT1U
  310. /* address range for flashes */
  311. #define CFG_IBAT1L (CFG_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
  312. #define CFG_IBAT1U (CFG_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
  313. #define CFG_DBAT1L CFG_IBAT1L
  314. #define CFG_DBAT1U CFG_IBAT1U
  315. /* ISA IO space */
  316. #define CFG_IBAT2L (CFG_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
  317. #define CFG_IBAT2U (CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
  318. #define CFG_DBAT2L CFG_IBAT2L
  319. #define CFG_DBAT2U CFG_IBAT2U
  320. /* ISA memory space */
  321. #define CFG_IBAT3L (CFG_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
  322. #define CFG_IBAT3U (CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
  323. #define CFG_DBAT3L CFG_IBAT3L
  324. #define CFG_DBAT3U CFG_IBAT3U
  325. #endif
  326. /*
  327. * Speed settings are board specific
  328. */
  329. #ifndef __ASSEMBLY__
  330. extern unsigned long bab7xx_get_bus_freq (void);
  331. extern unsigned long bab7xx_get_gclk_freq (void);
  332. #endif
  333. #define CFG_BUS_HZ bab7xx_get_bus_freq()
  334. #define CFG_BUS_CLK CFG_BUS_HZ
  335. #define CFG_CPU_CLK bab7xx_get_gclk_freq()
  336. /*
  337. * For booting Linux, the board info and command line data
  338. * have to be in the first 8 MB of memory, since this is
  339. * the maximum mapped by the Linux kernel during initialization.
  340. */
  341. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  342. /*
  343. * Cache Configuration
  344. */
  345. #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
  346. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  347. #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  348. #endif
  349. /*
  350. * L2 Cache Configuration is board specific for BAB740/BAB750
  351. * Init values read from revision srom.
  352. */
  353. #undef CFG_L2
  354. #define L2_INIT (L2CR_L2SIZ_HM | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
  355. L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
  356. #define L2_ENABLE (L2_INIT | L2CR_L2E)
  357. #define CFG_L2_BAB7xx
  358. /*
  359. * Internal Definitions
  360. *
  361. * Boot Flags
  362. */
  363. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  364. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  365. #define CONFIG_NET_MULTI /* Multi ethernet cards support */
  366. #define CONFIG_TULIP
  367. #define CONFIG_TULIP_SELECT_MEDIA
  368. #endif /* __CONFIG_H */