hymod.h 9.5 KB

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  1. #ifndef _ASM_HYMOD_H_
  2. #define _ASM_HYMOD_H_
  3. #include <linux/config.h>
  4. #ifdef CONFIG_8260
  5. #include <asm/iopin_8260.h>
  6. #endif
  7. /*
  8. * hymod configuration data - passed by boot code via the board information
  9. * structure (only U-Boot has support for this at the moment)
  10. *
  11. * there are three types of data passed up from the boot monitor. the first
  12. * (type hymod_eeprom_t) is the eeprom data that was read off both the main
  13. * (or mother) board and the mezzanine board (if any). this data defines how
  14. * many Xilinx fpgas are on each board, and their types (among other things).
  15. * the second type of data (type xlx_mmap_t, one per Xilinx fpga) defines where
  16. * in the physical address space the various Xilinx fpga access regions have
  17. * been mapped by the boot rom. the third type of data (type xlx_iopins_t,
  18. * one per Xilinx fpga) defines which io port pins are connected to the various
  19. * signals required to program a Xilinx fpga.
  20. *
  21. * A ram/flash "bank" refers to memory controlled by the same chip select.
  22. *
  23. * the eeprom contents are defined as in technical note #2 - basically,
  24. * a header, zero or more records in no particular order, and a 32 bit crc
  25. * a record is 1 or more type bytes, a length byte and "length" bytes.
  26. */
  27. #define HYMOD_EEPROM_ID 0xAA /* eeprom id byte */
  28. #define HYMOD_EEPROM_VER 1 /* eeprom contents version */
  29. #define HYMOD_EEPROM_SIZE 256 /* number of bytes in the eeprom */
  30. /* eeprom header */
  31. typedef
  32. struct {
  33. unsigned char id; /* eeprom id byte */
  34. unsigned char ver; /* eeprom contents version number */
  35. unsigned long len; /* total # of bytes btw hdr and crc */
  36. }
  37. hymod_eehdr_t;
  38. /* maximum number of bytes available for eeprom data records */
  39. #define HYMOD_EEPROM_MAXLEN (HYMOD_EEPROM_SIZE \
  40. - sizeof (hymod_eehdr_t) \
  41. - sizeof (unsigned long))
  42. /* eeprom data record */
  43. typedef
  44. union {
  45. struct {
  46. unsigned char topbit:1;
  47. unsigned char type:7;
  48. unsigned char len;
  49. unsigned char data[1]; /* variable length */
  50. } small;
  51. struct {
  52. unsigned short topbit:1;
  53. unsigned short nxtbit:1;
  54. unsigned short type:14;
  55. unsigned short len;
  56. unsigned char data[1]; /* variable length */
  57. } medium;
  58. struct {
  59. unsigned long topbit:1;
  60. unsigned long nxtbit:1;
  61. unsigned long type:30;
  62. unsigned long len;
  63. unsigned char data[1]; /* variable length */
  64. } large;
  65. }
  66. hymod_eerec_t;
  67. #define HYMOD_EEOFF_MAIN 0x00 /* i2c addr offset for main eeprom */
  68. #define HYMOD_EEOFF_MEZZ 0x04 /* i2c addr offset for mezz eepomr */
  69. /* eeprom record types */
  70. #define HYMOD_EEREC_SERNO 1 /* serial number */
  71. #define HYMOD_EEREC_DATE 2 /* date */
  72. #define HYMOD_EEREC_BATCH 3 /* batch id */
  73. #define HYMOD_EEREC_TYPE 4 /* board type */
  74. #define HYMOD_EEREC_REV 5 /* revision number */
  75. #define HYMOD_EEREC_SDRAM 6 /* sdram sizes */
  76. #define HYMOD_EEREC_FLASH 7 /* flash sizes */
  77. #define HYMOD_EEREC_ZBT 8 /* zbt ram sizes */
  78. #define HYMOD_EEREC_XLXTYP 9 /* Xilinx fpga types */
  79. #define HYMOD_EEREC_XLXSPD 10 /* Xilinx fpga speeds */
  80. #define HYMOD_EEREC_XLXTMP 11 /* Xilinx fpga temperatures */
  81. #define HYMOD_EEREC_XLXGRD 12 /* Xilinx fpga grades */
  82. #define HYMOD_EEREC_CPUTYP 13 /* Motorola CPU type */
  83. #define HYMOD_EEREC_CPUSPD 14 /* CPU speed */
  84. #define HYMOD_EEREC_BUSSPD 15 /* bus speed */
  85. #define HYMOD_EEREC_CPMSPD 16 /* CPM speed */
  86. #define HYMOD_EEREC_HSTYPE 17 /* high-speed serial chip type */
  87. #define HYMOD_EEREC_HSCHIN 18 /* high-speed serial input channels */
  88. #define HYMOD_EEREC_HSCHOUT 19 /* high-speed serial output channels */
  89. /* some dimensions */
  90. #define HYMOD_MAX_BATCH 32 /* max no. of bytes in batch id */
  91. #define HYMOD_MAX_SDRAM 4 /* max sdram "banks" on any board */
  92. #define HYMOD_MAX_FLASH 4 /* max flash "banks" on any board */
  93. #define HYMOD_MAX_ZBT 16 /* max ZBT rams on any board */
  94. #define HYMOD_MAX_XLX 4 /* max Xilinx fpgas on any board */
  95. #define HYMOD_MAX_BYTES 16 /* enough to store any bytes array */
  96. /* board types */
  97. #define HYMOD_BDTYPE_NONE 0 /* information not present */
  98. #define HYMOD_BDTYPE_IO 1 /* I/O main board */
  99. #define HYMOD_BDTYPE_CLP 2 /* CLP main board */
  100. #define HYMOD_BDTYPE_DSP 3 /* DSP main board */
  101. #define HYMOD_BDTYPE_INPUT 4 /* video input mezzanine board */
  102. #define HYMOD_BDTYPE_ALTINPUT 5 /* video input mezzanine board */
  103. #define HYMOD_BDTYPE_DISPLAY 6 /* video display mezzanine board */
  104. #define HYMOD_BDTYPE_MAX 7 /* first invalid value */
  105. /* Xilinx fpga types */
  106. #define HYMOD_XTYP_NONE 0 /* information not present */
  107. #define HYMOD_XTYP_XCV300E 1 /* Xilinx Virtex 300 */
  108. #define HYMOD_XTYP_XCV400E 2 /* Xilinx Virtex 400 */
  109. #define HYMOD_XTYP_XCV600E 3 /* Xilinx Virtex 600 */
  110. #define HYMOD_XTYP_MAX 4 /* first invalid value */
  111. /* Xilinx fpga speeds */
  112. #define HYMOD_XSPD_NONE 0 /* information not present */
  113. #define HYMOD_XSPD_SIX 1
  114. #define HYMOD_XSPD_SEVEN 2
  115. #define HYMOD_XSPD_EIGHT 3
  116. #define HYMOD_XSPD_MAX 4 /* first invalid value */
  117. /* Xilinx fpga temperatures */
  118. #define HYMOD_XTMP_NONE 0 /* information not present */
  119. #define HYMOD_XTMP_COM 1
  120. #define HYMOD_XTMP_IND 2
  121. #define HYMOD_XTMP_MAX 3 /* first invalid value */
  122. /* Xilinx fpga grades */
  123. #define HYMOD_XTMP_NONE 0 /* information not present */
  124. #define HYMOD_XTMP_NORMAL 1
  125. #define HYMOD_XTMP_ENGSAMP 2
  126. #define HYMOD_XTMP_MAX 3 /* first invalid value */
  127. /* CPU types */
  128. #define HYMOD_CPUTYPE_NONE 0 /* information not present */
  129. #define HYMOD_CPUTYPE_MPC8260 1 /* Motorola MPC8260 embedded powerpc */
  130. #define HYMOD_CPUTYPE_MAX 2 /* first invalid value */
  131. /* CPU/BUS/CPM clock speeds */
  132. #define HYMOD_CLKSPD_NONE 0 /* information not present */
  133. #define HYMOD_CLKSPD_33MHZ 1
  134. #define HYMOD_CLKSPD_66MHZ 2
  135. #define HYMOD_CLKSPD_100MHZ 3
  136. #define HYMOD_CLKSPD_133MHZ 4
  137. #define HYMOD_CLKSPD_166MHZ 5
  138. #define HYMOD_CLKSPD_200MHZ 6
  139. #define HYMOD_CLKSPD_MAX 7 /* first invalid value */
  140. /* high speed serial chip types */
  141. #define HYMOD_HSSTYPE_NONE 0 /* information not present */
  142. #define HYMOD_HSSTYPE_AMCC52064 1
  143. #define HYMOD_HSSTYPE_MAX 2 /* first invalid value */
  144. /* a date (yyyy-mm-dd) */
  145. typedef
  146. struct {
  147. unsigned short year;
  148. unsigned char month;
  149. unsigned char day;
  150. }
  151. hymod_date_t;
  152. /* describes a Xilinx fpga */
  153. typedef
  154. struct {
  155. unsigned char type; /* chip type */
  156. unsigned char speed; /* chip speed rating */
  157. unsigned char temp; /* chip temperature rating */
  158. unsigned char grade; /* chip grade */
  159. }
  160. hymod_xlx_t;
  161. /* describes a Motorola embedded processor */
  162. typedef
  163. struct {
  164. unsigned char type; /* CPU type */
  165. unsigned char cpuspd; /* speed of the PowerPC core */
  166. unsigned char busspd; /* speed of the system and 60x bus */
  167. unsigned char cpmspd; /* speed of the CPM co-processor */
  168. }
  169. hymod_mpc_t;
  170. /* info about high-speed (1Gbit) serial interface */
  171. typedef
  172. struct {
  173. unsigned char type; /* high-speed serial chip type */
  174. unsigned char nchin; /* number of input channels mounted */
  175. unsigned char nchout; /* number of output channels mounted */
  176. }
  177. hymod_hss_t;
  178. /*
  179. * this defines the contents of the serial eeprom that exists on every
  180. * hymod board, including mezzanine boards (the serial eeprom will be
  181. * faked for early development boards that don't have one)
  182. */
  183. typedef
  184. struct {
  185. unsigned char ver; /* eeprom contents version */
  186. unsigned char bdtype; /* board type */
  187. unsigned char bdrev; /* board revision */
  188. unsigned char batchlen; /* length of batch string below */
  189. unsigned long serno; /* serial number */
  190. hymod_date_t date; /* manufacture date */
  191. unsigned char batch[32]; /* manufacturer specific batch id */
  192. unsigned char nsdram; /* # of ram "banks" */
  193. unsigned char nflash; /* # of flash "banks" */
  194. unsigned char nzbt; /* # of ZBT rams */
  195. unsigned char nxlx; /* # of Xilinx fpgas */
  196. unsigned char sdramsz[HYMOD_MAX_SDRAM]; /* log2 of sdram size */
  197. unsigned char flashsz[HYMOD_MAX_FLASH]; /* log2 of flash size */
  198. unsigned char zbtsz[HYMOD_MAX_ZBT]; /* log2 of ZBT ram size */
  199. hymod_xlx_t xlx[HYMOD_MAX_XLX]; /* Xilinx fpga info */
  200. hymod_mpc_t mpc; /* Motorola MPC CPU info */
  201. hymod_hss_t hss; /* high-speed serial info */
  202. }
  203. hymod_eeprom_t;
  204. /*
  205. * this defines a region in the processor's physical address space
  206. */
  207. typedef
  208. struct {
  209. unsigned long exists:1; /* 1 if the region exists, 0 if not */
  210. unsigned long size:31; /* size in bytes */
  211. unsigned long base; /* base address */
  212. }
  213. xlx_prgn_t;
  214. /*
  215. * this defines where the various Xilinx fpga access regions are mapped
  216. * into the physical address space of the processor
  217. */
  218. typedef
  219. struct {
  220. xlx_prgn_t prog; /* program access region */
  221. xlx_prgn_t reg; /* register access region */
  222. xlx_prgn_t port; /* port access region */
  223. }
  224. xlx_mmap_t;
  225. /*
  226. * this defines which 8260 i/o port pins are connected to the various
  227. * signals required for programming a Xilinx fpga
  228. */
  229. typedef
  230. struct {
  231. iopin_t prog_pin; /* assert for >= 300ns to program */
  232. iopin_t init_pin; /* goes high when fpga is cleared */
  233. iopin_t done_pin; /* goes high when program is done */
  234. iopin_t enable_pin; /* some fpgas need enabling */
  235. }
  236. xlx_iopins_t;
  237. /* all info about one hymod board */
  238. typedef
  239. struct {
  240. unsigned char eeprom_valid:1;
  241. hymod_eeprom_t eeprom;
  242. xlx_mmap_t mmap[HYMOD_MAX_XLX];
  243. xlx_iopins_t iopins[HYMOD_MAX_XLX];
  244. }
  245. hymod_board_t;
  246. /*
  247. * this defines the configuration information of a hymod board-set
  248. * (main board + possible mezzanine board). In future, there may be
  249. * more than one mezzanine board (stackable?) - if so, add a "mezz2"
  250. * field, and so on... or make mezz an array?
  251. */
  252. typedef
  253. struct {
  254. hymod_board_t main; /* main board info */
  255. hymod_board_t mezz; /* mezzanine board info */
  256. unsigned long crc; /* ensures kernel and boot prom agree */
  257. }
  258. hymod_conf_t;
  259. #endif /* _ASM_HYMOD_H_ */