spartan2.c 13 KB

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  1. /*
  2. * (C) Copyright 2002
  3. * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. *
  23. */
  24. #include <common.h> /* core U-Boot definitions */
  25. #include <spartan2.h> /* Spartan-II device family */
  26. #if (CONFIG_FPGA & (CFG_XILINX | CFG_SPARTAN2))
  27. /* Define FPGA_DEBUG to get debug printf's */
  28. #ifdef FPGA_DEBUG
  29. #define PRINTF(fmt,args...) printf (fmt ,##args)
  30. #else
  31. #define PRINTF(fmt,args...)
  32. #endif
  33. #undef CFG_FPGA_CHECK_BUSY
  34. #define CFG_FPGA_PROG_FEEDBACK
  35. /* Note: The assumption is that we cannot possibly run fast enough to
  36. * overrun the device (the Slave Parallel mode can free run at 50MHz).
  37. * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
  38. * the board config file to slow things down.
  39. */
  40. #ifndef CONFIG_FPGA_DELAY
  41. #define CONFIG_FPGA_DELAY()
  42. #endif
  43. #ifndef CFG_FPGA_WAIT
  44. #define CFG_FPGA_WAIT 10
  45. #endif
  46. static int Spartan2_sp_load( Xilinx_desc *desc, void *buf, size_t bsize );
  47. static int Spartan2_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize );
  48. /* static int Spartan2_sp_info( Xilinx_desc *desc ); */
  49. static int Spartan2_sp_reloc( Xilinx_desc *desc, ulong reloc_offset );
  50. static int Spartan2_ss_load( Xilinx_desc *desc, void *buf, size_t bsize );
  51. static int Spartan2_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize );
  52. /* static int Spartan2_ss_info( Xilinx_desc *desc ); */
  53. static int Spartan2_ss_reloc( Xilinx_desc *desc, ulong reloc_offset );
  54. /* ------------------------------------------------------------------------- */
  55. /* Spartan-II Generic Implementation */
  56. int Spartan2_load (Xilinx_desc * desc, void *buf, size_t bsize)
  57. {
  58. int ret_val = FPGA_FAIL;
  59. switch (desc->iface) {
  60. case slave_serial:
  61. PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
  62. ret_val = Spartan2_ss_load (desc, buf, bsize);
  63. break;
  64. case slave_parallel:
  65. PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
  66. ret_val = Spartan2_sp_load (desc, buf, bsize);
  67. break;
  68. default:
  69. printf ("%s: Unsupported interface type, %d\n",
  70. __FUNCTION__, desc->iface);
  71. }
  72. return ret_val;
  73. }
  74. int Spartan2_dump (Xilinx_desc * desc, void *buf, size_t bsize)
  75. {
  76. int ret_val = FPGA_FAIL;
  77. switch (desc->iface) {
  78. case slave_serial:
  79. PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
  80. ret_val = Spartan2_ss_dump (desc, buf, bsize);
  81. break;
  82. case slave_parallel:
  83. PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
  84. ret_val = Spartan2_sp_dump (desc, buf, bsize);
  85. break;
  86. default:
  87. printf ("%s: Unsupported interface type, %d\n",
  88. __FUNCTION__, desc->iface);
  89. }
  90. return ret_val;
  91. }
  92. int Spartan2_info( Xilinx_desc *desc )
  93. {
  94. return FPGA_SUCCESS;
  95. }
  96. int Spartan2_reloc (Xilinx_desc * desc, ulong reloc_offset)
  97. {
  98. int ret_val = FPGA_FAIL; /* assume a failure */
  99. if (desc->family != Xilinx_Spartan2) {
  100. printf ("%s: Unsupported family type, %d\n",
  101. __FUNCTION__, desc->family);
  102. return FPGA_FAIL;
  103. } else
  104. switch (desc->iface) {
  105. case slave_serial:
  106. ret_val = Spartan2_ss_reloc (desc, reloc_offset);
  107. break;
  108. case slave_parallel:
  109. ret_val = Spartan2_sp_reloc (desc, reloc_offset);
  110. break;
  111. default:
  112. printf ("%s: Unsupported interface type, %d\n",
  113. __FUNCTION__, desc->iface);
  114. }
  115. return ret_val;
  116. }
  117. /* ------------------------------------------------------------------------- */
  118. /* Spartan-II Slave Parallel Generic Implementation */
  119. static int Spartan2_sp_load (Xilinx_desc * desc, void *buf, size_t bsize)
  120. {
  121. int ret_val = FPGA_FAIL; /* assume the worst */
  122. Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns;
  123. PRINTF ("%s: start with interface functions @ 0x%p\n",
  124. __FUNCTION__, fn);
  125. if (fn) {
  126. size_t bytecount = 0;
  127. unsigned char *data = (unsigned char *) buf;
  128. int cookie = desc->cookie; /* make a local copy */
  129. unsigned long ts; /* timestamp */
  130. PRINTF ("%s: Function Table:\n"
  131. "ptr:\t0x%p\n"
  132. "struct: 0x%p\n"
  133. "pre: 0x%p\n"
  134. "pgm:\t0x%p\n"
  135. "init:\t0x%p\n"
  136. "err:\t0x%p\n"
  137. "clk:\t0x%p\n"
  138. "cs:\t0x%p\n"
  139. "wr:\t0x%p\n"
  140. "read data:\t0x%p\n"
  141. "write data:\t0x%p\n"
  142. "busy:\t0x%p\n"
  143. "abort:\t0x%p\n",
  144. "post:\t0x%p\n\n",
  145. __FUNCTION__, &fn, fn, fn->pre, fn->pgm, fn->init, fn->err,
  146. fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy,
  147. fn->abort, fn->post);
  148. /*
  149. * This code is designed to emulate the "Express Style"
  150. * Continuous Data Loading in Slave Parallel Mode for
  151. * the Spartan-II Family.
  152. */
  153. #ifdef CFG_FPGA_PROG_FEEDBACK
  154. printf ("Loading FPGA Device %d...\n", cookie);
  155. #endif
  156. /*
  157. * Run the pre configuration function if there is one.
  158. */
  159. if (*fn->pre) {
  160. (*fn->pre) (cookie);
  161. }
  162. /* Establish the initial state */
  163. (*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */
  164. /* Get ready for the burn */
  165. CONFIG_FPGA_DELAY ();
  166. (*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */
  167. ts = get_timer (0); /* get current time */
  168. /* Now wait for INIT and BUSY to go high */
  169. do {
  170. CONFIG_FPGA_DELAY ();
  171. if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
  172. puts ("** Timeout waiting for INIT to clear.\n");
  173. (*fn->abort) (cookie); /* abort the burn */
  174. return FPGA_FAIL;
  175. }
  176. } while ((*fn->init) (cookie) && (*fn->busy) (cookie));
  177. (*fn->wr) (TRUE, TRUE, cookie); /* Assert write, commit */
  178. (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
  179. (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
  180. /* Load the data */
  181. while (bytecount < bsize) {
  182. /* XXX - do we check for an Ctrl-C press in here ??? */
  183. /* XXX - Check the error bit? */
  184. (*fn->wdata) (data[bytecount++], TRUE, cookie); /* write the data */
  185. CONFIG_FPGA_DELAY ();
  186. (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
  187. CONFIG_FPGA_DELAY ();
  188. (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
  189. #ifdef CFG_FPGA_CHECK_BUSY
  190. ts = get_timer (0); /* get current time */
  191. while ((*fn->busy) (cookie)) {
  192. /* XXX - we should have a check in here somewhere to
  193. * make sure we aren't busy forever... */
  194. CONFIG_FPGA_DELAY ();
  195. (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
  196. CONFIG_FPGA_DELAY ();
  197. (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
  198. if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
  199. puts ("** Timeout waiting for BUSY to clear.\n");
  200. (*fn->abort) (cookie); /* abort the burn */
  201. return FPGA_FAIL;
  202. }
  203. }
  204. #endif
  205. #ifdef CFG_FPGA_PROG_FEEDBACK
  206. if (bytecount % (bsize / 40) == 0)
  207. putc ('.'); /* let them know we are alive */
  208. #endif
  209. }
  210. CONFIG_FPGA_DELAY ();
  211. (*fn->cs) (FALSE, TRUE, cookie); /* Deassert the chip select */
  212. (*fn->wr) (FALSE, TRUE, cookie); /* Deassert the write pin */
  213. #ifdef CFG_FPGA_PROG_FEEDBACK
  214. putc ('\n'); /* terminate the dotted line */
  215. #endif
  216. /* now check for done signal */
  217. ts = get_timer (0); /* get current time */
  218. ret_val = FPGA_SUCCESS;
  219. while ((*fn->done) (cookie) == FPGA_FAIL) {
  220. /* XXX - we should have a check in here somewhere to
  221. * make sure we aren't busy forever... */
  222. CONFIG_FPGA_DELAY ();
  223. (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
  224. CONFIG_FPGA_DELAY ();
  225. (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
  226. if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
  227. puts ("** Timeout waiting for DONE to clear.\n");
  228. (*fn->abort) (cookie); /* abort the burn */
  229. ret_val = FPGA_FAIL;
  230. break;
  231. }
  232. }
  233. if (ret_val == FPGA_SUCCESS) {
  234. #ifdef CFG_FPGA_PROG_FEEDBACK
  235. puts ("Done.\n");
  236. #endif
  237. }
  238. /*
  239. * Run the post configuration function if there is one.
  240. */
  241. if (*fn->post) {
  242. (*fn->post) (cookie);
  243. }
  244. else {
  245. #ifdef CFG_FPGA_PROG_FEEDBACK
  246. puts ("Fail.\n");
  247. #endif
  248. }
  249. } else {
  250. printf ("%s: NULL Interface function table!\n", __FUNCTION__);
  251. }
  252. return ret_val;
  253. }
  254. static int Spartan2_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize)
  255. {
  256. int ret_val = FPGA_FAIL; /* assume the worst */
  257. Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns;
  258. if (fn) {
  259. unsigned char *data = (unsigned char *) buf;
  260. size_t bytecount = 0;
  261. int cookie = desc->cookie; /* make a local copy */
  262. printf ("Starting Dump of FPGA Device %d...\n", cookie);
  263. (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
  264. (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
  265. /* dump the data */
  266. while (bytecount < bsize) {
  267. /* XXX - do we check for an Ctrl-C press in here ??? */
  268. (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
  269. (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
  270. (*fn->rdata) (&(data[bytecount++]), cookie); /* read the data */
  271. #ifdef CFG_FPGA_PROG_FEEDBACK
  272. if (bytecount % (bsize / 40) == 0)
  273. putc ('.'); /* let them know we are alive */
  274. #endif
  275. }
  276. (*fn->cs) (FALSE, FALSE, cookie); /* Deassert the chip select */
  277. (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
  278. (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
  279. #ifdef CFG_FPGA_PROG_FEEDBACK
  280. putc ('\n'); /* terminate the dotted line */
  281. #endif
  282. puts ("Done.\n");
  283. /* XXX - checksum the data? */
  284. } else {
  285. printf ("%s: NULL Interface function table!\n", __FUNCTION__);
  286. }
  287. return ret_val;
  288. }
  289. static int Spartan2_sp_reloc (Xilinx_desc * desc, ulong reloc_offset)
  290. {
  291. int ret_val = FPGA_FAIL; /* assume the worst */
  292. Xilinx_Spartan2_Slave_Parallel_fns *fn_r, *fn =
  293. (Xilinx_Spartan2_Slave_Parallel_fns *) (desc->iface_fns);
  294. if (fn) {
  295. ulong addr;
  296. /* Get the relocated table address */
  297. addr = (ulong) fn + reloc_offset;
  298. fn_r = (Xilinx_Spartan2_Slave_Parallel_fns *) addr;
  299. if (!fn_r->relocated) {
  300. if (memcmp (fn_r, fn,
  301. sizeof (Xilinx_Spartan2_Slave_Parallel_fns))
  302. == 0) {
  303. /* good copy of the table, fix the descriptor pointer */
  304. desc->iface_fns = fn_r;
  305. } else {
  306. PRINTF ("%s: Invalid function table at 0x%p\n",
  307. __FUNCTION__, fn_r);
  308. return FPGA_FAIL;
  309. }
  310. PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
  311. desc);
  312. addr = (ulong) (fn->pre) + reloc_offset;
  313. fn_r->pre = (Xilinx_pre_fn) addr;
  314. addr = (ulong) (fn->pgm) + reloc_offset;
  315. fn_r->pgm = (Xilinx_pgm_fn) addr;
  316. addr = (ulong) (fn->init) + reloc_offset;
  317. fn_r->init = (Xilinx_init_fn) addr;
  318. addr = (ulong) (fn->done) + reloc_offset;
  319. fn_r->done = (Xilinx_done_fn) addr;
  320. addr = (ulong) (fn->clk) + reloc_offset;
  321. fn_r->clk = (Xilinx_clk_fn) addr;
  322. addr = (ulong) (fn->err) + reloc_offset;
  323. fn_r->err = (Xilinx_err_fn) addr;
  324. addr = (ulong) (fn->cs) + reloc_offset;
  325. fn_r->cs = (Xilinx_cs_fn) addr;
  326. addr = (ulong) (fn->wr) + reloc_offset;
  327. fn_r->wr = (Xilinx_wr_fn) addr;
  328. addr = (ulong) (fn->rdata) + reloc_offset;
  329. fn_r->rdata = (Xilinx_rdata_fn) addr;
  330. addr = (ulong) (fn->wdata) + reloc_offset;
  331. fn_r->wdata = (Xilinx_wdata_fn) addr;
  332. addr = (ulong) (fn->busy) + reloc_offset;
  333. fn_r->busy = (Xilinx_busy_fn) addr;
  334. addr = (ulong) (fn->abort) + reloc_offset;
  335. fn_r->abort = (Xilinx_abort_fn) addr;
  336. addr = (ulong) (fn->post) + reloc_offset;
  337. fn_r->post = (Xilinx_post_fn) addr;
  338. fn_r->relocated = TRUE;
  339. } else {
  340. /* this table has already been moved */
  341. /* XXX - should check to see if the descriptor is correct */
  342. desc->iface_fns = fn_r;
  343. }
  344. ret_val = FPGA_SUCCESS;
  345. } else {
  346. printf ("%s: NULL Interface function table!\n", __FUNCTION__);
  347. }
  348. return ret_val;
  349. }
  350. /* ------------------------------------------------------------------------- */
  351. static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
  352. {
  353. printf ("%s: Slave Serial Loading is still unsupported\n",
  354. __FUNCTION__);
  355. return FPGA_FAIL;
  356. }
  357. static int Spartan2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
  358. {
  359. printf ("%s: Slave Serial Dumping is still unsupported\n",
  360. __FUNCTION__);
  361. return FPGA_FAIL;
  362. }
  363. static int Spartan2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
  364. {
  365. int ret_val = FPGA_FAIL; /* assume the worst */
  366. Xilinx_Spartan2_Slave_Serial_fns *fn =
  367. (Xilinx_Spartan2_Slave_Serial_fns *) (desc->iface_fns);
  368. if (fn) {
  369. printf ("%s: Slave Serial Loading is still unsupported\n",
  370. __FUNCTION__);
  371. } else {
  372. printf ("%s: NULL Interface function table!\n", __FUNCTION__);
  373. }
  374. return ret_val;
  375. }
  376. #endif