123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687 |
- // SPDX-License-Identifier: (GPL-2.0 OR MIT)
- /* Copyright (c) 2021 StarFive Technology Co., Ltd. */
- / {
- chosen {
- stdout-path = "serial0";
- bootph-pre-ram;
- };
- config {
- u-boot,spl-payload-offset = <0x42000>;
- bootph-pre-ram;
- };
- cpus {
- bootph-pre-ram;
- cpu@0 {
- bootph-pre-ram;
- };
- cpu@1 {
- bootph-pre-ram;
- };
- };
- memory@80000000 {
- bootph-pre-ram;
- };
- soc {
- bootph-pre-ram;
- dmc: dmc@10280000 {
- compatible = "starfive,dubhe-ddr";
- reg = <0x0 0x10280000 0x0 0x10000
- 0x0 0x10290000 0x0 0x10000
- 0x0 0x102A0000 0x0 0x10000>;
- clocks = <&pbus_clk>;
- clock-frequency = <25000000>;
- bootph-pre-ram;
- };
- };
- };
- &clint {
- bootph-pre-ram;
- };
- &pbus_clk {
- bootph-pre-ram;
- };
- &plic0 {
- bootph-pre-ram;
- };
- &spi0 {
- bootph-pre-ram;
-
- mmc@0 {
- bootph-pre-ram;
- };
- };
- &qspi1 {
- bootph-pre-ram;
- flash@0 {
- bootph-pre-ram;
- };
- };
- &uart0 {
- bootph-pre-ram;
- };
- &pbus_clk {
- bootph-pre-ram;
- };
- &clint {
- clocks = <&pbus_clk>;
- bootph-pre-ram;
- };
- &cpu0_intc {
- bootph-pre-ram;
- };
|