dubhe-fpga-u-boot.dtsi 1.0 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /* Copyright (c) 2021 StarFive Technology Co., Ltd. */
  3. / {
  4. chosen {
  5. stdout-path = "serial0";
  6. bootph-pre-ram;
  7. };
  8. config {
  9. u-boot,spl-payload-offset = <0x42000>;
  10. bootph-pre-ram;
  11. };
  12. cpus {
  13. bootph-pre-ram;
  14. cpu@0 {
  15. bootph-pre-ram;
  16. };
  17. cpu@1 {
  18. bootph-pre-ram;
  19. };
  20. };
  21. memory@80000000 {
  22. bootph-pre-ram;
  23. };
  24. soc {
  25. bootph-pre-ram;
  26. dmc: dmc@10280000 {
  27. compatible = "starfive,dubhe-ddr";
  28. reg = <0x0 0x10280000 0x0 0x10000
  29. 0x0 0x10290000 0x0 0x10000
  30. 0x0 0x102A0000 0x0 0x10000>;
  31. clocks = <&pbus_clk>;
  32. clock-frequency = <25000000>;
  33. bootph-pre-ram;
  34. };
  35. };
  36. };
  37. &clint {
  38. bootph-pre-ram;
  39. };
  40. &pbus_clk {
  41. bootph-pre-ram;
  42. };
  43. &plic0 {
  44. bootph-pre-ram;
  45. };
  46. &spi0 {
  47. bootph-pre-ram;
  48. mmc@0 {
  49. bootph-pre-ram;
  50. };
  51. };
  52. &qspi1 {
  53. bootph-pre-ram;
  54. flash@0 {
  55. bootph-pre-ram;
  56. };
  57. };
  58. &uart0 {
  59. bootph-pre-ram;
  60. };
  61. &pbus_clk {
  62. bootph-pre-ram;
  63. };
  64. &clint {
  65. clocks = <&pbus_clk>;
  66. bootph-pre-ram;
  67. };
  68. &cpu0_intc {
  69. bootph-pre-ram;
  70. };