fsl_sata.c 25 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2008,2010 Freescale Semiconductor, Inc.
  4. * Copyright 2019 NXP
  5. * Author: Dave Liu <daveliu@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <command.h>
  9. #include <console.h>
  10. #include <asm/io.h>
  11. #include <asm/processor.h>
  12. #include <asm/fsl_serdes.h>
  13. #include <malloc.h>
  14. #include <libata.h>
  15. #include <fis.h>
  16. #include <sata.h>
  17. #include "fsl_sata.h"
  18. #if CONFIG_IS_ENABLED(BLK)
  19. #include <dm.h>
  20. #include <ahci.h>
  21. #include <blk.h>
  22. #else
  23. #ifndef CONFIG_SYS_SATA1_FLAGS
  24. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  25. #endif
  26. #ifndef CONFIG_SYS_SATA2_FLAGS
  27. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  28. #endif
  29. static struct fsl_sata_info fsl_sata_info[] = {
  30. #ifdef CONFIG_SATA1
  31. {CONFIG_SYS_SATA1, CONFIG_SYS_SATA1_FLAGS},
  32. #else
  33. {0, 0},
  34. #endif
  35. #ifdef CONFIG_SATA2
  36. {CONFIG_SYS_SATA2, CONFIG_SYS_SATA2_FLAGS},
  37. #else
  38. {0, 0},
  39. #endif
  40. };
  41. #endif
  42. static inline void sdelay(unsigned long sec)
  43. {
  44. unsigned long i;
  45. for (i = 0; i < sec; i++)
  46. mdelay(1000);
  47. }
  48. static void fsl_sata_dump_sfis(struct sata_fis_d2h *s)
  49. {
  50. printf("Status FIS dump:\n\r");
  51. printf("fis_type: %02x\n\r", s->fis_type);
  52. printf("pm_port_i: %02x\n\r", s->pm_port_i);
  53. printf("status: %02x\n\r", s->status);
  54. printf("error: %02x\n\r", s->error);
  55. printf("lba_low: %02x\n\r", s->lba_low);
  56. printf("lba_mid: %02x\n\r", s->lba_mid);
  57. printf("lba_high: %02x\n\r", s->lba_high);
  58. printf("device: %02x\n\r", s->device);
  59. printf("lba_low_exp: %02x\n\r", s->lba_low_exp);
  60. printf("lba_mid_exp: %02x\n\r", s->lba_mid_exp);
  61. printf("lba_high_exp: %02x\n\r", s->lba_high_exp);
  62. printf("res1: %02x\n\r", s->res1);
  63. printf("sector_count: %02x\n\r", s->sector_count);
  64. printf("sector_count_exp: %02x\n\r", s->sector_count_exp);
  65. }
  66. static int ata_wait_register(unsigned __iomem *addr, u32 mask,
  67. u32 val, u32 timeout_msec)
  68. {
  69. int i;
  70. u32 temp;
  71. for (i = 0; (((temp = in_le32(addr)) & mask) != val)
  72. && i < timeout_msec; i++)
  73. mdelay(1);
  74. return (i < timeout_msec) ? 0 : -1;
  75. }
  76. #if !CONFIG_IS_ENABLED(BLK)
  77. int init_sata(int dev)
  78. #else
  79. static int init_sata(struct fsl_ata_priv *priv, int dev)
  80. #endif
  81. {
  82. u32 length, align;
  83. cmd_hdr_tbl_t *cmd_hdr;
  84. u32 cda;
  85. u32 val32;
  86. fsl_sata_reg_t __iomem *reg;
  87. u32 sig;
  88. int i;
  89. fsl_sata_t *sata;
  90. if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
  91. printf("the sata index %d is out of ranges\n\r", dev);
  92. return -1;
  93. }
  94. #ifdef CONFIG_MPC85xx
  95. if ((dev == 0) && (!is_serdes_configured(SATA1))) {
  96. printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
  97. return -1;
  98. }
  99. if ((dev == 1) && (!is_serdes_configured(SATA2))) {
  100. printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
  101. return -1;
  102. }
  103. #endif
  104. /* Allocate SATA device driver struct */
  105. sata = (fsl_sata_t *)malloc(sizeof(fsl_sata_t));
  106. if (!sata) {
  107. printf("alloc the sata device struct failed\n\r");
  108. return -1;
  109. }
  110. /* Zero all of the device driver struct */
  111. memset((void *)sata, 0, sizeof(fsl_sata_t));
  112. snprintf(sata->name, 12, "SATA%d:\n", dev);
  113. /* Set the controller register base address to device struct */
  114. #if !CONFIG_IS_ENABLED(BLK)
  115. sata_dev_desc[dev].priv = (void *)sata;
  116. reg = (fsl_sata_reg_t *)(fsl_sata_info[dev].sata_reg_base);
  117. sata->dma_flag = fsl_sata_info[dev].flags;
  118. #else
  119. reg = (fsl_sata_reg_t *)(priv->base + priv->offset * dev);
  120. sata->dma_flag = priv->flag;
  121. priv->fsl_sata = sata;
  122. #endif
  123. sata->reg_base = reg;
  124. /* Allocate the command header table, 4 bytes aligned */
  125. length = sizeof(struct cmd_hdr_tbl);
  126. align = SATA_HC_CMD_HDR_TBL_ALIGN;
  127. sata->cmd_hdr_tbl_offset = (void *)malloc(length + align);
  128. if (!sata->cmd_hdr_tbl_offset) {
  129. printf("alloc the command header failed\n\r");
  130. return -1;
  131. }
  132. cmd_hdr = (cmd_hdr_tbl_t *)(((u32)sata->cmd_hdr_tbl_offset + align)
  133. & ~(align - 1));
  134. sata->cmd_hdr = cmd_hdr;
  135. /* Zero all of the command header table */
  136. memset((void *)sata->cmd_hdr_tbl_offset, 0, length + align);
  137. /* Allocate command descriptor for all command */
  138. length = sizeof(struct cmd_desc) * SATA_HC_MAX_CMD;
  139. align = SATA_HC_CMD_DESC_ALIGN;
  140. sata->cmd_desc_offset = (void *)malloc(length + align);
  141. if (!sata->cmd_desc_offset) {
  142. printf("alloc the command descriptor failed\n\r");
  143. return -1;
  144. }
  145. sata->cmd_desc = (cmd_desc_t *)(((u32)sata->cmd_desc_offset + align)
  146. & ~(align - 1));
  147. /* Zero all of command descriptor */
  148. memset((void *)sata->cmd_desc_offset, 0, length + align);
  149. /* Link the command descriptor to command header */
  150. for (i = 0; i < SATA_HC_MAX_CMD; i++) {
  151. cda = ((u32)sata->cmd_desc + SATA_HC_CMD_DESC_SIZE * i)
  152. & ~(CMD_HDR_CDA_ALIGN - 1);
  153. cmd_hdr->cmd_slot[i].cda = cpu_to_le32(cda);
  154. }
  155. /* To have safe state, force the controller offline */
  156. val32 = in_le32(&reg->hcontrol);
  157. val32 &= ~HCONTROL_ONOFF;
  158. val32 |= HCONTROL_FORCE_OFFLINE;
  159. out_le32(&reg->hcontrol, val32);
  160. /* Wait the controller offline */
  161. ata_wait_register(&reg->hstatus, HSTATUS_ONOFF, 0, 1000);
  162. /* Set the command header base address to CHBA register to tell DMA */
  163. out_le32(&reg->chba, (u32)cmd_hdr & ~0x3);
  164. /* Snoop for the command header */
  165. val32 = in_le32(&reg->hcontrol);
  166. val32 |= HCONTROL_HDR_SNOOP;
  167. out_le32(&reg->hcontrol, val32);
  168. /* Disable all of interrupts */
  169. val32 = in_le32(&reg->hcontrol);
  170. val32 &= ~HCONTROL_INT_EN_ALL;
  171. out_le32(&reg->hcontrol, val32);
  172. /* Clear all of interrupts */
  173. val32 = in_le32(&reg->hstatus);
  174. out_le32(&reg->hstatus, val32);
  175. /* Set the ICC, no interrupt coalescing */
  176. out_le32(&reg->icc, 0x01000000);
  177. /* No PM attatched, the SATA device direct connect */
  178. out_le32(&reg->cqpmp, 0);
  179. /* Clear SError register */
  180. val32 = in_le32(&reg->serror);
  181. out_le32(&reg->serror, val32);
  182. /* Clear CER register */
  183. val32 = in_le32(&reg->cer);
  184. out_le32(&reg->cer, val32);
  185. /* Clear DER register */
  186. val32 = in_le32(&reg->der);
  187. out_le32(&reg->der, val32);
  188. /* No device detection or initialization action requested */
  189. out_le32(&reg->scontrol, 0x00000300);
  190. /* Configure the transport layer, default value */
  191. out_le32(&reg->transcfg, 0x08000016);
  192. /* Configure the link layer, default value */
  193. out_le32(&reg->linkcfg, 0x0000ff34);
  194. /* Bring the controller online */
  195. val32 = in_le32(&reg->hcontrol);
  196. val32 |= HCONTROL_ONOFF;
  197. out_le32(&reg->hcontrol, val32);
  198. mdelay(100);
  199. /* print sata device name */
  200. if (!dev)
  201. printf("%s ", sata->name);
  202. else
  203. printf(" %s ", sata->name);
  204. /* Wait PHY RDY signal changed for 500ms */
  205. ata_wait_register(&reg->hstatus, HSTATUS_PHY_RDY,
  206. HSTATUS_PHY_RDY, 500);
  207. /* Check PHYRDY */
  208. val32 = in_le32(&reg->hstatus);
  209. if (val32 & HSTATUS_PHY_RDY) {
  210. sata->link = 1;
  211. } else {
  212. sata->link = 0;
  213. printf("(No RDY)\n\r");
  214. return -1;
  215. }
  216. /* Wait for signature updated, which is 1st D2H */
  217. ata_wait_register(&reg->hstatus, HSTATUS_SIGNATURE,
  218. HSTATUS_SIGNATURE, 10000);
  219. if (val32 & HSTATUS_SIGNATURE) {
  220. sig = in_le32(&reg->sig);
  221. debug("Signature updated, the sig =%08x\n\r", sig);
  222. sata->ata_device_type = ata_dev_classify(sig);
  223. }
  224. /* Check the speed */
  225. val32 = in_le32(&reg->sstatus);
  226. if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN1)
  227. printf("(1.5 Gbps)\n\r");
  228. else if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN2)
  229. printf("(3 Gbps)\n\r");
  230. return 0;
  231. }
  232. int reset_sata(int dev)
  233. {
  234. return 0;
  235. }
  236. static void fsl_sata_dump_regs(fsl_sata_reg_t __iomem *reg)
  237. {
  238. printf("\n\rSATA: %08x\n\r", (u32)reg);
  239. printf("CQR: %08x\n\r", in_le32(&reg->cqr));
  240. printf("CAR: %08x\n\r", in_le32(&reg->car));
  241. printf("CCR: %08x\n\r", in_le32(&reg->ccr));
  242. printf("CER: %08x\n\r", in_le32(&reg->cer));
  243. printf("CQR: %08x\n\r", in_le32(&reg->cqr));
  244. printf("DER: %08x\n\r", in_le32(&reg->der));
  245. printf("CHBA: %08x\n\r", in_le32(&reg->chba));
  246. printf("HStatus: %08x\n\r", in_le32(&reg->hstatus));
  247. printf("HControl: %08x\n\r", in_le32(&reg->hcontrol));
  248. printf("CQPMP: %08x\n\r", in_le32(&reg->cqpmp));
  249. printf("SIG: %08x\n\r", in_le32(&reg->sig));
  250. printf("ICC: %08x\n\r", in_le32(&reg->icc));
  251. printf("SStatus: %08x\n\r", in_le32(&reg->sstatus));
  252. printf("SError: %08x\n\r", in_le32(&reg->serror));
  253. printf("SControl: %08x\n\r", in_le32(&reg->scontrol));
  254. printf("SNotification: %08x\n\r", in_le32(&reg->snotification));
  255. printf("TransCfg: %08x\n\r", in_le32(&reg->transcfg));
  256. printf("TransStatus: %08x\n\r", in_le32(&reg->transstatus));
  257. printf("LinkCfg: %08x\n\r", in_le32(&reg->linkcfg));
  258. printf("LinkCfg1: %08x\n\r", in_le32(&reg->linkcfg1));
  259. printf("LinkCfg2: %08x\n\r", in_le32(&reg->linkcfg2));
  260. printf("LinkStatus: %08x\n\r", in_le32(&reg->linkstatus));
  261. printf("LinkStatus1: %08x\n\r", in_le32(&reg->linkstatus1));
  262. printf("PhyCtrlCfg: %08x\n\r", in_le32(&reg->phyctrlcfg));
  263. printf("SYSPR: %08x\n\r", in_be32(&reg->syspr));
  264. }
  265. static int fsl_ata_exec_ata_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
  266. int is_ncq, int tag, u8 *buffer, u32 len)
  267. {
  268. cmd_hdr_entry_t *cmd_hdr;
  269. cmd_desc_t *cmd_desc;
  270. sata_fis_h2d_t *h2d;
  271. prd_entry_t *prde;
  272. u32 ext_c_ddc;
  273. u32 prde_count;
  274. u32 val32;
  275. u32 ttl;
  276. fsl_sata_reg_t __iomem *reg = sata->reg_base;
  277. int i;
  278. /* Check xfer length */
  279. if (len > SATA_HC_MAX_XFER_LEN) {
  280. printf("max transfer length is 64MB\n\r");
  281. return 0;
  282. }
  283. /* Setup the command descriptor */
  284. cmd_desc = sata->cmd_desc + tag;
  285. /* Get the pointer cfis of command descriptor */
  286. h2d = (sata_fis_h2d_t *)cmd_desc->cfis;
  287. /* Zero the cfis of command descriptor */
  288. memset((void *)h2d, 0, SATA_HC_CMD_DESC_CFIS_SIZE);
  289. /* Copy the cfis from user to command descriptor */
  290. h2d->fis_type = cfis->fis_type;
  291. h2d->pm_port_c = cfis->pm_port_c;
  292. h2d->command = cfis->command;
  293. h2d->features = cfis->features;
  294. h2d->features_exp = cfis->features_exp;
  295. h2d->lba_low = cfis->lba_low;
  296. h2d->lba_mid = cfis->lba_mid;
  297. h2d->lba_high = cfis->lba_high;
  298. h2d->lba_low_exp = cfis->lba_low_exp;
  299. h2d->lba_mid_exp = cfis->lba_mid_exp;
  300. h2d->lba_high_exp = cfis->lba_high_exp;
  301. if (!is_ncq) {
  302. h2d->sector_count = cfis->sector_count;
  303. h2d->sector_count_exp = cfis->sector_count_exp;
  304. } else { /* NCQ */
  305. h2d->sector_count = (u8)(tag << 3);
  306. }
  307. h2d->device = cfis->device;
  308. h2d->control = cfis->control;
  309. /* Setup the PRD table */
  310. prde = (prd_entry_t *)cmd_desc->prdt;
  311. memset((void *)prde, 0, sizeof(struct prdt));
  312. prde_count = 0;
  313. ttl = len;
  314. for (i = 0; i < SATA_HC_MAX_PRD_DIRECT; i++) {
  315. if (!len)
  316. break;
  317. prde->dba = cpu_to_le32((u32)buffer & ~0x3);
  318. debug("dba = %08x\n\r", (u32)buffer);
  319. if (len < PRD_ENTRY_MAX_XFER_SZ) {
  320. ext_c_ddc = PRD_ENTRY_DATA_SNOOP | len;
  321. debug("ext_c_ddc1 = %08x, len = %08x\n\r", ext_c_ddc, len);
  322. prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
  323. prde_count++;
  324. prde++;
  325. break;
  326. } else {
  327. ext_c_ddc = PRD_ENTRY_DATA_SNOOP; /* 4M bytes */
  328. debug("ext_c_ddc2 = %08x, len = %08x\n\r", ext_c_ddc, len);
  329. prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
  330. buffer += PRD_ENTRY_MAX_XFER_SZ;
  331. len -= PRD_ENTRY_MAX_XFER_SZ;
  332. prde_count++;
  333. prde++;
  334. }
  335. }
  336. /* Setup the command slot of cmd hdr */
  337. cmd_hdr = (cmd_hdr_entry_t *)&sata->cmd_hdr->cmd_slot[tag];
  338. cmd_hdr->cda = cpu_to_le32((u32)cmd_desc & ~0x3);
  339. val32 = prde_count << CMD_HDR_PRD_ENTRY_SHIFT;
  340. val32 |= sizeof(sata_fis_h2d_t);
  341. cmd_hdr->prde_fis_len = cpu_to_le32(val32);
  342. cmd_hdr->ttl = cpu_to_le32(ttl);
  343. if (!is_ncq) {
  344. val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP;
  345. } else {
  346. val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP | CMD_HDR_ATTR_FPDMA;
  347. }
  348. tag &= CMD_HDR_ATTR_TAG;
  349. val32 |= tag;
  350. debug("attribute = %08x\n\r", val32);
  351. cmd_hdr->attribute = cpu_to_le32(val32);
  352. /* Make sure cmd desc and cmd slot valid before command issue */
  353. sync();
  354. /* PMP*/
  355. val32 = (u32)(h2d->pm_port_c & 0x0f);
  356. out_le32(&reg->cqpmp, val32);
  357. /* Wait no active */
  358. if (ata_wait_register(&reg->car, (1 << tag), 0, 10000))
  359. printf("Wait no active time out\n\r");
  360. /* Issue command */
  361. if (!(in_le32(&reg->cqr) & (1 << tag))) {
  362. val32 = 1 << tag;
  363. out_le32(&reg->cqr, val32);
  364. }
  365. /* Wait command completed for 10s */
  366. if (ata_wait_register(&reg->ccr, (1 << tag), (1 << tag), 10000)) {
  367. if (!is_ncq)
  368. printf("Non-NCQ command time out\n\r");
  369. else
  370. printf("NCQ command time out\n\r");
  371. }
  372. val32 = in_le32(&reg->cer);
  373. if (val32) {
  374. u32 der;
  375. fsl_sata_dump_sfis((struct sata_fis_d2h *)cmd_desc->sfis);
  376. printf("CE at device\n\r");
  377. fsl_sata_dump_regs(reg);
  378. der = in_le32(&reg->der);
  379. out_le32(&reg->cer, val32);
  380. out_le32(&reg->der, der);
  381. }
  382. /* Clear complete flags */
  383. val32 = in_le32(&reg->ccr);
  384. out_le32(&reg->ccr, val32);
  385. return len;
  386. }
  387. static int fsl_ata_exec_reset_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
  388. int tag, u8 *buffer, u32 len)
  389. {
  390. return 0;
  391. }
  392. static int fsl_sata_exec_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
  393. enum cmd_type command_type, int tag, u8 *buffer, u32 len)
  394. {
  395. int rc;
  396. if (tag > SATA_HC_MAX_CMD || tag < 0) {
  397. printf("tag is out of range, tag=%d\n\r", tag);
  398. return -1;
  399. }
  400. switch (command_type) {
  401. case CMD_ATA:
  402. rc = fsl_ata_exec_ata_cmd(sata, cfis, 0, tag, buffer, len);
  403. return rc;
  404. case CMD_RESET:
  405. rc = fsl_ata_exec_reset_cmd(sata, cfis, tag, buffer, len);
  406. return rc;
  407. case CMD_NCQ:
  408. rc = fsl_ata_exec_ata_cmd(sata, cfis, 1, tag, buffer, len);
  409. return rc;
  410. case CMD_ATAPI:
  411. case CMD_VENDOR_BIST:
  412. case CMD_BIST:
  413. printf("not support now\n\r");
  414. return -1;
  415. default:
  416. break;
  417. }
  418. return -1;
  419. }
  420. static void fsl_sata_xfer_mode(fsl_sata_t *sata, u16 *id)
  421. {
  422. sata->pio = id[ATA_ID_PIO_MODES];
  423. sata->mwdma = id[ATA_ID_MWDMA_MODES];
  424. sata->udma = id[ATA_ID_UDMA_MODES];
  425. debug("pio %04x, mwdma %04x, udma %04x\n\r", sata->pio, sata->mwdma, sata->udma);
  426. }
  427. static void fsl_sata_set_features(fsl_sata_t *sata)
  428. {
  429. struct sata_fis_h2d h2d, *cfis = &h2d;
  430. u8 udma_cap;
  431. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  432. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  433. cfis->pm_port_c = 0x80; /* is command */
  434. cfis->command = ATA_CMD_SET_FEATURES;
  435. cfis->features = SETFEATURES_XFER;
  436. /* First check the device capablity */
  437. udma_cap = (u8)(sata->udma & 0xff);
  438. debug("udma_cap %02x\n\r", udma_cap);
  439. if (udma_cap == ATA_UDMA6)
  440. cfis->sector_count = XFER_UDMA_6;
  441. if (udma_cap == ATA_UDMA5)
  442. cfis->sector_count = XFER_UDMA_5;
  443. if (udma_cap == ATA_UDMA4)
  444. cfis->sector_count = XFER_UDMA_4;
  445. if (udma_cap == ATA_UDMA3)
  446. cfis->sector_count = XFER_UDMA_3;
  447. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
  448. }
  449. static u32 fsl_sata_rw_cmd(fsl_sata_t *sata, u32 start, u32 blkcnt, u8 *buffer,
  450. int is_write)
  451. {
  452. struct sata_fis_h2d h2d, *cfis = &h2d;
  453. u32 block;
  454. block = start;
  455. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  456. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  457. cfis->pm_port_c = 0x80; /* is command */
  458. cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
  459. cfis->device = ATA_LBA;
  460. cfis->device |= (block >> 24) & 0xf;
  461. cfis->lba_high = (block >> 16) & 0xff;
  462. cfis->lba_mid = (block >> 8) & 0xff;
  463. cfis->lba_low = block & 0xff;
  464. cfis->sector_count = (u8)(blkcnt & 0xff);
  465. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt);
  466. return blkcnt;
  467. }
  468. static void fsl_sata_flush_cache(fsl_sata_t *sata)
  469. {
  470. struct sata_fis_h2d h2d, *cfis = &h2d;
  471. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  472. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  473. cfis->pm_port_c = 0x80; /* is command */
  474. cfis->command = ATA_CMD_FLUSH;
  475. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
  476. }
  477. static u32 fsl_sata_rw_cmd_ext(fsl_sata_t *sata, u32 start, u32 blkcnt,
  478. u8 *buffer, int is_write)
  479. {
  480. struct sata_fis_h2d h2d, *cfis = &h2d;
  481. u64 block;
  482. block = (u64)start;
  483. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  484. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  485. cfis->pm_port_c = 0x80; /* is command */
  486. cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
  487. : ATA_CMD_READ_EXT;
  488. cfis->lba_high_exp = (block >> 40) & 0xff;
  489. cfis->lba_mid_exp = (block >> 32) & 0xff;
  490. cfis->lba_low_exp = (block >> 24) & 0xff;
  491. cfis->lba_high = (block >> 16) & 0xff;
  492. cfis->lba_mid = (block >> 8) & 0xff;
  493. cfis->lba_low = block & 0xff;
  494. cfis->device = ATA_LBA;
  495. cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
  496. cfis->sector_count = blkcnt & 0xff;
  497. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt);
  498. return blkcnt;
  499. }
  500. static u32 fsl_sata_rw_ncq_cmd(fsl_sata_t *sata, u32 start, u32 blkcnt,
  501. u8 *buffer, int is_write)
  502. {
  503. struct sata_fis_h2d h2d, *cfis = &h2d;
  504. int ncq_channel;
  505. u64 block;
  506. if (sata->lba48 != 1) {
  507. printf("execute FPDMA command on non-LBA48 hard disk\n\r");
  508. return -1;
  509. }
  510. block = (u64)start;
  511. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  512. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  513. cfis->pm_port_c = 0x80; /* is command */
  514. cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE
  515. : ATA_CMD_FPDMA_READ;
  516. cfis->lba_high_exp = (block >> 40) & 0xff;
  517. cfis->lba_mid_exp = (block >> 32) & 0xff;
  518. cfis->lba_low_exp = (block >> 24) & 0xff;
  519. cfis->lba_high = (block >> 16) & 0xff;
  520. cfis->lba_mid = (block >> 8) & 0xff;
  521. cfis->lba_low = block & 0xff;
  522. cfis->device = ATA_LBA;
  523. cfis->features_exp = (blkcnt >> 8) & 0xff;
  524. cfis->features = blkcnt & 0xff;
  525. if (sata->queue_depth >= SATA_HC_MAX_CMD)
  526. ncq_channel = SATA_HC_MAX_CMD - 1;
  527. else
  528. ncq_channel = sata->queue_depth - 1;
  529. /* Use the latest queue */
  530. fsl_sata_exec_cmd(sata, cfis, CMD_NCQ, ncq_channel, buffer, ATA_SECT_SIZE * blkcnt);
  531. return blkcnt;
  532. }
  533. static void fsl_sata_flush_cache_ext(fsl_sata_t *sata)
  534. {
  535. struct sata_fis_h2d h2d, *cfis = &h2d;
  536. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  537. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  538. cfis->pm_port_c = 0x80; /* is command */
  539. cfis->command = ATA_CMD_FLUSH_EXT;
  540. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
  541. }
  542. static void fsl_sata_init_wcache(fsl_sata_t *sata, u16 *id)
  543. {
  544. if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
  545. sata->wcache = 1;
  546. if (ata_id_has_flush(id))
  547. sata->flush = 1;
  548. if (ata_id_has_flush_ext(id))
  549. sata->flush_ext = 1;
  550. }
  551. static u32 ata_low_level_rw_lba48(fsl_sata_t *sata, u32 blknr, lbaint_t blkcnt,
  552. const void *buffer, int is_write)
  553. {
  554. u32 start, blks;
  555. u8 *addr;
  556. int max_blks;
  557. start = blknr;
  558. blks = blkcnt;
  559. addr = (u8 *)buffer;
  560. max_blks = ATA_MAX_SECTORS_LBA48;
  561. do {
  562. if (blks > max_blks) {
  563. if (sata->dma_flag != FLAGS_FPDMA)
  564. fsl_sata_rw_cmd_ext(sata, start, max_blks, addr,
  565. is_write);
  566. else
  567. fsl_sata_rw_ncq_cmd(sata, start, max_blks, addr,
  568. is_write);
  569. start += max_blks;
  570. blks -= max_blks;
  571. addr += ATA_SECT_SIZE * max_blks;
  572. } else {
  573. if (sata->dma_flag != FLAGS_FPDMA)
  574. fsl_sata_rw_cmd_ext(sata, start, blks, addr,
  575. is_write);
  576. else
  577. fsl_sata_rw_ncq_cmd(sata, start, blks, addr,
  578. is_write);
  579. start += blks;
  580. blks = 0;
  581. addr += ATA_SECT_SIZE * blks;
  582. }
  583. } while (blks != 0);
  584. return blkcnt;
  585. }
  586. static u32 ata_low_level_rw_lba28(fsl_sata_t *sata, u32 blknr, u32 blkcnt,
  587. const void *buffer, int is_write)
  588. {
  589. u32 start, blks;
  590. u8 *addr;
  591. int max_blks;
  592. start = blknr;
  593. blks = blkcnt;
  594. addr = (u8 *)buffer;
  595. max_blks = ATA_MAX_SECTORS;
  596. do {
  597. if (blks > max_blks) {
  598. fsl_sata_rw_cmd(sata, start, max_blks, addr, is_write);
  599. start += max_blks;
  600. blks -= max_blks;
  601. addr += ATA_SECT_SIZE * max_blks;
  602. } else {
  603. fsl_sata_rw_cmd(sata, start, blks, addr, is_write);
  604. start += blks;
  605. blks = 0;
  606. addr += ATA_SECT_SIZE * blks;
  607. }
  608. } while (blks != 0);
  609. return blkcnt;
  610. }
  611. /*
  612. * SATA interface between low level driver and command layer
  613. */
  614. #if !CONFIG_IS_ENABLED(BLK)
  615. ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
  616. {
  617. fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
  618. #else
  619. static ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
  620. void *buffer)
  621. {
  622. struct fsl_ata_priv *priv = dev_get_platdata(dev);
  623. fsl_sata_t *sata = priv->fsl_sata;
  624. #endif
  625. u32 rc;
  626. if (sata->lba48)
  627. rc = ata_low_level_rw_lba48(sata, blknr, blkcnt, buffer,
  628. READ_CMD);
  629. else
  630. rc = ata_low_level_rw_lba28(sata, blknr, blkcnt, buffer,
  631. READ_CMD);
  632. return rc;
  633. }
  634. #if !CONFIG_IS_ENABLED(BLK)
  635. ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
  636. {
  637. fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
  638. #else
  639. static ulong sata_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
  640. const void *buffer)
  641. {
  642. struct fsl_ata_priv *priv = dev_get_platdata(dev);
  643. fsl_sata_t *sata = priv->fsl_sata;
  644. #endif
  645. u32 rc;
  646. if (sata->lba48) {
  647. rc = ata_low_level_rw_lba48(sata, blknr, blkcnt, buffer,
  648. WRITE_CMD);
  649. if (sata->wcache && sata->flush_ext)
  650. fsl_sata_flush_cache_ext(sata);
  651. } else {
  652. rc = ata_low_level_rw_lba28(sata, blknr, blkcnt, buffer,
  653. WRITE_CMD);
  654. if (sata->wcache && sata->flush)
  655. fsl_sata_flush_cache(sata);
  656. }
  657. return rc;
  658. }
  659. static void fsl_sata_identify(fsl_sata_t *sata, u16 *id)
  660. {
  661. struct sata_fis_h2d h2d, *cfis = &h2d;
  662. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  663. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  664. cfis->pm_port_c = 0x80; /* is command */
  665. cfis->command = ATA_CMD_ID_ATA;
  666. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, (u8 *)id, ATA_ID_WORDS * 2);
  667. ata_swap_buf_le16(id, ATA_ID_WORDS);
  668. }
  669. #if !CONFIG_IS_ENABLED(BLK)
  670. int scan_sata(int dev)
  671. {
  672. fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
  673. #else
  674. static int scan_sata(struct udevice *dev)
  675. {
  676. struct blk_desc *desc = dev_get_uclass_platdata(dev);
  677. struct fsl_ata_priv *priv = dev_get_platdata(dev);
  678. fsl_sata_t *sata = priv->fsl_sata;
  679. #endif
  680. unsigned char serial[ATA_ID_SERNO_LEN + 1];
  681. unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
  682. unsigned char product[ATA_ID_PROD_LEN + 1];
  683. u16 *id;
  684. u64 n_sectors;
  685. /* if no detected link */
  686. if (!sata->link)
  687. return -1;
  688. id = (u16 *)malloc(ATA_ID_WORDS * 2);
  689. if (!id) {
  690. printf("id malloc failed\n\r");
  691. return -1;
  692. }
  693. /* Identify device to get information */
  694. fsl_sata_identify(sata, id);
  695. /* Serial number */
  696. ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
  697. /* Firmware version */
  698. ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
  699. /* Product model */
  700. ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
  701. /* Totoal sectors */
  702. n_sectors = ata_id_n_sectors(id);
  703. #ifdef CONFIG_LBA48
  704. /* Check if support LBA48 */
  705. if (ata_id_has_lba48(id)) {
  706. sata->lba48 = 1;
  707. debug("Device support LBA48\n\r");
  708. } else
  709. debug("Device supports LBA28\n\r");
  710. #endif
  711. #if !CONFIG_IS_ENABLED(BLK)
  712. memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
  713. memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
  714. memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
  715. sata_dev_desc[dev].lba = (u32)n_sectors;
  716. #ifdef CONFIG_LBA48
  717. sata_dev_desc[dev].lba48 = sata->lba48;
  718. #endif
  719. #else
  720. memcpy(desc->product, serial, sizeof(serial));
  721. memcpy(desc->revision, firmware, sizeof(firmware));
  722. memcpy(desc->vendor, product, sizeof(product));
  723. desc->lba = n_sectors;
  724. #ifdef CONFIG_LBA48
  725. desc->lba48 = sata->lba48;
  726. #endif
  727. #endif
  728. /* Get the NCQ queue depth from device */
  729. sata->queue_depth = ata_id_queue_depth(id);
  730. /* Get the xfer mode from device */
  731. fsl_sata_xfer_mode(sata, id);
  732. /* Get the write cache status from device */
  733. fsl_sata_init_wcache(sata, id);
  734. /* Set the xfer mode to highest speed */
  735. fsl_sata_set_features(sata);
  736. #ifdef DEBUG
  737. ata_dump_id(id);
  738. #endif
  739. free((void *)id);
  740. return 0;
  741. }
  742. #if CONFIG_IS_ENABLED(BLK)
  743. static const struct blk_ops sata_fsl_blk_ops = {
  744. .read = sata_read,
  745. .write = sata_write,
  746. };
  747. U_BOOT_DRIVER(sata_fsl_driver) = {
  748. .name = "sata_fsl_blk",
  749. .id = UCLASS_BLK,
  750. .ops = &sata_fsl_blk_ops,
  751. .platdata_auto_alloc_size = sizeof(struct fsl_ata_priv),
  752. };
  753. static int fsl_ata_ofdata_to_platdata(struct udevice *dev)
  754. {
  755. struct fsl_ata_priv *priv = dev_get_priv(dev);
  756. priv->number = dev_read_u32_default(dev, "sata-number", -1);
  757. priv->flag = dev_read_u32_default(dev, "sata-fpdma", -1);
  758. priv->offset = dev_read_u32_default(dev, "sata-offset", -1);
  759. priv->base = dev_read_addr(dev);
  760. if (priv->base == FDT_ADDR_T_NONE)
  761. return -EINVAL;
  762. return 0;
  763. }
  764. static int fsl_ata_probe(struct udevice *dev)
  765. {
  766. struct fsl_ata_priv *blk_priv, *priv;
  767. struct udevice *blk;
  768. char sata_name[10];
  769. int nr_ports;
  770. int ret;
  771. int i;
  772. priv = dev_get_priv(dev);
  773. nr_ports = priv->number;
  774. nr_ports = min(nr_ports, CONFIG_SYS_SATA_MAX_DEVICE);
  775. for (i = 0; i < nr_ports; i++) {
  776. snprintf(sata_name, sizeof(sata_name), "fsl_sata%d", i);
  777. ret = blk_create_devicef(dev, "sata_fsl_blk", sata_name,
  778. IF_TYPE_SATA, -1, 512, 0, &blk);
  779. if (ret) {
  780. debug("Can't create device\n");
  781. return ret;
  782. }
  783. /* Init SATA port */
  784. ret = init_sata(priv, i);
  785. if (ret) {
  786. debug("%s: Failed to init sata\n", __func__);
  787. return ret;
  788. }
  789. blk_priv = dev_get_platdata(blk);
  790. blk_priv->fsl_sata = priv->fsl_sata;
  791. /* Scan SATA port */
  792. ret = scan_sata(blk);
  793. if (ret) {
  794. debug("%s: Failed to scan bus\n", __func__);
  795. return ret;
  796. }
  797. }
  798. return 0;
  799. }
  800. static int sata_fsl_scan(struct udevice *dev)
  801. {
  802. /* Nothing to do here */
  803. return 0;
  804. }
  805. struct ahci_ops sata_fsl_ahci_ops = {
  806. .scan = sata_fsl_scan,
  807. };
  808. static const struct udevice_id fsl_ata_ids[] = {
  809. { .compatible = "fsl,pq-sata-v2" },
  810. { }
  811. };
  812. U_BOOT_DRIVER(fsl_ahci) = {
  813. .name = "fsl_ahci",
  814. .id = UCLASS_AHCI,
  815. .of_match = fsl_ata_ids,
  816. .ops = &sata_fsl_ahci_ops,
  817. .ofdata_to_platdata = fsl_ata_ofdata_to_platdata,
  818. .probe = fsl_ata_probe,
  819. .priv_auto_alloc_size = sizeof(struct fsl_ata_priv),
  820. };
  821. #endif