mtk_nand_headers.h 5.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * MediaTek BootROM NAND header definitions
  4. *
  5. * Copyright (C) 2022 MediaTek Inc.
  6. * Author: Weijie Gao <weijie.gao@mediatek.com>
  7. */
  8. #ifndef _MTK_NAND_HEADERS_H
  9. #define _MTK_NAND_HEADERS_H
  10. #include <stdint.h>
  11. #include <stdbool.h>
  12. struct nand_header_info {
  13. uint32_t page_size;
  14. uint32_t spare_size;
  15. uint32_t gfh_offset;
  16. bool snfi;
  17. };
  18. /* AP BROM Header for NAND */
  19. union nand_boot_header {
  20. struct {
  21. char name[12];
  22. char version[4];
  23. char id[8];
  24. uint16_t ioif; /* I/O interface */
  25. uint16_t pagesize; /* NAND page size */
  26. uint16_t addrcycles; /* Address cycles */
  27. uint16_t oobsize; /* NAND page spare size */
  28. uint16_t pages_of_block; /* Pages of one block */
  29. uint16_t numblocks; /* Total blocks of NAND chip */
  30. uint16_t writesize_shift;
  31. uint16_t erasesize_shift;
  32. uint8_t dummy[60];
  33. uint8_t ecc_parity[28]; /* ECC parity of this header */
  34. };
  35. uint8_t data[0x80];
  36. };
  37. /* HSM BROM Header for NAND */
  38. union hsm_nand_boot_header {
  39. struct {
  40. char id[8];
  41. uint32_t version; /* Header version */
  42. uint32_t config; /* Header config */
  43. uint32_t sector_size; /* ECC step size */
  44. uint32_t fdm_size; /* User OOB size of a step */
  45. uint32_t fdm_ecc_size; /* ECC parity size of a step */
  46. uint32_t lbs;
  47. uint32_t page_size; /* NAND page size */
  48. uint32_t spare_size; /* NAND page spare size */
  49. uint32_t page_per_block; /* Pages of one block */
  50. uint32_t blocks; /* Total blocks of NAND chip */
  51. uint32_t plane_sel_position; /* Plane bit position */
  52. uint32_t pll; /* Value of pll reg */
  53. uint32_t acccon; /* Value of access timing reg */
  54. uint32_t strobe_sel; /* Value of DQS selection reg*/
  55. uint32_t acccon1; /* Value of access timing reg */
  56. uint32_t dqs_mux; /* Value of DQS mux reg */
  57. uint32_t dqs_ctrl; /* Value of DQS control reg */
  58. uint32_t delay_ctrl; /* Value of delay ctrl reg */
  59. uint32_t latch_lat; /* Value of latch latency reg */
  60. uint32_t sample_delay; /* Value of sample delay reg */
  61. uint32_t driving; /* Value of driving reg */
  62. uint32_t bl_start; /* Bootloader start addr */
  63. uint32_t bl_end; /* Bootloader end addr */
  64. uint8_t ecc_parity[42]; /* ECC parity of this header */
  65. };
  66. uint8_t data[0x8E];
  67. };
  68. /* HSM2.0 BROM Header for NAND */
  69. union hsm20_nand_boot_header {
  70. struct {
  71. char id[8];
  72. uint32_t version; /* Header version */
  73. uint32_t config; /* Header config */
  74. uint32_t sector_size; /* ECC step size */
  75. uint32_t fdm_size; /* User OOB size of a step */
  76. uint32_t fdm_ecc_size; /* ECC parity size of a step */
  77. uint32_t lbs;
  78. uint32_t page_size; /* NAND page size */
  79. uint32_t spare_size; /* NAND page spare size */
  80. uint32_t page_per_block; /* Pages of one block */
  81. uint32_t blocks; /* Total blocks of NAND chip */
  82. uint32_t plane_sel_position; /* Plane bit position */
  83. uint32_t pll; /* Value of pll reg */
  84. uint32_t acccon; /* Value of access timing reg */
  85. uint32_t strobe_sel; /* Value of DQS selection reg*/
  86. uint32_t acccon1; /* Value of access timing reg */
  87. uint32_t dqs_mux; /* Value of DQS mux reg */
  88. uint32_t dqs_ctrl; /* Value of DQS control reg */
  89. uint32_t delay_ctrl; /* Value of delay ctrl reg */
  90. uint32_t latch_lat; /* Value of latch latency reg */
  91. uint32_t sample_delay; /* Value of sample delay reg */
  92. uint32_t driving; /* Value of driving reg */
  93. uint32_t reserved;
  94. uint32_t bl0_start; /* Bootloader start addr */
  95. uint32_t bl0_end; /* Bootloader end addr */
  96. uint32_t bl0_type; /* Bootloader type */
  97. uint8_t bl_reserve[84];
  98. uint8_t ecc_parity[42]; /* ECC parity of this header */
  99. };
  100. uint8_t data[0xEA];
  101. };
  102. /* SPIM BROM Header for SPI-NAND */
  103. union spim_nand_boot_header {
  104. struct {
  105. char id[8];
  106. uint32_t version; /* Header version */
  107. uint32_t config; /* Header config */
  108. uint32_t page_size; /* NAND page size */
  109. uint32_t spare_size; /* NAND page spare size */
  110. uint16_t page_per_block; /* Pages of one block */
  111. uint16_t plane_sel_position; /* Plane bit position */
  112. uint16_t reserve_reg;
  113. uint16_t reserve_val;
  114. uint16_t ecc_error; /* ECC error reg addr */
  115. uint16_t ecc_mask; /* ECC error bit mask */
  116. uint32_t bl_start; /* Bootloader start addr */
  117. uint32_t bl_end; /* Bootloader end addr */
  118. uint8_t ecc_parity[32]; /* ECC parity of this header */
  119. uint32_t integrity_crc; /* CRC of this header */
  120. };
  121. uint8_t data[0x50];
  122. };
  123. enum nand_boot_header_type {
  124. NAND_BOOT_AP_HEADER,
  125. NAND_BOOT_HSM_HEADER,
  126. NAND_BOOT_HSM20_HEADER,
  127. NAND_BOOT_SPIM_HEADER
  128. };
  129. #define NAND_BOOT_NAME "BOOTLOADER!"
  130. #define NAND_BOOT_VERSION "V006"
  131. #define NAND_BOOT_ID "NFIINFO"
  132. #define HSM_NAND_BOOT_NAME "NANDCFG!"
  133. #define SPIM_NAND_BOOT_NAME "SPINAND!"
  134. /* Find nand header data by name */
  135. const struct nand_header_type *mtk_nand_header_find(const char *name);
  136. /* Device header size using this nand header */
  137. uint32_t mtk_nand_header_size(const struct nand_header_type *hdr_nand);
  138. /* Get nand info from nand header (page size, spare size, ...) */
  139. int mtk_nand_header_info(const void *ptr, struct nand_header_info *info);
  140. /* Whether given header data is valid */
  141. bool is_mtk_nand_header(const void *ptr);
  142. /* Generate Device header using give nand header */
  143. uint32_t mtk_nand_header_put(const struct nand_header_type *hdr_nand,
  144. void *ptr);
  145. #endif /* _MTK_NAND_HEADERS_H */