mmc.h 30 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2008,2010 Freescale Semiconductor, Inc
  4. * Andy Fleming
  5. *
  6. * Based (loosely) on the Linux code
  7. */
  8. #ifndef _MMC_H_
  9. #define _MMC_H_
  10. #include <linux/bitops.h>
  11. #include <linux/list.h>
  12. #include <linux/sizes.h>
  13. #include <linux/compiler.h>
  14. #include <linux/dma-direction.h>
  15. #include <part.h>
  16. struct bd_info;
  17. #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
  18. #define MMC_SUPPORTS_TUNING
  19. #endif
  20. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  21. #define MMC_SUPPORTS_TUNING
  22. #endif
  23. /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
  24. #define SD_VERSION_SD (1U << 31)
  25. #define MMC_VERSION_MMC (1U << 30)
  26. #define MAKE_SDMMC_VERSION(a, b, c) \
  27. ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
  28. #define MAKE_SD_VERSION(a, b, c) \
  29. (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
  30. #define MAKE_MMC_VERSION(a, b, c) \
  31. (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
  32. #define EXTRACT_SDMMC_MAJOR_VERSION(x) \
  33. (((u32)(x) >> 16) & 0xff)
  34. #define EXTRACT_SDMMC_MINOR_VERSION(x) \
  35. (((u32)(x) >> 8) & 0xff)
  36. #define EXTRACT_SDMMC_CHANGE_VERSION(x) \
  37. ((u32)(x) & 0xff)
  38. #define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0)
  39. #define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0)
  40. #define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0)
  41. #define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0)
  42. #define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0)
  43. #define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0)
  44. #define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0)
  45. #define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0)
  46. #define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0)
  47. #define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0)
  48. #define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0)
  49. #define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0)
  50. #define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0)
  51. #define MMC_VERSION_4_4 MAKE_MMC_VERSION(4, 4, 0)
  52. #define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1)
  53. #define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0)
  54. #define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0)
  55. #define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0)
  56. #define MMC_CAP(mode) (1 << mode)
  57. #define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
  58. #define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52)
  59. #define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52)
  60. #define MMC_MODE_HS200 MMC_CAP(MMC_HS_200)
  61. #define MMC_MODE_HS400 MMC_CAP(MMC_HS_400)
  62. #define MMC_MODE_HS400_ES MMC_CAP(MMC_HS_400_ES)
  63. #define MMC_CAP_NONREMOVABLE BIT(14)
  64. #define MMC_CAP_NEEDS_POLL BIT(15)
  65. #define MMC_CAP_CD_ACTIVE_HIGH BIT(16)
  66. #define MMC_MODE_8BIT BIT(30)
  67. #define MMC_MODE_4BIT BIT(29)
  68. #define MMC_MODE_1BIT BIT(28)
  69. #define MMC_MODE_SPI BIT(27)
  70. #define SD_DATA_4BIT 0x00040000
  71. #define IS_SD(x) ((x)->version & SD_VERSION_SD)
  72. #define IS_MMC(x) ((x)->version & MMC_VERSION_MMC)
  73. #define MMC_DATA_READ 1
  74. #define MMC_DATA_WRITE 2
  75. #define MMC_CMD_GO_IDLE_STATE 0
  76. #define MMC_CMD_SEND_OP_COND 1
  77. #define MMC_CMD_ALL_SEND_CID 2
  78. #define MMC_CMD_SET_RELATIVE_ADDR 3
  79. #define MMC_CMD_SET_DSR 4
  80. #define MMC_CMD_SWITCH 6
  81. #define MMC_CMD_SELECT_CARD 7
  82. #define MMC_CMD_SEND_EXT_CSD 8
  83. #define MMC_CMD_SEND_CSD 9
  84. #define MMC_CMD_SEND_CID 10
  85. #define MMC_CMD_STOP_TRANSMISSION 12
  86. #define MMC_CMD_SEND_STATUS 13
  87. #define MMC_CMD_SET_BLOCKLEN 16
  88. #define MMC_CMD_READ_SINGLE_BLOCK 17
  89. #define MMC_CMD_READ_MULTIPLE_BLOCK 18
  90. #define MMC_CMD_SEND_TUNING_BLOCK 19
  91. #define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
  92. #define MMC_CMD_SET_BLOCK_COUNT 23
  93. #define MMC_CMD_WRITE_SINGLE_BLOCK 24
  94. #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
  95. #define MMC_CMD_ERASE_GROUP_START 35
  96. #define MMC_CMD_ERASE_GROUP_END 36
  97. #define MMC_CMD_ERASE 38
  98. #define MMC_CMD_APP_CMD 55
  99. #define MMC_CMD_SPI_READ_OCR 58
  100. #define MMC_CMD_SPI_CRC_ON_OFF 59
  101. #define MMC_CMD_RES_MAN 62
  102. #define MMC_CMD62_ARG1 0xefac62ec
  103. #define MMC_CMD62_ARG2 0xcbaea7
  104. #define SD_CMD_SEND_RELATIVE_ADDR 3
  105. #define SD_CMD_SWITCH_FUNC 6
  106. #define SD_CMD_SEND_IF_COND 8
  107. #define SD_CMD_SWITCH_UHS18V 11
  108. #define SD_CMD_APP_SET_BUS_WIDTH 6
  109. #define SD_CMD_APP_SD_STATUS 13
  110. #define SD_CMD_ERASE_WR_BLK_START 32
  111. #define SD_CMD_ERASE_WR_BLK_END 33
  112. #define SD_CMD_APP_SEND_OP_COND 41
  113. #define SD_CMD_APP_SEND_SCR 51
  114. static inline bool mmc_is_tuning_cmd(uint cmdidx)
  115. {
  116. if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
  117. (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
  118. return true;
  119. return false;
  120. }
  121. /* SCR definitions in different words */
  122. #define SD_HIGHSPEED_BUSY 0x00020000
  123. #define SD_HIGHSPEED_SUPPORTED 0x00020000
  124. #define UHS_SDR12_BUS_SPEED 0
  125. #define HIGH_SPEED_BUS_SPEED 1
  126. #define UHS_SDR25_BUS_SPEED 1
  127. #define UHS_SDR50_BUS_SPEED 2
  128. #define UHS_SDR104_BUS_SPEED 3
  129. #define UHS_DDR50_BUS_SPEED 4
  130. #define SD_MODE_UHS_SDR12 BIT(UHS_SDR12_BUS_SPEED)
  131. #define SD_MODE_UHS_SDR25 BIT(UHS_SDR25_BUS_SPEED)
  132. #define SD_MODE_UHS_SDR50 BIT(UHS_SDR50_BUS_SPEED)
  133. #define SD_MODE_UHS_SDR104 BIT(UHS_SDR104_BUS_SPEED)
  134. #define SD_MODE_UHS_DDR50 BIT(UHS_DDR50_BUS_SPEED)
  135. #define OCR_BUSY 0x80000000
  136. #define OCR_HCS 0x40000000
  137. #define OCR_S18R 0x1000000
  138. #define OCR_VOLTAGE_MASK 0x007FFF80
  139. #define OCR_ACCESS_MODE 0x60000000
  140. #define MMC_ERASE_ARG 0x00000000
  141. #define MMC_SECURE_ERASE_ARG 0x80000000
  142. #define MMC_TRIM_ARG 0x00000001
  143. #define MMC_DISCARD_ARG 0x00000003
  144. #define MMC_SECURE_TRIM1_ARG 0x80000001
  145. #define MMC_SECURE_TRIM2_ARG 0x80008000
  146. #define MMC_STATUS_MASK (~0x0206BF7F)
  147. #define MMC_STATUS_SWITCH_ERROR (1 << 7)
  148. #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
  149. #define MMC_STATUS_CURR_STATE (0xf << 9)
  150. #define MMC_STATUS_ERROR (1 << 19)
  151. #define MMC_STATE_PRG (7 << 9)
  152. #define MMC_STATE_TRANS (4 << 9)
  153. #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
  154. #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
  155. #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
  156. #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
  157. #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
  158. #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
  159. #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
  160. #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
  161. #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
  162. #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
  163. #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
  164. #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
  165. #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
  166. #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
  167. #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
  168. #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
  169. #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
  170. #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
  171. #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
  172. addressed by index which are
  173. 1 in value field */
  174. #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
  175. addressed by index, which are
  176. 1 in value field */
  177. #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
  178. #define SD_SWITCH_CHECK 0
  179. #define SD_SWITCH_SWITCH 1
  180. /*
  181. * EXT_CSD fields
  182. */
  183. #define EXT_CSD_ENH_START_ADDR 136 /* R/W */
  184. #define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
  185. #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
  186. #define EXT_CSD_PARTITION_SETTING 155 /* R/W */
  187. #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
  188. #define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
  189. #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
  190. #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
  191. #define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */
  192. #define EXT_CSD_WR_REL_PARAM 166 /* R */
  193. #define EXT_CSD_WR_REL_SET 167 /* R/W */
  194. #define EXT_CSD_RPMB_MULT 168 /* RO */
  195. #define EXT_CSD_USER_WP 171 /* R/W & R/W/C_P & R/W/E_P */
  196. #define EXT_CSD_BOOT_WP 173 /* R/W & R/W/C_P */
  197. #define EXT_CSD_BOOT_WP_STATUS 174 /* R */
  198. #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
  199. #define EXT_CSD_BOOT_BUS_WIDTH 177
  200. #define EXT_CSD_PART_CONF 179 /* R/W */
  201. #define EXT_CSD_BUS_WIDTH 183 /* R/W */
  202. #define EXT_CSD_STROBE_SUPPORT 184 /* R/W */
  203. #define EXT_CSD_HS_TIMING 185 /* R/W */
  204. #define EXT_CSD_REV 192 /* RO */
  205. #define EXT_CSD_CARD_TYPE 196 /* RO */
  206. #define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
  207. #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
  208. #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
  209. #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
  210. #define EXT_CSD_BOOT_MULT 226 /* RO */
  211. #define EXT_CSD_SEC_FEATURE 231 /* RO */
  212. #define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
  213. #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
  214. /*
  215. * EXT_CSD field definitions
  216. */
  217. #define EXT_CSD_CMD_SET_NORMAL (1 << 0)
  218. #define EXT_CSD_CMD_SET_SECURE (1 << 1)
  219. #define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
  220. #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
  221. #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
  222. #define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
  223. #define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
  224. #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
  225. | EXT_CSD_CARD_TYPE_DDR_1_2V)
  226. #define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */
  227. /* SDR mode @1.8V I/O */
  228. #define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */
  229. /* SDR mode @1.2V I/O */
  230. #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
  231. EXT_CSD_CARD_TYPE_HS200_1_2V)
  232. #define EXT_CSD_CARD_TYPE_HS400_1_8V BIT(6)
  233. #define EXT_CSD_CARD_TYPE_HS400_1_2V BIT(7)
  234. #define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
  235. EXT_CSD_CARD_TYPE_HS400_1_2V)
  236. #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
  237. #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
  238. #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
  239. #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
  240. #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
  241. #define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */
  242. #define EXT_CSD_BUS_WIDTH_STROBE BIT(7) /* Enhanced strobe mode */
  243. #define EXT_CSD_TIMING_LEGACY 0 /* no high speed */
  244. #define EXT_CSD_TIMING_HS 1 /* HS */
  245. #define EXT_CSD_TIMING_HS200 2 /* HS200 */
  246. #define EXT_CSD_TIMING_HS400 3 /* HS400 */
  247. #define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */
  248. #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
  249. #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
  250. #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
  251. #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
  252. #define EXT_CSD_BOOT_ACK(x) (x << 6)
  253. #define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
  254. #define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
  255. #define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1)
  256. #define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7)
  257. #define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7)
  258. #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
  259. #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
  260. #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
  261. #define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
  262. #define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
  263. #define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
  264. #define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */
  265. #define EXT_CSD_BOOT_WP_B_SEC_WP_SEL (0x80) /* enable partition selector */
  266. #define EXT_CSD_BOOT_WP_B_PWR_WP_SEC_SEL (0x02) /* partition selector to protect */
  267. #define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01) /* power-on write-protect */
  268. #define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */
  269. #define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */
  270. #define EXT_CSD_SEC_FEATURE_TRIM_EN (1 << 4) /* Support secure & insecure trim */
  271. #define R1_ILLEGAL_COMMAND (1 << 22)
  272. #define R1_APP_CMD (1 << 5)
  273. #define MMC_RSP_PRESENT (1 << 0)
  274. #define MMC_RSP_136 (1 << 1) /* 136 bit response */
  275. #define MMC_RSP_CRC (1 << 2) /* expect valid crc */
  276. #define MMC_RSP_BUSY (1 << 3) /* card may send busy */
  277. #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
  278. #define MMC_RSP_NONE (0)
  279. #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  280. #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
  281. MMC_RSP_BUSY)
  282. #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
  283. #define MMC_RSP_R3 (MMC_RSP_PRESENT)
  284. #define MMC_RSP_R4 (MMC_RSP_PRESENT)
  285. #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  286. #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  287. #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  288. #define MMCPART_NOAVAILABLE (0xff)
  289. #define PART_ACCESS_MASK (0x7)
  290. #define PART_SUPPORT (0x1)
  291. #define ENHNCD_SUPPORT (0x2)
  292. #define PART_ENH_ATTRIB (0x1f)
  293. #define MMC_QUIRK_RETRY_SEND_CID BIT(0)
  294. #define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1)
  295. #define MMC_QUIRK_RETRY_APP_CMD BIT(2)
  296. enum mmc_voltage {
  297. MMC_SIGNAL_VOLTAGE_000 = 0,
  298. MMC_SIGNAL_VOLTAGE_120 = 1,
  299. MMC_SIGNAL_VOLTAGE_180 = 2,
  300. MMC_SIGNAL_VOLTAGE_330 = 4,
  301. };
  302. #define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\
  303. MMC_SIGNAL_VOLTAGE_180 |\
  304. MMC_SIGNAL_VOLTAGE_330)
  305. /* Maximum block size for MMC */
  306. #define MMC_MAX_BLOCK_LEN 512
  307. /* The number of MMC physical partitions. These consist of:
  308. * boot partitions (2), general purpose partitions (4) in MMC v4.4.
  309. */
  310. #define MMC_NUM_BOOT_PARTITION 2
  311. #define MMC_PART_RPMB 3 /* RPMB partition number */
  312. /* timing specification used */
  313. #define MMC_TIMING_LEGACY 0
  314. #define MMC_TIMING_MMC_HS 1
  315. #define MMC_TIMING_SD_HS 2
  316. #define MMC_TIMING_UHS_SDR12 3
  317. #define MMC_TIMING_UHS_SDR25 4
  318. #define MMC_TIMING_UHS_SDR50 5
  319. #define MMC_TIMING_UHS_SDR104 6
  320. #define MMC_TIMING_UHS_DDR50 7
  321. #define MMC_TIMING_MMC_DDR52 8
  322. #define MMC_TIMING_MMC_HS200 9
  323. #define MMC_TIMING_MMC_HS400 10
  324. /* Driver model support */
  325. /**
  326. * struct mmc_uclass_priv - Holds information about a device used by the uclass
  327. */
  328. struct mmc_uclass_priv {
  329. struct mmc *mmc;
  330. };
  331. /**
  332. * mmc_get_mmc_dev() - get the MMC struct pointer for a device
  333. *
  334. * Provided that the device is already probed and ready for use, this value
  335. * will be available.
  336. *
  337. * @dev: Device
  338. * Return: associated mmc struct pointer if available, else NULL
  339. */
  340. struct mmc *mmc_get_mmc_dev(const struct udevice *dev);
  341. /* End of driver model support */
  342. struct mmc_cid {
  343. unsigned long psn;
  344. unsigned short oid;
  345. unsigned char mid;
  346. unsigned char prv;
  347. unsigned char mdt;
  348. char pnm[7];
  349. };
  350. struct mmc_cmd {
  351. ushort cmdidx;
  352. uint resp_type;
  353. uint cmdarg;
  354. uint response[4];
  355. };
  356. struct mmc_data {
  357. union {
  358. char *dest;
  359. const char *src; /* src buffers don't get written to */
  360. };
  361. uint flags;
  362. uint blocks;
  363. uint blocksize;
  364. };
  365. /* forward decl. */
  366. struct mmc;
  367. #if CONFIG_IS_ENABLED(DM_MMC)
  368. struct dm_mmc_ops {
  369. /**
  370. * deferred_probe() - Some configurations that need to be deferred
  371. * to just before enumerating the device
  372. *
  373. * @dev: Device to init
  374. * @return 0 if Ok, -ve if error
  375. */
  376. int (*deferred_probe)(struct udevice *dev);
  377. /**
  378. * reinit() - Re-initialization to clear old configuration for
  379. * mmc rescan.
  380. *
  381. * @dev: Device to reinit
  382. * @return 0 if Ok, -ve if error
  383. */
  384. int (*reinit)(struct udevice *dev);
  385. /**
  386. * send_cmd() - Send a command to the MMC device
  387. *
  388. * @dev: Device to receive the command
  389. * @cmd: Command to send
  390. * @data: Additional data to send/receive
  391. * @return 0 if OK, -ve on error
  392. */
  393. int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
  394. struct mmc_data *data);
  395. /**
  396. * set_ios() - Set the I/O speed/width for an MMC device
  397. *
  398. * @dev: Device to update
  399. * @return 0 if OK, -ve on error
  400. */
  401. int (*set_ios)(struct udevice *dev);
  402. /**
  403. * get_cd() - See whether a card is present
  404. *
  405. * @dev: Device to check
  406. * @return 0 if not present, 1 if present, -ve on error
  407. */
  408. int (*get_cd)(struct udevice *dev);
  409. /**
  410. * get_wp() - See whether a card has write-protect enabled
  411. *
  412. * @dev: Device to check
  413. * @return 0 if write-enabled, 1 if write-protected, -ve on error
  414. */
  415. int (*get_wp)(struct udevice *dev);
  416. #ifdef MMC_SUPPORTS_TUNING
  417. /**
  418. * execute_tuning() - Start the tuning process
  419. *
  420. * @dev: Device to start the tuning
  421. * @opcode: Command opcode to send
  422. * @return 0 if OK, -ve on error
  423. */
  424. int (*execute_tuning)(struct udevice *dev, uint opcode);
  425. #endif
  426. /**
  427. * wait_dat0() - wait until dat0 is in the target state
  428. * (CLK must be running during the wait)
  429. *
  430. * @dev: Device to check
  431. * @state: target state
  432. * @timeout_us: timeout in us
  433. * @return 0 if dat0 is in the target state, -ve on error
  434. */
  435. int (*wait_dat0)(struct udevice *dev, int state, int timeout_us);
  436. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  437. /* set_enhanced_strobe() - set HS400 enhanced strobe */
  438. int (*set_enhanced_strobe)(struct udevice *dev);
  439. #endif
  440. /**
  441. * host_power_cycle - host specific tasks in power cycle sequence
  442. * Called between mmc_power_off() and
  443. * mmc_power_on()
  444. *
  445. * @dev: Device to check
  446. * @return 0 if not present, 1 if present, -ve on error
  447. */
  448. int (*host_power_cycle)(struct udevice *dev);
  449. /**
  450. * get_b_max - get maximum length of single transfer
  451. * Called before reading blocks from the card,
  452. * useful for system which have e.g. DMA limits
  453. * on various memory ranges.
  454. *
  455. * @dev: Device to check
  456. * @dst: Destination buffer in memory
  457. * @blkcnt: Total number of blocks in this transfer
  458. * @return maximum number of blocks for this transfer
  459. */
  460. int (*get_b_max)(struct udevice *dev, void *dst, lbaint_t blkcnt);
  461. /**
  462. * hs400_prepare_ddr - prepare to switch to DDR mode
  463. *
  464. * @dev: Device to check
  465. * @return 0 if success, -ve on error
  466. */
  467. int (*hs400_prepare_ddr)(struct udevice *dev);
  468. };
  469. #define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops)
  470. /* Transition functions for compatibility */
  471. int mmc_set_ios(struct mmc *mmc);
  472. int mmc_getcd(struct mmc *mmc);
  473. int mmc_getwp(struct mmc *mmc);
  474. int mmc_execute_tuning(struct mmc *mmc, uint opcode);
  475. int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us);
  476. int mmc_set_enhanced_strobe(struct mmc *mmc);
  477. int mmc_host_power_cycle(struct mmc *mmc);
  478. int mmc_deferred_probe(struct mmc *mmc);
  479. int mmc_reinit(struct mmc *mmc);
  480. int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt);
  481. int mmc_hs400_prepare_ddr(struct mmc *mmc);
  482. int mmc_send_stop_transmission(struct mmc *mmc, bool write);
  483. #else
  484. struct mmc_ops {
  485. int (*send_cmd)(struct mmc *mmc,
  486. struct mmc_cmd *cmd, struct mmc_data *data);
  487. int (*set_ios)(struct mmc *mmc);
  488. int (*init)(struct mmc *mmc);
  489. int (*getcd)(struct mmc *mmc);
  490. int (*getwp)(struct mmc *mmc);
  491. int (*host_power_cycle)(struct mmc *mmc);
  492. int (*get_b_max)(struct mmc *mmc, void *dst, lbaint_t blkcnt);
  493. int (*wait_dat0)(struct mmc *mmc, int state, int timeout_us);
  494. };
  495. static inline int mmc_hs400_prepare_ddr(struct mmc *mmc)
  496. {
  497. return 0;
  498. }
  499. #endif
  500. struct mmc_config {
  501. const char *name;
  502. #if !CONFIG_IS_ENABLED(DM_MMC)
  503. const struct mmc_ops *ops;
  504. #endif
  505. uint host_caps;
  506. uint voltages;
  507. uint f_min;
  508. uint f_max;
  509. uint b_max;
  510. unsigned char part_type;
  511. #ifdef CONFIG_MMC_PWRSEQ
  512. struct udevice *pwr_dev;
  513. #endif
  514. };
  515. struct sd_ssr {
  516. unsigned int au; /* In sectors */
  517. unsigned int erase_timeout; /* In milliseconds */
  518. unsigned int erase_offset; /* In milliseconds */
  519. };
  520. enum bus_mode {
  521. MMC_LEGACY,
  522. MMC_HS,
  523. SD_HS,
  524. MMC_HS_52,
  525. MMC_DDR_52,
  526. UHS_SDR12,
  527. UHS_SDR25,
  528. UHS_SDR50,
  529. UHS_DDR50,
  530. UHS_SDR104,
  531. MMC_HS_200,
  532. MMC_HS_400,
  533. MMC_HS_400_ES,
  534. MMC_MODES_END
  535. };
  536. const char *mmc_mode_name(enum bus_mode mode);
  537. void mmc_dump_capabilities(const char *text, uint caps);
  538. static inline bool mmc_is_mode_ddr(enum bus_mode mode)
  539. {
  540. if (mode == MMC_DDR_52)
  541. return true;
  542. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  543. else if (mode == UHS_DDR50)
  544. return true;
  545. #endif
  546. #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  547. else if (mode == MMC_HS_400)
  548. return true;
  549. #endif
  550. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  551. else if (mode == MMC_HS_400_ES)
  552. return true;
  553. #endif
  554. else
  555. return false;
  556. }
  557. #define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
  558. MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
  559. MMC_CAP(UHS_DDR50))
  560. static inline bool supports_uhs(uint caps)
  561. {
  562. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  563. return (caps & UHS_CAPS) ? true : false;
  564. #else
  565. return false;
  566. #endif
  567. }
  568. /*
  569. * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
  570. * with mmc_get_mmc_dev().
  571. *
  572. * TODO struct mmc should be in mmc_private but it's hard to fix right now
  573. */
  574. struct mmc {
  575. #if !CONFIG_IS_ENABLED(BLK)
  576. struct list_head link;
  577. #endif
  578. const struct mmc_config *cfg; /* provided configuration */
  579. uint version;
  580. void *priv;
  581. uint has_init;
  582. int high_capacity;
  583. bool clk_disable; /* true if the clock can be turned off */
  584. uint bus_width;
  585. uint clock;
  586. uint saved_clock;
  587. enum mmc_voltage signal_voltage;
  588. uint card_caps;
  589. uint host_caps;
  590. uint ocr;
  591. uint dsr;
  592. uint dsr_imp;
  593. uint scr[2];
  594. uint csd[4];
  595. uint cid[4];
  596. ushort rca;
  597. u8 part_support;
  598. u8 part_attr;
  599. u8 wr_rel_set;
  600. u8 part_config;
  601. u8 gen_cmd6_time; /* units: 10 ms */
  602. u8 part_switch_time; /* units: 10 ms */
  603. uint tran_speed;
  604. uint legacy_speed; /* speed for the legacy mode provided by the card */
  605. uint read_bl_len;
  606. bool can_trim;
  607. #if CONFIG_IS_ENABLED(MMC_WRITE)
  608. uint write_bl_len;
  609. uint erase_grp_size; /* in 512-byte sectors */
  610. #endif
  611. #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
  612. uint hc_wp_grp_size; /* in 512-byte sectors */
  613. #endif
  614. #if CONFIG_IS_ENABLED(MMC_WRITE)
  615. struct sd_ssr ssr; /* SD status register */
  616. #endif
  617. u64 capacity;
  618. u64 capacity_user;
  619. u64 capacity_boot;
  620. u64 capacity_rpmb;
  621. u64 capacity_gp[4];
  622. #ifndef CONFIG_SPL_BUILD
  623. u64 enh_user_start;
  624. u64 enh_user_size;
  625. #endif
  626. #if !CONFIG_IS_ENABLED(BLK)
  627. struct blk_desc block_dev;
  628. #endif
  629. char op_cond_pending; /* 1 if we are waiting on an op_cond command */
  630. char init_in_progress; /* 1 if we have done mmc_start_init() */
  631. char preinit; /* start init as early as possible */
  632. int ddr_mode;
  633. #if CONFIG_IS_ENABLED(DM_MMC)
  634. struct udevice *dev; /* Device for this MMC controller */
  635. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  636. struct udevice *vmmc_supply; /* Main voltage regulator (Vcc)*/
  637. struct udevice *vqmmc_supply; /* IO voltage regulator (Vccq)*/
  638. #endif
  639. #endif
  640. u8 *ext_csd;
  641. u32 cardtype; /* cardtype read from the MMC */
  642. enum mmc_voltage current_voltage;
  643. enum bus_mode selected_mode; /* mode currently used */
  644. enum bus_mode best_mode; /* best mode is the supported mode with the
  645. * highest bandwidth. It may not always be the
  646. * operating mode due to limitations when
  647. * accessing the boot partitions
  648. */
  649. u32 quirks;
  650. u8 hs400_tuning;
  651. enum bus_mode user_speed_mode; /* input speed mode from user */
  652. };
  653. #if CONFIG_IS_ENABLED(DM_MMC)
  654. #define mmc_to_dev(_mmc) _mmc->dev
  655. #else
  656. #define mmc_to_dev(_mmc) NULL
  657. #endif
  658. struct mmc_hwpart_conf {
  659. struct {
  660. uint enh_start; /* in 512-byte sectors */
  661. uint enh_size; /* in 512-byte sectors, if 0 no enh area */
  662. unsigned wr_rel_change : 1;
  663. unsigned wr_rel_set : 1;
  664. } user;
  665. struct {
  666. uint size; /* in 512-byte sectors */
  667. unsigned enhanced : 1;
  668. unsigned wr_rel_change : 1;
  669. unsigned wr_rel_set : 1;
  670. } gp_part[4];
  671. };
  672. enum mmc_hwpart_conf_mode {
  673. MMC_HWPART_CONF_CHECK,
  674. MMC_HWPART_CONF_SET,
  675. MMC_HWPART_CONF_COMPLETE,
  676. };
  677. struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
  678. /**
  679. * mmc_bind() - Set up a new MMC device ready for probing
  680. *
  681. * A child block device is bound with the UCLASS_MMC interface type. This
  682. * allows the device to be used with CONFIG_BLK
  683. *
  684. * @dev: MMC device to set up
  685. * @mmc: MMC struct
  686. * @cfg: MMC configuration
  687. * Return: 0 if OK, -ve on error
  688. */
  689. int mmc_bind(struct udevice *dev, struct mmc *mmc,
  690. const struct mmc_config *cfg);
  691. void mmc_destroy(struct mmc *mmc);
  692. /**
  693. * mmc_unbind() - Unbind a MMC device's child block device
  694. *
  695. * @dev: MMC device
  696. * Return: 0 if OK, -ve on error
  697. */
  698. int mmc_unbind(struct udevice *dev);
  699. int mmc_initialize(struct bd_info *bis);
  700. int mmc_init_device(int num);
  701. int mmc_init(struct mmc *mmc);
  702. int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
  703. int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data);
  704. int mmc_deinit(struct mmc *mmc);
  705. /**
  706. * mmc_of_parse() - Parse the device tree to get the capabilities of the host
  707. *
  708. * @dev: MMC device
  709. * @cfg: MMC configuration
  710. * Return: 0 if OK, -ve on error
  711. */
  712. int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg);
  713. #ifdef CONFIG_MMC_PWRSEQ
  714. /**
  715. * mmc_pwrseq_get_power() - get a power device from device tree
  716. *
  717. * @dev: MMC device
  718. * @cfg: MMC configuration
  719. * Return: 0 if OK, -ve on error
  720. */
  721. int mmc_pwrseq_get_power(struct udevice *dev, struct mmc_config *cfg);
  722. #endif
  723. int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
  724. /**
  725. * mmc_voltage_to_mv() - Convert a mmc_voltage in mV
  726. *
  727. * @voltage: The mmc_voltage to convert
  728. * Return: the value in mV if OK, -EINVAL on error (invalid mmc_voltage value)
  729. */
  730. int mmc_voltage_to_mv(enum mmc_voltage voltage);
  731. /**
  732. * mmc_set_clock() - change the bus clock
  733. * @mmc: MMC struct
  734. * @clock: bus frequency in Hz
  735. * @disable: flag indicating if the clock must on or off
  736. * Return: 0 if OK, -ve on error
  737. */
  738. int mmc_set_clock(struct mmc *mmc, uint clock, bool disable);
  739. #define MMC_CLK_ENABLE false
  740. #define MMC_CLK_DISABLE true
  741. struct mmc *find_mmc_device(int dev_num);
  742. int mmc_set_dev(int dev_num);
  743. void print_mmc_devices(char separator);
  744. /**
  745. * get_mmc_num() - get the total MMC device number
  746. *
  747. * Return: 0 if there is no MMC device, else the number of devices
  748. */
  749. int get_mmc_num(void);
  750. int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
  751. int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
  752. enum mmc_hwpart_conf_mode mode);
  753. #if !CONFIG_IS_ENABLED(DM_MMC)
  754. int mmc_getcd(struct mmc *mmc);
  755. int board_mmc_getcd(struct mmc *mmc);
  756. int mmc_getwp(struct mmc *mmc);
  757. int board_mmc_getwp(struct mmc *mmc);
  758. #endif
  759. int mmc_set_dsr(struct mmc *mmc, u16 val);
  760. /* Function to change the size of boot partition and rpmb partitions */
  761. int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
  762. unsigned long rpmbsize);
  763. /* Function to modify the PARTITION_CONFIG field of EXT_CSD */
  764. int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
  765. /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
  766. int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
  767. /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
  768. int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
  769. /* Functions to read / write the RPMB partition */
  770. int mmc_rpmb_set_key(struct mmc *mmc, void *key);
  771. int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
  772. int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
  773. unsigned short cnt, unsigned char *key);
  774. int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
  775. unsigned short cnt, unsigned char *key);
  776. /**
  777. * mmc_rpmb_route_frames() - route RPMB data frames
  778. * @mmc Pointer to a MMC device struct
  779. * @req Request data frames
  780. * @reqlen Length of data frames in bytes
  781. * @rsp Supplied buffer for response data frames
  782. * @rsplen Length of supplied buffer for response data frames
  783. *
  784. * The RPMB data frames are routed to/from some external entity, for
  785. * example a Trusted Exectuion Environment in an arm TrustZone protected
  786. * secure world. It's expected that it's the external entity who is in
  787. * control of the RPMB key.
  788. *
  789. * Returns 0 on success, < 0 on error.
  790. */
  791. int mmc_rpmb_route_frames(struct mmc *mmc, void *req, unsigned long reqlen,
  792. void *rsp, unsigned long rsplen);
  793. /**
  794. * mmc_set_bkops_enable() - enable background operations
  795. * @param mmc Pointer to a MMC device struct
  796. * @param autobkops Enable automatic bkops, not manual bkops
  797. * @param enable Enable bkops, not disable
  798. *
  799. * Enable or disable automatic or manual background operation of the eMMC.
  800. *
  801. * Return: 0 on success, <0 on error.
  802. */
  803. int mmc_set_bkops_enable(struct mmc *mmc, bool autobkops, bool enable);
  804. /**
  805. * Start device initialization and return immediately; it does not block on
  806. * polling OCR (operation condition register) status. Useful for checking
  807. * the presence of SD/eMMC when no card detect logic is available.
  808. *
  809. * @param mmc Pointer to a MMC device struct
  810. * @param quiet Be quiet, do not print error messages when card is not detected.
  811. * Return: 0 on success, <0 on error.
  812. */
  813. int mmc_get_op_cond(struct mmc *mmc, bool quiet);
  814. /**
  815. * Start device initialization and return immediately; it does not block on
  816. * polling OCR (operation condition register) status. Then you should call
  817. * mmc_init, which would block on polling OCR status and complete the device
  818. * initializatin.
  819. *
  820. * @param mmc Pointer to a MMC device struct
  821. * Return: 0 on success, <0 on error.
  822. */
  823. int mmc_start_init(struct mmc *mmc);
  824. /**
  825. * Set preinit flag of mmc device.
  826. *
  827. * This will cause the device to be pre-inited during mmc_initialize(),
  828. * which may save boot time if the device is not accessed until later.
  829. * Some eMMC devices take 200-300ms to init, but unfortunately they
  830. * must be sent a series of commands to even get them to start preparing
  831. * for operation.
  832. *
  833. * @param mmc Pointer to a MMC device struct
  834. * @param preinit preinit flag value
  835. */
  836. void mmc_set_preinit(struct mmc *mmc, int preinit);
  837. #ifdef CONFIG_MMC_SPI
  838. #define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
  839. #else
  840. #define mmc_host_is_spi(mmc) 0
  841. #endif
  842. #define mmc_dev(x) ((x)->dev)
  843. void board_mmc_power_init(void);
  844. int board_mmc_init(struct bd_info *bis);
  845. int cpu_mmc_init(struct bd_info *bis);
  846. int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
  847. # ifdef CONFIG_SYS_MMC_ENV_PART
  848. extern uint mmc_get_env_part(struct mmc *mmc);
  849. # endif
  850. int mmc_get_env_dev(void);
  851. /* Minimum partition switch timeout in units of 10-milliseconds */
  852. #define MMC_MIN_PART_SWITCH_TIME 30 /* 300 ms */
  853. /**
  854. * mmc_get_blk_desc() - Get the block descriptor for an MMC device
  855. *
  856. * @mmc: MMC device
  857. * Return: block descriptor if found, else NULL
  858. */
  859. struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
  860. /**
  861. * mmc_get_blk() - Get the block device for an MMC device
  862. *
  863. * @dev: MMC device
  864. * @blkp: Returns pointer to probed block device on sucesss
  865. *
  866. * Return: 0 on success, -ve on error
  867. */
  868. int mmc_get_blk(struct udevice *dev, struct udevice **blkp);
  869. /**
  870. * mmc_send_ext_csd() - read the extended CSD register
  871. *
  872. * @mmc: MMC device
  873. * @ext_csd a cache aligned buffer of length MMC_MAX_BLOCK_LEN allocated by
  874. * the caller, e.g. using
  875. * ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN)
  876. * Return: 0 for success
  877. */
  878. int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd);
  879. /**
  880. * mmc_boot_wp() - power on write protect boot partitions
  881. *
  882. * The boot partitions are write protected until the next power cycle.
  883. *
  884. * Return: 0 for success
  885. */
  886. int mmc_boot_wp(struct mmc *mmc);
  887. /**
  888. * mmc_boot_wp_single_partition() - set write protection to a boot partition.
  889. *
  890. * This function sets a single boot partition to protect and leave the
  891. * other partition writable.
  892. *
  893. * @param mmc the mmc device.
  894. * @param partition 0 - first boot partition, 1 - second boot partition.
  895. * @return 0 for success
  896. */
  897. int mmc_boot_wp_single_partition(struct mmc *mmc, int partition);
  898. static inline enum dma_data_direction mmc_get_dma_dir(struct mmc_data *data)
  899. {
  900. return data->flags & MMC_DATA_WRITE ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
  901. }
  902. #endif /* _MMC_H_ */