fsl_ddr.h 4.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright 2008-2014 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef FSL_DDR_MAIN_H
  6. #define FSL_DDR_MAIN_H
  7. #include <fsl_ddrc_version.h>
  8. #include <fsl_ddr_sdram.h>
  9. #include <fsl_ddr_dimm_params.h>
  10. #include <common_timing_params.h>
  11. struct cmd_tbl;
  12. #ifdef CONFIG_SYS_FSL_DDR_LE
  13. #define ddr_in32(a) in_le32(a)
  14. #define ddr_out32(a, v) out_le32(a, v)
  15. #define ddr_setbits32(a, v) setbits_le32(a, v)
  16. #define ddr_clrbits32(a, v) clrbits_le32(a, v)
  17. #define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set)
  18. #else
  19. #define ddr_in32(a) in_be32(a)
  20. #define ddr_out32(a, v) out_be32(a, v)
  21. #define ddr_setbits32(a, v) setbits_be32(a, v)
  22. #define ddr_clrbits32(a, v) clrbits_be32(a, v)
  23. #define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set)
  24. #endif
  25. u32 fsl_ddr_get_version(unsigned int ctrl_num);
  26. #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
  27. /*
  28. * Bind the main DDR setup driver's generic names
  29. * to this specific DDR technology.
  30. */
  31. static __inline__ int
  32. compute_dimm_parameters(const unsigned int ctrl_num,
  33. const generic_spd_eeprom_t *spd,
  34. dimm_params_t *pdimm,
  35. unsigned int dimm_number)
  36. {
  37. return ddr_compute_dimm_parameters(ctrl_num, spd, pdimm, dimm_number);
  38. }
  39. #endif
  40. /*
  41. * Data Structures
  42. *
  43. * All data structures have to be on the stack
  44. */
  45. typedef struct {
  46. generic_spd_eeprom_t
  47. spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
  48. struct dimm_params_s
  49. dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
  50. memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
  51. common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
  52. fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
  53. unsigned int first_ctrl;
  54. unsigned int num_ctrls;
  55. unsigned long long mem_base;
  56. unsigned int dimm_slots_per_ctrl;
  57. int (*board_need_mem_reset)(void);
  58. void (*board_mem_reset)(void);
  59. void (*board_mem_de_reset)(void);
  60. } fsl_ddr_info_t;
  61. /* Compute steps */
  62. #define STEP_GET_SPD (1 << 0)
  63. #define STEP_COMPUTE_DIMM_PARMS (1 << 1)
  64. #define STEP_COMPUTE_COMMON_PARMS (1 << 2)
  65. #define STEP_GATHER_OPTS (1 << 3)
  66. #define STEP_ASSIGN_ADDRESSES (1 << 4)
  67. #define STEP_COMPUTE_REGS (1 << 5)
  68. #define STEP_PROGRAM_REGS (1 << 6)
  69. #define STEP_ALL 0xFFF
  70. unsigned long long
  71. fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
  72. unsigned int size_only);
  73. const char *step_to_string(unsigned int step);
  74. unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
  75. const memctl_options_t *popts,
  76. fsl_ddr_cfg_regs_t *ddr,
  77. const common_timing_params_t *common_dimm,
  78. const dimm_params_t *dimm_parameters,
  79. unsigned int dbw_capacity_adjust,
  80. unsigned int size_only);
  81. unsigned int compute_lowest_common_dimm_parameters(
  82. const unsigned int ctrl_num,
  83. const dimm_params_t *dimm_params,
  84. common_timing_params_t *outpdimm,
  85. unsigned int number_of_dimms);
  86. unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
  87. memctl_options_t *popts,
  88. dimm_params_t *pdimm,
  89. unsigned int ctrl_num);
  90. void check_interleaving_options(fsl_ddr_info_t *pinfo);
  91. unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk);
  92. unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num);
  93. unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos);
  94. void fsl_ddr_set_lawbar(
  95. const common_timing_params_t *memctl_common_params,
  96. unsigned int memctl_interleaved,
  97. unsigned int ctrl_num);
  98. void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
  99. unsigned int last_ctrl);
  100. int fsl_ddr_interactive_env_var_exists(void);
  101. unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
  102. void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
  103. unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
  104. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
  105. unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
  106. void board_add_ram_info(int use_default);
  107. /* processor specific function */
  108. void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  109. unsigned int ctrl_num, int step);
  110. void remove_unused_controllers(fsl_ddr_info_t *info);
  111. /* board specific function */
  112. int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  113. unsigned int controller_number,
  114. unsigned int dimm_number);
  115. void update_spd_address(unsigned int ctrl_num,
  116. unsigned int slot,
  117. unsigned int *addr);
  118. void erratum_a009942_check_cpo(void);
  119. #endif