README.socfpga 6.1 KB

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  1. ----------------------------------------
  2. SOCFPGA Documentation for U-Boot and SPL
  3. ----------------------------------------
  4. This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore
  5. based SOCFPGA. To know more about the hardware itself, please refer to
  6. www.altera.com.
  7. ---------------------------------------------------------------------
  8. Cyclone 5 / Arria 5 generating the handoff header files for U-Boot SPL
  9. ---------------------------------------------------------------------
  10. This text is assuming quartus 16.1, but newer versions will probably work just fine too;
  11. verified with DE1_SOC_Linux_FB demo project (https://github.com/VCTLabs/DE1_SOC_Linux_FB).
  12. Updated/working projects should build using either process below.
  13. Note: it *should* work from Quartus 14.0.200 onwards, however, the current vendor demo
  14. projects must have the IP cores updated as shown below.
  15. Rebuilding your Quartus project
  16. -------------------------------
  17. Choose one of the follwing methods, either command line or GUI.
  18. Using the command line
  19. ~~~~~~~~~~~~~~~~~~~~~~
  20. First run the embedded command shell, using your path to the Quartus install:
  21. $ /path/to/intelFPGA/16.1/embedded/embedded_command_shell.sh
  22. Then (if necessary) update the IP cores in the project, generate HDL code, and
  23. build the project:
  24. $ cd path/to/project/dir
  25. $ qsys-generate soc_system.qsys --upgrade-ip-cores
  26. $ qsys-generate soc_system.qsys --synthesis=[VERILOG|VHDL]
  27. $ quartus_sh --flow compile <project name>
  28. Convert the resulting .sof file (SRAM object file) to .rbf file (Raw bit file):
  29. $ quartus_cpf -c <project_name>.sof soc_system.rbf
  30. Generate BSP handoff files
  31. ~~~~~~~~~~~~~~~~~~~~~~~~~~
  32. You can run the bsp editor GUI below, or run the following command from the
  33. project directory:
  34. $ /path/to/bsb/tools/bsp-create-settings --type spl --bsp-dir build \
  35. --preloader-settings-dir hps_isw_handoff/soc_system_hps_0/ \
  36. --settings build/settings.bsp
  37. You should use the bsp "build" directory above (ie, where the settings.bsp file is)
  38. in the following u-boot command to update the board headers. Once these headers
  39. are updated for a given project build, u-boot should be configured for the
  40. project board (eg, de0-nano-sockit) and then build the normal spl build.
  41. Now you can skip the GUI section.
  42. Using the Qsys GUI
  43. ~~~~~~~~~~~~~~~~~~
  44. 1. Navigate to your project directory
  45. 2. Run Quartus II
  46. 3. Open Project (Ctrl+J), select <project_name>.qpf
  47. 4. Run QSys [Tools->QSys]
  48. 4.1 In the Open dialog, select '<project_name>.qsys'
  49. 4.2 In the Open System dialog, wait until completion and press 'Close'
  50. 4.3 In the Qsys window, click on 'Generate HDL...' in bottom right corner
  51. 4.3.1 In the 'Generation' window, click 'Generate'
  52. 4.3.2 In the 'Generate' dialog, wait until completion and click 'Close'
  53. 4.4 In the QSys window, click 'Finish'
  54. 4.4.1 In the 'Quartus II' pop up window, click 'OK'
  55. 5. Back in Quartus II main window, do the following
  56. 5.1 Use Processing -> Start -> Start Analysis & Synthesis (Ctrl+K)
  57. 5.2 Use Processing -> Start Compilation (Ctrl+L)
  58. ... this may take some time, have patience ...
  59. 6. Start the embedded command shell as shown in the previous section
  60. 6.1 Change directory to 'software/spl_bsp'
  61. 6.2 Prepare BSP by launching the BSP editor from ECS
  62. => bsp-editor
  63. 6.3 In BSP editor
  64. 6.3.1 Use File -> Open
  65. 6.3.2 Select 'settings.bsp' file
  66. 6.3.3 Click Generate
  67. 6.3.4 Click Exit
  68. Post handoff generation
  69. ~~~~~~~~~~~~~~~~~~~~~~~
  70. Now that the handoff files are generated, U-Boot can be used to process
  71. the handoff files generated by the bsp-editor. For this, please use the
  72. following script from the u-boot source tree:
  73. $ ./arch/arm/mach-socfpga/qts-filter.sh \
  74. <soc_type> \
  75. <input_qts_dir> \
  76. <input_bsp_dir> \
  77. <output_dir>
  78. Process QTS-generated files into U-Boot compatible ones.
  79. soc_type - Type of SoC, either 'cyclone5' or 'arria5'.
  80. input_qts_dir - Directory with compiled Quartus project
  81. and containing the Quartus project file (QPF).
  82. input_bsp_dir - Directory with generated bsp containing
  83. the settings.bsp file.
  84. output_dir - Directory to store the U-Boot compatible
  85. headers.
  86. This will generate (or update) the following 4 files:
  87. iocsr_config.h
  88. pinmux_config.h
  89. pll_config.h
  90. sdram_config.h
  91. These files should be copied into "qts" directory in the board directory
  92. (see output argument of qts-filter.sh command above).
  93. Here is an example for the DE-0 Nano SoC after the above rebuild process:
  94. $ ll board/terasic/de0-nano-soc/qts/
  95. total 36
  96. -rw-r--r-- 1 sarnold sarnold 8826 Mar 21 18:11 iocsr_config.h
  97. -rw-r--r-- 1 sarnold sarnold 4398 Mar 21 18:11 pinmux_config.h
  98. -rw-r--r-- 1 sarnold sarnold 3190 Mar 21 18:11 pll_config.h
  99. -rw-r--r-- 1 sarnold sarnold 9022 Mar 21 18:11 sdram_config.h
  100. Note: file sizes will differ slightly depending on the selected board.
  101. Now your board is ready for full mainline support including U-Boot SPL.
  102. The Preloader will not be needed any more.
  103. ----------------------------------------------------------
  104. Arria 10 generating the handoff header files for U-Boot SPL
  105. ----------------------------------------------------------
  106. A header file for inclusion in a devicetree for Arria10 can be generated
  107. by the qts-filter-a10.sh script directly from the hps_isw_handoff/hps.xml
  108. file generated during the FPGA project compilation. The header contains
  109. all PLL, clock, pinmux, and bridge configurations required.
  110. Please look at the socfpga_arria10_socdk_sdmmc-u-boot.dtsi for an example
  111. that includes use of the generated handoff header.
  112. Devicetree header generation
  113. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  114. The qts-filter-a10.sh script can process the compile time genetated hps.xml
  115. to create the appropriate devicetree header.
  116. $ ./arch/arm/mach-socfpga/qts-filter-a10.sh \
  117. <hps_xml> \
  118. <output_file>
  119. hps_xml - hps_isw_handoff/hps.xml from Quartus project
  120. output_file - Output filename and location for header file
  121. The script generates a single header file names <output_file> that should
  122. be placed in arch/arm/dts.