Kconfig.nxp 7.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298
  1. menu "Functionality shared between NXP SoCs"
  2. config FSL_TRUST_ARCH_v1
  3. bool
  4. config NXP_ESBC
  5. bool "NXP ESBC (secure boot) functionality"
  6. select FSL_TRUST_ARCH_v1 if ARCH_P3041 || ARCH_P4080 || \
  7. ARCH_P5040 || ARCH_P2041
  8. help
  9. Enable Freescale Secure Boot feature. Normally selected by defconfig.
  10. If unsure, do not change.
  11. menu "Chain of trust / secure boot options"
  12. depends on !FIT_SIGNATURE && NXP_ESBC
  13. config CHAIN_OF_TRUST
  14. select FSL_CAAM
  15. select ARCH_MISC_INIT
  16. select FSL_ISBC_KEY_EXT if (ARM || FSL_CORENET) && !SYS_RAMBOOT
  17. select FSL_SEC_MON
  18. select SPL_BOARD_INIT if (ARM && SPL)
  19. select SPL_HASH if (ARM && SPL)
  20. select SHA_HW_ACCEL
  21. select SHA_PROG_HW_ACCEL
  22. select ENV_IS_NOWHERE
  23. select SYS_CPC_REINIT_F if MPC85xx && !SYS_RAMBOOT
  24. select CMD_EXT4 if ARM
  25. select CMD_EXT4_WRITE if ARM
  26. imply CMD_BLOB
  27. imply CMD_HASH if ARM
  28. def_bool y
  29. config CMD_ESBC_VALIDATE
  30. bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
  31. default y
  32. help
  33. This option enables two commands used for secure booting:
  34. esbc_validate - validate signature using RSA verification
  35. esbc_halt - put the core in spin loop (Secure Boot Only)
  36. config ESBC_HDR_LS
  37. bool
  38. config ESBC_ADDR_64BIT
  39. def_bool y
  40. depends on FSL_LAYERSCAPE
  41. help
  42. For Layerscape based platforms, ESBC image Address in Header is 64bit.
  43. config FSL_ISBC_KEY_EXT
  44. bool
  45. help
  46. The key used for verification of next level images is picked up from
  47. an Extension Table which has been verified by the ISBC (Internal
  48. Secure boot Code) in boot ROM of the SoC. The feature is only
  49. applicable in case of NOR boot and is not applicable in case of
  50. RAMBOOT (NAND, SD, SPI). For Layerscape, this feature is available
  51. for all device if IE Table is copied to XIP memory Also, for
  52. Layerscape, ISBC doesn't verify this table.
  53. config SYS_FSL_SFP_BE
  54. def_bool y
  55. depends on PPC || FSL_LSCH2 || ARCH_LS1021A
  56. config SYS_FSL_SFP_LE
  57. def_bool y
  58. depends on !SYS_FSL_SFP_BE
  59. choice
  60. prompt "SFP IP revision"
  61. default SYS_FSL_SFP_VER_3_0 if PPC
  62. default SYS_FSL_SFP_VER_3_4
  63. config SYS_FSL_SFP_VER_3_0
  64. bool "SFP version 3.0"
  65. config SYS_FSL_SFP_VER_3_2
  66. bool "SFP version 3.2"
  67. config SYS_FSL_SFP_VER_3_4
  68. bool "SFP version 3.4"
  69. endchoice
  70. config SPL_UBOOT_KEY_HASH
  71. string "Non-SRK key hash for U-Boot public/private key pair"
  72. depends on SPL
  73. default ""
  74. help
  75. Set the key hash for U-Boot here if public/private key pair used to
  76. sign U-Boot are different from the SRK hash put in the fuse. Example
  77. of a key hash is
  78. 41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
  79. Otherwise leave this empty.
  80. if PPC
  81. config BOOTSCRIPT_COPY_RAM
  82. bool "Secure boot copies boot script to RAM"
  83. help
  84. On systems that support chain of trust booting, a number of addresses
  85. are required to set variables that are used in the copying and then
  86. verification of different parts of the system. If enabled, the subsequent
  87. options are for what location to use in each step.
  88. config BS_ADDR_DEVICE
  89. hex "Address in RAM for bs_device"
  90. depends on BOOTSCRIPT_COPY_RAM
  91. config BS_SIZE
  92. hex "The size of bs_size which is the amount read from bs_device"
  93. depends on BOOTSCRIPT_COPY_RAM
  94. config BS_ADDR_RAM
  95. hex "Address in RAM for bs_ram"
  96. depends on BOOTSCRIPT_COPY_RAM
  97. config BS_HDR_ADDR_DEVICE
  98. hex "Address in RAM for bs_hdr_device"
  99. depends on BOOTSCRIPT_COPY_RAM
  100. config BS_HDR_SIZE
  101. hex "The size of bs_hdr_size which is the amount read from bs_hdr_device"
  102. depends on BOOTSCRIPT_COPY_RAM
  103. config BS_HDR_ADDR_RAM
  104. hex "Address in RAM for bs_hdr_ram"
  105. depends on BOOTSCRIPT_COPY_RAM
  106. config BOOTSCRIPT_HDR_ADDR
  107. hex "CONFIG_BOOTSCRIPT_HDR_ADDR"
  108. default BS_ADDR_RAM if BOOTSCRIPT_COPY_RAM
  109. endif
  110. config SYS_FSL_SRK_LE
  111. def_bool y
  112. depends on ARM
  113. config KEY_REVOCATION
  114. def_bool y
  115. endmenu
  116. config DEEP_SLEEP
  117. bool "Enable SoC deep sleep feature"
  118. depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A
  119. default y
  120. help
  121. Indicates this SoC supports deep sleep feature. If deep sleep is
  122. supported, core will start to execute uboot when wakes up.
  123. config LAYERSCAPE_NS_ACCESS
  124. bool "Layerscape non-secure access support"
  125. depends on ARCH_LS1021A || FSL_LSCH2
  126. config PCIE1
  127. bool "PCIe controller #1"
  128. depends on LAYERSCAPE_NS_ACCESS || PPC
  129. config PCIE2
  130. bool "PCIe controller #2"
  131. depends on LAYERSCAPE_NS_ACCESS || PPC
  132. config PCIE3
  133. bool "PCIe controller #3"
  134. depends on LAYERSCAPE_NS_ACCESS || PPC
  135. config PCIE4
  136. bool "PCIe controller #4"
  137. depends on LAYERSCAPE_NS_ACCESS || PPC
  138. config FSL_USE_PCA9547_MUX
  139. bool "Enable PCA9547 I2C Mux on Freescale boards"
  140. depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
  141. help
  142. This option enables the PCA9547 I2C mux on Freescale boards.
  143. config VID
  144. bool "Enable Freescale VID"
  145. depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (I2C || DM_I2C)
  146. help
  147. This option enables setting core voltage based on individual
  148. values saved in SoC fuses.
  149. config SPL_VID
  150. bool "Enable Freescale VID in SPL"
  151. depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (SPL_I2C || DM_SPL_I2C)
  152. help
  153. This option enables setting core voltage based on individual
  154. values saved in SoC fuses, in SPL.
  155. if VID || SPL_VID
  156. config VID_FLS_ENV
  157. string "Environment variable for overriding VDD"
  158. help
  159. This option allows for specifying the environment variable
  160. to check to override VDD information.
  161. config VOL_MONITOR_INA220
  162. bool "Enable the INA220 voltage monitor read"
  163. help
  164. This option enables INA220 voltage monitor read
  165. functionality. It is used by the common VID driver.
  166. config VOL_MONITOR_IR36021_READ
  167. bool "Enable the IR36021 voltage monitor read"
  168. help
  169. This option enables IR36021 voltage monitor read
  170. functionality. It is used by the common VID driver.
  171. config VOL_MONITOR_IR36021_SET
  172. bool "Enable the IR36021 voltage monitor set"
  173. help
  174. This option enables IR36021 voltage monitor set
  175. functionality. It is used by the common VID driver.
  176. config VOL_MONITOR_LTC3882_READ
  177. bool "Enable the LTC3882 voltage monitor read"
  178. help
  179. This option enables LTC3882 voltage monitor read
  180. functionality. It is used by the common VID driver.
  181. config VOL_MONITOR_LTC3882_SET
  182. bool "Enable the LTC3882 voltage monitor set"
  183. help
  184. This option enables LTC3882 voltage monitor set
  185. functionality. It is used by the common VID driver.
  186. config VOL_MONITOR_ISL68233_READ
  187. bool "Enable the ISL68233 voltage monitor read"
  188. help
  189. This option enables ISL68233 voltage monitor read
  190. functionality. It is used by the common VID driver.
  191. config VOL_MONITOR_ISL68233_SET
  192. bool "Enable the ISL68233 voltage monitor set"
  193. help
  194. This option enables ISL68233 voltage monitor set
  195. functionality. It is used by the common VID driver.
  196. endif
  197. config SYS_FSL_NUM_CC_PLLS
  198. int "Number of clock control PLLs"
  199. depends on MPC85xx || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A || ARCH_LS1028A
  200. default 2 if ARCH_LS1021A || ARCH_LS1028A || FSL_LSCH2
  201. default 6 if FSL_LSCH3 || MPC85xx
  202. config SYS_FSL_ESDHC_BE
  203. bool
  204. config SYS_FSL_IFC_BE
  205. bool
  206. config SYS_FSL_IFC_BANK_COUNT
  207. int "Maximum banks of Integrated flash controller"
  208. depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || \
  209. ARCH_LS1088A || ARCH_LS1021A || ARCH_B4860 || ARCH_B4420 || \
  210. ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || ARCH_T1024 || \
  211. ARCH_T2080 || ARCH_C29X || ARCH_P1010 || ARCH_BSC9131 || \
  212. ARCH_BSC9132
  213. default 3 if ARCH_BSC9131 || ARCH_BSC9132
  214. default 4 if ARCH_LS1043A || ARCH_LS1046A || ARCH_B4860 || \
  215. ARCH_B4420 || ARCH_P1010
  216. default 8 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LS1021A || \
  217. ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || \
  218. ARCH_T1024 || ARCH_T2080 || ARCH_C29X
  219. config FSL_QIXIS
  220. bool "Enable QIXIS support"
  221. depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
  222. config QIXIS_I2C_ACCESS
  223. bool "Access to QIXIS is over i2c"
  224. depends on FSL_QIXIS
  225. default y
  226. config HAS_FSL_DR_USB
  227. def_bool y
  228. depends on USB_EHCI_HCD && PPC
  229. config SYS_DPAA_FMAN
  230. bool
  231. config SYS_FSL_SRDS_1
  232. bool
  233. config SYS_FSL_SRDS_2
  234. bool
  235. config SYS_HAS_SERDES
  236. bool
  237. endmenu