pci-uclass.c 32 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2014 Google, Inc
  4. * Written by Simon Glass <sjg@chromium.org>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <pci.h>
  10. #include <asm/io.h>
  11. #include <dm/device-internal.h>
  12. #include <dm/lists.h>
  13. #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
  14. #include <asm/fsp/fsp_support.h>
  15. #endif
  16. #include "pci_internal.h"
  17. DECLARE_GLOBAL_DATA_PTR;
  18. int pci_get_bus(int busnum, struct udevice **busp)
  19. {
  20. int ret;
  21. ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
  22. /* Since buses may not be numbered yet try a little harder with bus 0 */
  23. if (ret == -ENODEV) {
  24. ret = uclass_first_device_err(UCLASS_PCI, busp);
  25. if (ret)
  26. return ret;
  27. ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
  28. }
  29. return ret;
  30. }
  31. struct udevice *pci_get_controller(struct udevice *dev)
  32. {
  33. while (device_is_on_pci_bus(dev))
  34. dev = dev->parent;
  35. return dev;
  36. }
  37. pci_dev_t dm_pci_get_bdf(struct udevice *dev)
  38. {
  39. struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
  40. struct udevice *bus = dev->parent;
  41. return PCI_ADD_BUS(bus->seq, pplat->devfn);
  42. }
  43. /**
  44. * pci_get_bus_max() - returns the bus number of the last active bus
  45. *
  46. * @return last bus number, or -1 if no active buses
  47. */
  48. static int pci_get_bus_max(void)
  49. {
  50. struct udevice *bus;
  51. struct uclass *uc;
  52. int ret = -1;
  53. ret = uclass_get(UCLASS_PCI, &uc);
  54. uclass_foreach_dev(bus, uc) {
  55. if (bus->seq > ret)
  56. ret = bus->seq;
  57. }
  58. debug("%s: ret=%d\n", __func__, ret);
  59. return ret;
  60. }
  61. int pci_last_busno(void)
  62. {
  63. return pci_get_bus_max();
  64. }
  65. int pci_get_ff(enum pci_size_t size)
  66. {
  67. switch (size) {
  68. case PCI_SIZE_8:
  69. return 0xff;
  70. case PCI_SIZE_16:
  71. return 0xffff;
  72. default:
  73. return 0xffffffff;
  74. }
  75. }
  76. int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
  77. struct udevice **devp)
  78. {
  79. struct udevice *dev;
  80. for (device_find_first_child(bus, &dev);
  81. dev;
  82. device_find_next_child(&dev)) {
  83. struct pci_child_platdata *pplat;
  84. pplat = dev_get_parent_platdata(dev);
  85. if (pplat && pplat->devfn == find_devfn) {
  86. *devp = dev;
  87. return 0;
  88. }
  89. }
  90. return -ENODEV;
  91. }
  92. int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
  93. {
  94. struct udevice *bus;
  95. int ret;
  96. ret = pci_get_bus(PCI_BUS(bdf), &bus);
  97. if (ret)
  98. return ret;
  99. return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
  100. }
  101. static int pci_device_matches_ids(struct udevice *dev,
  102. struct pci_device_id *ids)
  103. {
  104. struct pci_child_platdata *pplat;
  105. int i;
  106. pplat = dev_get_parent_platdata(dev);
  107. if (!pplat)
  108. return -EINVAL;
  109. for (i = 0; ids[i].vendor != 0; i++) {
  110. if (pplat->vendor == ids[i].vendor &&
  111. pplat->device == ids[i].device)
  112. return i;
  113. }
  114. return -EINVAL;
  115. }
  116. int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
  117. int *indexp, struct udevice **devp)
  118. {
  119. struct udevice *dev;
  120. /* Scan all devices on this bus */
  121. for (device_find_first_child(bus, &dev);
  122. dev;
  123. device_find_next_child(&dev)) {
  124. if (pci_device_matches_ids(dev, ids) >= 0) {
  125. if ((*indexp)-- <= 0) {
  126. *devp = dev;
  127. return 0;
  128. }
  129. }
  130. }
  131. return -ENODEV;
  132. }
  133. int pci_find_device_id(struct pci_device_id *ids, int index,
  134. struct udevice **devp)
  135. {
  136. struct udevice *bus;
  137. /* Scan all known buses */
  138. for (uclass_first_device(UCLASS_PCI, &bus);
  139. bus;
  140. uclass_next_device(&bus)) {
  141. if (!pci_bus_find_devices(bus, ids, &index, devp))
  142. return 0;
  143. }
  144. *devp = NULL;
  145. return -ENODEV;
  146. }
  147. static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
  148. unsigned int device, int *indexp,
  149. struct udevice **devp)
  150. {
  151. struct pci_child_platdata *pplat;
  152. struct udevice *dev;
  153. for (device_find_first_child(bus, &dev);
  154. dev;
  155. device_find_next_child(&dev)) {
  156. pplat = dev_get_parent_platdata(dev);
  157. if (pplat->vendor == vendor && pplat->device == device) {
  158. if (!(*indexp)--) {
  159. *devp = dev;
  160. return 0;
  161. }
  162. }
  163. }
  164. return -ENODEV;
  165. }
  166. int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
  167. struct udevice **devp)
  168. {
  169. struct udevice *bus;
  170. /* Scan all known buses */
  171. for (uclass_first_device(UCLASS_PCI, &bus);
  172. bus;
  173. uclass_next_device(&bus)) {
  174. if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
  175. return device_probe(*devp);
  176. }
  177. *devp = NULL;
  178. return -ENODEV;
  179. }
  180. int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
  181. {
  182. struct udevice *dev;
  183. /* Scan all known buses */
  184. for (pci_find_first_device(&dev);
  185. dev;
  186. pci_find_next_device(&dev)) {
  187. struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
  188. if (pplat->class == find_class && !index--) {
  189. *devp = dev;
  190. return device_probe(*devp);
  191. }
  192. }
  193. *devp = NULL;
  194. return -ENODEV;
  195. }
  196. int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
  197. unsigned long value, enum pci_size_t size)
  198. {
  199. struct dm_pci_ops *ops;
  200. ops = pci_get_ops(bus);
  201. if (!ops->write_config)
  202. return -ENOSYS;
  203. return ops->write_config(bus, bdf, offset, value, size);
  204. }
  205. int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
  206. u32 clr, u32 set)
  207. {
  208. ulong val;
  209. int ret;
  210. ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
  211. if (ret)
  212. return ret;
  213. val &= ~clr;
  214. val |= set;
  215. return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
  216. }
  217. int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
  218. enum pci_size_t size)
  219. {
  220. struct udevice *bus;
  221. int ret;
  222. ret = pci_get_bus(PCI_BUS(bdf), &bus);
  223. if (ret)
  224. return ret;
  225. return pci_bus_write_config(bus, bdf, offset, value, size);
  226. }
  227. int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
  228. enum pci_size_t size)
  229. {
  230. struct udevice *bus;
  231. for (bus = dev; device_is_on_pci_bus(bus);)
  232. bus = bus->parent;
  233. return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
  234. size);
  235. }
  236. int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
  237. {
  238. return pci_write_config(bdf, offset, value, PCI_SIZE_32);
  239. }
  240. int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
  241. {
  242. return pci_write_config(bdf, offset, value, PCI_SIZE_16);
  243. }
  244. int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
  245. {
  246. return pci_write_config(bdf, offset, value, PCI_SIZE_8);
  247. }
  248. int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
  249. {
  250. return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
  251. }
  252. int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
  253. {
  254. return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
  255. }
  256. int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
  257. {
  258. return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
  259. }
  260. int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
  261. unsigned long *valuep, enum pci_size_t size)
  262. {
  263. struct dm_pci_ops *ops;
  264. ops = pci_get_ops(bus);
  265. if (!ops->read_config)
  266. return -ENOSYS;
  267. return ops->read_config(bus, bdf, offset, valuep, size);
  268. }
  269. int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
  270. enum pci_size_t size)
  271. {
  272. struct udevice *bus;
  273. int ret;
  274. ret = pci_get_bus(PCI_BUS(bdf), &bus);
  275. if (ret)
  276. return ret;
  277. return pci_bus_read_config(bus, bdf, offset, valuep, size);
  278. }
  279. int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
  280. enum pci_size_t size)
  281. {
  282. struct udevice *bus;
  283. for (bus = dev; device_is_on_pci_bus(bus);)
  284. bus = bus->parent;
  285. return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
  286. size);
  287. }
  288. int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
  289. {
  290. unsigned long value;
  291. int ret;
  292. ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
  293. if (ret)
  294. return ret;
  295. *valuep = value;
  296. return 0;
  297. }
  298. int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
  299. {
  300. unsigned long value;
  301. int ret;
  302. ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
  303. if (ret)
  304. return ret;
  305. *valuep = value;
  306. return 0;
  307. }
  308. int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
  309. {
  310. unsigned long value;
  311. int ret;
  312. ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
  313. if (ret)
  314. return ret;
  315. *valuep = value;
  316. return 0;
  317. }
  318. int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
  319. {
  320. unsigned long value;
  321. int ret;
  322. ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
  323. if (ret)
  324. return ret;
  325. *valuep = value;
  326. return 0;
  327. }
  328. int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
  329. {
  330. unsigned long value;
  331. int ret;
  332. ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
  333. if (ret)
  334. return ret;
  335. *valuep = value;
  336. return 0;
  337. }
  338. int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
  339. {
  340. unsigned long value;
  341. int ret;
  342. ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
  343. if (ret)
  344. return ret;
  345. *valuep = value;
  346. return 0;
  347. }
  348. int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
  349. {
  350. u8 val;
  351. int ret;
  352. ret = dm_pci_read_config8(dev, offset, &val);
  353. if (ret)
  354. return ret;
  355. val &= ~clr;
  356. val |= set;
  357. return dm_pci_write_config8(dev, offset, val);
  358. }
  359. int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
  360. {
  361. u16 val;
  362. int ret;
  363. ret = dm_pci_read_config16(dev, offset, &val);
  364. if (ret)
  365. return ret;
  366. val &= ~clr;
  367. val |= set;
  368. return dm_pci_write_config16(dev, offset, val);
  369. }
  370. int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
  371. {
  372. u32 val;
  373. int ret;
  374. ret = dm_pci_read_config32(dev, offset, &val);
  375. if (ret)
  376. return ret;
  377. val &= ~clr;
  378. val |= set;
  379. return dm_pci_write_config32(dev, offset, val);
  380. }
  381. static void set_vga_bridge_bits(struct udevice *dev)
  382. {
  383. struct udevice *parent = dev->parent;
  384. u16 bc;
  385. while (parent->seq != 0) {
  386. dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
  387. bc |= PCI_BRIDGE_CTL_VGA;
  388. dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
  389. parent = parent->parent;
  390. }
  391. }
  392. int pci_auto_config_devices(struct udevice *bus)
  393. {
  394. struct pci_controller *hose = bus->uclass_priv;
  395. struct pci_child_platdata *pplat;
  396. unsigned int sub_bus;
  397. struct udevice *dev;
  398. int ret;
  399. sub_bus = bus->seq;
  400. debug("%s: start\n", __func__);
  401. pciauto_config_init(hose);
  402. for (ret = device_find_first_child(bus, &dev);
  403. !ret && dev;
  404. ret = device_find_next_child(&dev)) {
  405. unsigned int max_bus;
  406. int ret;
  407. debug("%s: device %s\n", __func__, dev->name);
  408. ret = dm_pciauto_config_device(dev);
  409. if (ret < 0)
  410. return ret;
  411. max_bus = ret;
  412. sub_bus = max(sub_bus, max_bus);
  413. pplat = dev_get_parent_platdata(dev);
  414. if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
  415. set_vga_bridge_bits(dev);
  416. }
  417. debug("%s: done\n", __func__);
  418. return sub_bus;
  419. }
  420. int pci_generic_mmap_write_config(
  421. struct udevice *bus,
  422. int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
  423. pci_dev_t bdf,
  424. uint offset,
  425. ulong value,
  426. enum pci_size_t size)
  427. {
  428. void *address;
  429. if (addr_f(bus, bdf, offset, &address) < 0)
  430. return 0;
  431. switch (size) {
  432. case PCI_SIZE_8:
  433. writeb(value, address);
  434. return 0;
  435. case PCI_SIZE_16:
  436. writew(value, address);
  437. return 0;
  438. case PCI_SIZE_32:
  439. writel(value, address);
  440. return 0;
  441. default:
  442. return -EINVAL;
  443. }
  444. }
  445. int pci_generic_mmap_read_config(
  446. struct udevice *bus,
  447. int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
  448. pci_dev_t bdf,
  449. uint offset,
  450. ulong *valuep,
  451. enum pci_size_t size)
  452. {
  453. void *address;
  454. if (addr_f(bus, bdf, offset, &address) < 0) {
  455. *valuep = pci_get_ff(size);
  456. return 0;
  457. }
  458. switch (size) {
  459. case PCI_SIZE_8:
  460. *valuep = readb(address);
  461. return 0;
  462. case PCI_SIZE_16:
  463. *valuep = readw(address);
  464. return 0;
  465. case PCI_SIZE_32:
  466. *valuep = readl(address);
  467. return 0;
  468. default:
  469. return -EINVAL;
  470. }
  471. }
  472. int dm_pci_hose_probe_bus(struct udevice *bus)
  473. {
  474. int sub_bus;
  475. int ret;
  476. debug("%s\n", __func__);
  477. sub_bus = pci_get_bus_max() + 1;
  478. debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
  479. dm_pciauto_prescan_setup_bridge(bus, sub_bus);
  480. ret = device_probe(bus);
  481. if (ret) {
  482. debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
  483. ret);
  484. return ret;
  485. }
  486. if (sub_bus != bus->seq) {
  487. printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
  488. __func__, bus->name, bus->seq, sub_bus);
  489. return -EPIPE;
  490. }
  491. sub_bus = pci_get_bus_max();
  492. dm_pciauto_postscan_setup_bridge(bus, sub_bus);
  493. return sub_bus;
  494. }
  495. /**
  496. * pci_match_one_device - Tell if a PCI device structure has a matching
  497. * PCI device id structure
  498. * @id: single PCI device id structure to match
  499. * @find: the PCI device id structure to match against
  500. *
  501. * Returns true if the finding pci_device_id structure matched or false if
  502. * there is no match.
  503. */
  504. static bool pci_match_one_id(const struct pci_device_id *id,
  505. const struct pci_device_id *find)
  506. {
  507. if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
  508. (id->device == PCI_ANY_ID || id->device == find->device) &&
  509. (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
  510. (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
  511. !((id->class ^ find->class) & id->class_mask))
  512. return true;
  513. return false;
  514. }
  515. /**
  516. * pci_find_and_bind_driver() - Find and bind the right PCI driver
  517. *
  518. * This only looks at certain fields in the descriptor.
  519. *
  520. * @parent: Parent bus
  521. * @find_id: Specification of the driver to find
  522. * @bdf: Bus/device/function addreess - see PCI_BDF()
  523. * @devp: Returns a pointer to the device created
  524. * @return 0 if OK, -EPERM if the device is not needed before relocation and
  525. * therefore was not created, other -ve value on error
  526. */
  527. static int pci_find_and_bind_driver(struct udevice *parent,
  528. struct pci_device_id *find_id,
  529. pci_dev_t bdf, struct udevice **devp)
  530. {
  531. struct pci_driver_entry *start, *entry;
  532. const char *drv;
  533. int n_ents;
  534. int ret;
  535. char name[30], *str;
  536. bool bridge;
  537. *devp = NULL;
  538. debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
  539. find_id->vendor, find_id->device);
  540. start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
  541. n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
  542. for (entry = start; entry != start + n_ents; entry++) {
  543. const struct pci_device_id *id;
  544. struct udevice *dev;
  545. const struct driver *drv;
  546. for (id = entry->match;
  547. id->vendor || id->subvendor || id->class_mask;
  548. id++) {
  549. if (!pci_match_one_id(id, find_id))
  550. continue;
  551. drv = entry->driver;
  552. /*
  553. * In the pre-relocation phase, we only bind devices
  554. * whose driver has the DM_FLAG_PRE_RELOC set, to save
  555. * precious memory space as on some platforms as that
  556. * space is pretty limited (ie: using Cache As RAM).
  557. */
  558. if (!(gd->flags & GD_FLG_RELOC) &&
  559. !(drv->flags & DM_FLAG_PRE_RELOC))
  560. return -EPERM;
  561. /*
  562. * We could pass the descriptor to the driver as
  563. * platdata (instead of NULL) and allow its bind()
  564. * method to return -ENOENT if it doesn't support this
  565. * device. That way we could continue the search to
  566. * find another driver. For now this doesn't seem
  567. * necesssary, so just bind the first match.
  568. */
  569. ret = device_bind(parent, drv, drv->name, NULL, -1,
  570. &dev);
  571. if (ret)
  572. goto error;
  573. debug("%s: Match found: %s\n", __func__, drv->name);
  574. dev->driver_data = id->driver_data;
  575. *devp = dev;
  576. return 0;
  577. }
  578. }
  579. bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
  580. /*
  581. * In the pre-relocation phase, we only bind bridge devices to save
  582. * precious memory space as on some platforms as that space is pretty
  583. * limited (ie: using Cache As RAM).
  584. */
  585. if (!(gd->flags & GD_FLG_RELOC) && !bridge)
  586. return -EPERM;
  587. /* Bind a generic driver so that the device can be used */
  588. sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
  589. PCI_FUNC(bdf));
  590. str = strdup(name);
  591. if (!str)
  592. return -ENOMEM;
  593. drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
  594. ret = device_bind_driver(parent, drv, str, devp);
  595. if (ret) {
  596. debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
  597. free(str);
  598. return ret;
  599. }
  600. debug("%s: No match found: bound generic driver instead\n", __func__);
  601. return 0;
  602. error:
  603. debug("%s: No match found: error %d\n", __func__, ret);
  604. return ret;
  605. }
  606. int pci_bind_bus_devices(struct udevice *bus)
  607. {
  608. ulong vendor, device;
  609. ulong header_type;
  610. pci_dev_t bdf, end;
  611. bool found_multi;
  612. int ret;
  613. found_multi = false;
  614. end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
  615. PCI_MAX_PCI_FUNCTIONS - 1);
  616. for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
  617. bdf += PCI_BDF(0, 0, 1)) {
  618. struct pci_child_platdata *pplat;
  619. struct udevice *dev;
  620. ulong class;
  621. if (!PCI_FUNC(bdf))
  622. found_multi = false;
  623. if (PCI_FUNC(bdf) && !found_multi)
  624. continue;
  625. /* Check only the first access, we don't expect problems */
  626. ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
  627. &header_type, PCI_SIZE_8);
  628. if (ret)
  629. goto error;
  630. pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
  631. PCI_SIZE_16);
  632. if (vendor == 0xffff || vendor == 0x0000)
  633. continue;
  634. if (!PCI_FUNC(bdf))
  635. found_multi = header_type & 0x80;
  636. debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
  637. bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
  638. pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
  639. PCI_SIZE_16);
  640. pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
  641. PCI_SIZE_32);
  642. class >>= 8;
  643. /* Find this device in the device tree */
  644. ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
  645. /* If nothing in the device tree, bind a device */
  646. if (ret == -ENODEV) {
  647. struct pci_device_id find_id;
  648. ulong val;
  649. memset(&find_id, '\0', sizeof(find_id));
  650. find_id.vendor = vendor;
  651. find_id.device = device;
  652. find_id.class = class;
  653. if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
  654. pci_bus_read_config(bus, bdf,
  655. PCI_SUBSYSTEM_VENDOR_ID,
  656. &val, PCI_SIZE_32);
  657. find_id.subvendor = val & 0xffff;
  658. find_id.subdevice = val >> 16;
  659. }
  660. ret = pci_find_and_bind_driver(bus, &find_id, bdf,
  661. &dev);
  662. }
  663. if (ret == -EPERM)
  664. continue;
  665. else if (ret)
  666. return ret;
  667. /* Update the platform data */
  668. pplat = dev_get_parent_platdata(dev);
  669. pplat->devfn = PCI_MASK_BUS(bdf);
  670. pplat->vendor = vendor;
  671. pplat->device = device;
  672. pplat->class = class;
  673. }
  674. return 0;
  675. error:
  676. printf("Cannot read bus configuration: %d\n", ret);
  677. return ret;
  678. }
  679. static void decode_regions(struct pci_controller *hose, ofnode parent_node,
  680. ofnode node)
  681. {
  682. int pci_addr_cells, addr_cells, size_cells;
  683. int cells_per_record;
  684. const u32 *prop;
  685. int len;
  686. int i;
  687. prop = ofnode_get_property(node, "ranges", &len);
  688. if (!prop) {
  689. debug("%s: Cannot decode regions\n", __func__);
  690. return;
  691. }
  692. pci_addr_cells = ofnode_read_simple_addr_cells(node);
  693. addr_cells = ofnode_read_simple_addr_cells(parent_node);
  694. size_cells = ofnode_read_simple_size_cells(node);
  695. /* PCI addresses are always 3-cells */
  696. len /= sizeof(u32);
  697. cells_per_record = pci_addr_cells + addr_cells + size_cells;
  698. hose->region_count = 0;
  699. debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
  700. cells_per_record);
  701. for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
  702. u64 pci_addr, addr, size;
  703. int space_code;
  704. u32 flags;
  705. int type;
  706. int pos;
  707. if (len < cells_per_record)
  708. break;
  709. flags = fdt32_to_cpu(prop[0]);
  710. space_code = (flags >> 24) & 3;
  711. pci_addr = fdtdec_get_number(prop + 1, 2);
  712. prop += pci_addr_cells;
  713. addr = fdtdec_get_number(prop, addr_cells);
  714. prop += addr_cells;
  715. size = fdtdec_get_number(prop, size_cells);
  716. prop += size_cells;
  717. debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
  718. __func__, hose->region_count, pci_addr, addr, size, space_code);
  719. if (space_code & 2) {
  720. type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
  721. PCI_REGION_MEM;
  722. } else if (space_code & 1) {
  723. type = PCI_REGION_IO;
  724. } else {
  725. continue;
  726. }
  727. if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
  728. type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
  729. debug(" - beyond the 32-bit boundary, ignoring\n");
  730. continue;
  731. }
  732. pos = -1;
  733. for (i = 0; i < hose->region_count; i++) {
  734. if (hose->regions[i].flags == type)
  735. pos = i;
  736. }
  737. if (pos == -1)
  738. pos = hose->region_count++;
  739. debug(" - type=%d, pos=%d\n", type, pos);
  740. pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
  741. }
  742. /* Add a region for our local memory */
  743. #ifdef CONFIG_NR_DRAM_BANKS
  744. bd_t *bd = gd->bd;
  745. if (!bd)
  746. return;
  747. for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
  748. if (bd->bi_dram[i].size) {
  749. pci_set_region(hose->regions + hose->region_count++,
  750. bd->bi_dram[i].start,
  751. bd->bi_dram[i].start,
  752. bd->bi_dram[i].size,
  753. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  754. }
  755. }
  756. #else
  757. phys_addr_t base = 0, size;
  758. size = gd->ram_size;
  759. #ifdef CONFIG_SYS_SDRAM_BASE
  760. base = CONFIG_SYS_SDRAM_BASE;
  761. #endif
  762. if (gd->pci_ram_top && gd->pci_ram_top < base + size)
  763. size = gd->pci_ram_top - base;
  764. if (size)
  765. pci_set_region(hose->regions + hose->region_count++, base,
  766. base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  767. #endif
  768. return;
  769. }
  770. static int pci_uclass_pre_probe(struct udevice *bus)
  771. {
  772. struct pci_controller *hose;
  773. debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
  774. bus->parent->name);
  775. hose = bus->uclass_priv;
  776. /* For bridges, use the top-level PCI controller */
  777. if (!device_is_on_pci_bus(bus)) {
  778. hose->ctlr = bus;
  779. decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
  780. } else {
  781. struct pci_controller *parent_hose;
  782. parent_hose = dev_get_uclass_priv(bus->parent);
  783. hose->ctlr = parent_hose->bus;
  784. }
  785. hose->bus = bus;
  786. hose->first_busno = bus->seq;
  787. hose->last_busno = bus->seq;
  788. return 0;
  789. }
  790. static int pci_uclass_post_probe(struct udevice *bus)
  791. {
  792. int ret;
  793. debug("%s: probing bus %d\n", __func__, bus->seq);
  794. ret = pci_bind_bus_devices(bus);
  795. if (ret)
  796. return ret;
  797. #ifdef CONFIG_PCI_PNP
  798. ret = pci_auto_config_devices(bus);
  799. if (ret < 0)
  800. return ret;
  801. #endif
  802. #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
  803. /*
  804. * Per Intel FSP specification, we should call FSP notify API to
  805. * inform FSP that PCI enumeration has been done so that FSP will
  806. * do any necessary initialization as required by the chipset's
  807. * BIOS Writer's Guide (BWG).
  808. *
  809. * Unfortunately we have to put this call here as with driver model,
  810. * the enumeration is all done on a lazy basis as needed, so until
  811. * something is touched on PCI it won't happen.
  812. *
  813. * Note we only call this 1) after U-Boot is relocated, and 2)
  814. * root bus has finished probing.
  815. */
  816. if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
  817. ret = fsp_init_phase_pci();
  818. if (ret)
  819. return ret;
  820. }
  821. #endif
  822. return 0;
  823. }
  824. static int pci_uclass_child_post_bind(struct udevice *dev)
  825. {
  826. struct pci_child_platdata *pplat;
  827. struct fdt_pci_addr addr;
  828. int ret;
  829. if (!dev_of_valid(dev))
  830. return 0;
  831. pplat = dev_get_parent_platdata(dev);
  832. /* Extract vendor id and device id if available */
  833. ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
  834. /* Extract the devfn from fdt_pci_addr */
  835. ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG, "reg",
  836. &addr);
  837. if (ret) {
  838. if (ret != -ENOENT)
  839. return -EINVAL;
  840. } else {
  841. pplat->devfn = addr.phys_hi & 0xff00;
  842. }
  843. return 0;
  844. }
  845. static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
  846. uint offset, ulong *valuep,
  847. enum pci_size_t size)
  848. {
  849. struct pci_controller *hose = bus->uclass_priv;
  850. return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
  851. }
  852. static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
  853. uint offset, ulong value,
  854. enum pci_size_t size)
  855. {
  856. struct pci_controller *hose = bus->uclass_priv;
  857. return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
  858. }
  859. static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
  860. {
  861. struct udevice *dev;
  862. int ret = 0;
  863. /*
  864. * Scan through all the PCI controllers. On x86 there will only be one
  865. * but that is not necessarily true on other hardware.
  866. */
  867. do {
  868. device_find_first_child(bus, &dev);
  869. if (dev) {
  870. *devp = dev;
  871. return 0;
  872. }
  873. ret = uclass_next_device(&bus);
  874. if (ret)
  875. return ret;
  876. } while (bus);
  877. return 0;
  878. }
  879. int pci_find_next_device(struct udevice **devp)
  880. {
  881. struct udevice *child = *devp;
  882. struct udevice *bus = child->parent;
  883. int ret;
  884. /* First try all the siblings */
  885. *devp = NULL;
  886. while (child) {
  887. device_find_next_child(&child);
  888. if (child) {
  889. *devp = child;
  890. return 0;
  891. }
  892. }
  893. /* We ran out of siblings. Try the next bus */
  894. ret = uclass_next_device(&bus);
  895. if (ret)
  896. return ret;
  897. return bus ? skip_to_next_device(bus, devp) : 0;
  898. }
  899. int pci_find_first_device(struct udevice **devp)
  900. {
  901. struct udevice *bus;
  902. int ret;
  903. *devp = NULL;
  904. ret = uclass_first_device(UCLASS_PCI, &bus);
  905. if (ret)
  906. return ret;
  907. return skip_to_next_device(bus, devp);
  908. }
  909. ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
  910. {
  911. switch (size) {
  912. case PCI_SIZE_8:
  913. return (value >> ((offset & 3) * 8)) & 0xff;
  914. case PCI_SIZE_16:
  915. return (value >> ((offset & 2) * 8)) & 0xffff;
  916. default:
  917. return value;
  918. }
  919. }
  920. ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
  921. enum pci_size_t size)
  922. {
  923. uint off_mask;
  924. uint val_mask, shift;
  925. ulong ldata, mask;
  926. switch (size) {
  927. case PCI_SIZE_8:
  928. off_mask = 3;
  929. val_mask = 0xff;
  930. break;
  931. case PCI_SIZE_16:
  932. off_mask = 2;
  933. val_mask = 0xffff;
  934. break;
  935. default:
  936. return value;
  937. }
  938. shift = (offset & off_mask) * 8;
  939. ldata = (value & val_mask) << shift;
  940. mask = val_mask << shift;
  941. value = (old & ~mask) | ldata;
  942. return value;
  943. }
  944. int pci_get_regions(struct udevice *dev, struct pci_region **iop,
  945. struct pci_region **memp, struct pci_region **prefp)
  946. {
  947. struct udevice *bus = pci_get_controller(dev);
  948. struct pci_controller *hose = dev_get_uclass_priv(bus);
  949. int i;
  950. *iop = NULL;
  951. *memp = NULL;
  952. *prefp = NULL;
  953. for (i = 0; i < hose->region_count; i++) {
  954. switch (hose->regions[i].flags) {
  955. case PCI_REGION_IO:
  956. if (!*iop || (*iop)->size < hose->regions[i].size)
  957. *iop = hose->regions + i;
  958. break;
  959. case PCI_REGION_MEM:
  960. if (!*memp || (*memp)->size < hose->regions[i].size)
  961. *memp = hose->regions + i;
  962. break;
  963. case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
  964. if (!*prefp || (*prefp)->size < hose->regions[i].size)
  965. *prefp = hose->regions + i;
  966. break;
  967. }
  968. }
  969. return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
  970. }
  971. u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
  972. {
  973. u32 addr;
  974. int bar;
  975. bar = PCI_BASE_ADDRESS_0 + barnum * 4;
  976. dm_pci_read_config32(dev, bar, &addr);
  977. if (addr & PCI_BASE_ADDRESS_SPACE_IO)
  978. return addr & PCI_BASE_ADDRESS_IO_MASK;
  979. else
  980. return addr & PCI_BASE_ADDRESS_MEM_MASK;
  981. }
  982. void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
  983. {
  984. int bar;
  985. bar = PCI_BASE_ADDRESS_0 + barnum * 4;
  986. dm_pci_write_config32(dev, bar, addr);
  987. }
  988. static int _dm_pci_bus_to_phys(struct udevice *ctlr,
  989. pci_addr_t bus_addr, unsigned long flags,
  990. unsigned long skip_mask, phys_addr_t *pa)
  991. {
  992. struct pci_controller *hose = dev_get_uclass_priv(ctlr);
  993. struct pci_region *res;
  994. int i;
  995. if (hose->region_count == 0) {
  996. *pa = bus_addr;
  997. return 0;
  998. }
  999. for (i = 0; i < hose->region_count; i++) {
  1000. res = &hose->regions[i];
  1001. if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
  1002. continue;
  1003. if (res->flags & skip_mask)
  1004. continue;
  1005. if (bus_addr >= res->bus_start &&
  1006. (bus_addr - res->bus_start) < res->size) {
  1007. *pa = (bus_addr - res->bus_start + res->phys_start);
  1008. return 0;
  1009. }
  1010. }
  1011. return 1;
  1012. }
  1013. phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
  1014. unsigned long flags)
  1015. {
  1016. phys_addr_t phys_addr = 0;
  1017. struct udevice *ctlr;
  1018. int ret;
  1019. /* The root controller has the region information */
  1020. ctlr = pci_get_controller(dev);
  1021. /*
  1022. * if PCI_REGION_MEM is set we do a two pass search with preference
  1023. * on matches that don't have PCI_REGION_SYS_MEMORY set
  1024. */
  1025. if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
  1026. ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
  1027. flags, PCI_REGION_SYS_MEMORY,
  1028. &phys_addr);
  1029. if (!ret)
  1030. return phys_addr;
  1031. }
  1032. ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
  1033. if (ret)
  1034. puts("pci_hose_bus_to_phys: invalid physical address\n");
  1035. return phys_addr;
  1036. }
  1037. int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
  1038. unsigned long flags, unsigned long skip_mask,
  1039. pci_addr_t *ba)
  1040. {
  1041. struct pci_region *res;
  1042. struct udevice *ctlr;
  1043. pci_addr_t bus_addr;
  1044. int i;
  1045. struct pci_controller *hose;
  1046. /* The root controller has the region information */
  1047. ctlr = pci_get_controller(dev);
  1048. hose = dev_get_uclass_priv(ctlr);
  1049. if (hose->region_count == 0) {
  1050. *ba = phys_addr;
  1051. return 0;
  1052. }
  1053. for (i = 0; i < hose->region_count; i++) {
  1054. res = &hose->regions[i];
  1055. if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
  1056. continue;
  1057. if (res->flags & skip_mask)
  1058. continue;
  1059. bus_addr = phys_addr - res->phys_start + res->bus_start;
  1060. if (bus_addr >= res->bus_start &&
  1061. (bus_addr - res->bus_start) < res->size) {
  1062. *ba = bus_addr;
  1063. return 0;
  1064. }
  1065. }
  1066. return 1;
  1067. }
  1068. pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
  1069. unsigned long flags)
  1070. {
  1071. pci_addr_t bus_addr = 0;
  1072. int ret;
  1073. /*
  1074. * if PCI_REGION_MEM is set we do a two pass search with preference
  1075. * on matches that don't have PCI_REGION_SYS_MEMORY set
  1076. */
  1077. if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
  1078. ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
  1079. PCI_REGION_SYS_MEMORY, &bus_addr);
  1080. if (!ret)
  1081. return bus_addr;
  1082. }
  1083. ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
  1084. if (ret)
  1085. puts("pci_hose_phys_to_bus: invalid physical address\n");
  1086. return bus_addr;
  1087. }
  1088. void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
  1089. {
  1090. pci_addr_t pci_bus_addr;
  1091. u32 bar_response;
  1092. /* read BAR address */
  1093. dm_pci_read_config32(dev, bar, &bar_response);
  1094. pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
  1095. /*
  1096. * Pass "0" as the length argument to pci_bus_to_virt. The arg
  1097. * isn't actualy used on any platform because u-boot assumes a static
  1098. * linear mapping. In the future, this could read the BAR size
  1099. * and pass that as the size if needed.
  1100. */
  1101. return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
  1102. }
  1103. int dm_pci_find_capability(struct udevice *dev, int cap)
  1104. {
  1105. u16 status;
  1106. u8 header_type;
  1107. int ttl = PCI_FIND_CAP_TTL;
  1108. u8 id;
  1109. u16 ent;
  1110. u8 pos;
  1111. dm_pci_read_config16(dev, PCI_STATUS, &status);
  1112. if (!(status & PCI_STATUS_CAP_LIST))
  1113. return 0;
  1114. dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
  1115. if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
  1116. pos = PCI_CB_CAPABILITY_LIST;
  1117. else
  1118. pos = PCI_CAPABILITY_LIST;
  1119. dm_pci_read_config8(dev, pos, &pos);
  1120. while (ttl--) {
  1121. if (pos < PCI_STD_HEADER_SIZEOF)
  1122. break;
  1123. pos &= ~3;
  1124. dm_pci_read_config16(dev, pos, &ent);
  1125. id = ent & 0xff;
  1126. if (id == 0xff)
  1127. break;
  1128. if (id == cap)
  1129. return pos;
  1130. pos = (ent >> 8);
  1131. }
  1132. return 0;
  1133. }
  1134. int dm_pci_find_ext_capability(struct udevice *dev, int cap)
  1135. {
  1136. u32 header;
  1137. int ttl;
  1138. int pos = PCI_CFG_SPACE_SIZE;
  1139. /* minimum 8 bytes per capability */
  1140. ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
  1141. dm_pci_read_config32(dev, pos, &header);
  1142. /*
  1143. * If we have no capabilities, this is indicated by cap ID,
  1144. * cap version and next pointer all being 0.
  1145. */
  1146. if (header == 0)
  1147. return 0;
  1148. while (ttl--) {
  1149. if (PCI_EXT_CAP_ID(header) == cap)
  1150. return pos;
  1151. pos = PCI_EXT_CAP_NEXT(header);
  1152. if (pos < PCI_CFG_SPACE_SIZE)
  1153. break;
  1154. dm_pci_read_config32(dev, pos, &header);
  1155. }
  1156. return 0;
  1157. }
  1158. UCLASS_DRIVER(pci) = {
  1159. .id = UCLASS_PCI,
  1160. .name = "pci",
  1161. .flags = DM_UC_FLAG_SEQ_ALIAS,
  1162. .post_bind = dm_scan_fdt_dev,
  1163. .pre_probe = pci_uclass_pre_probe,
  1164. .post_probe = pci_uclass_post_probe,
  1165. .child_post_bind = pci_uclass_child_post_bind,
  1166. .per_device_auto_alloc_size = sizeof(struct pci_controller),
  1167. .per_child_platdata_auto_alloc_size =
  1168. sizeof(struct pci_child_platdata),
  1169. };
  1170. static const struct dm_pci_ops pci_bridge_ops = {
  1171. .read_config = pci_bridge_read_config,
  1172. .write_config = pci_bridge_write_config,
  1173. };
  1174. static const struct udevice_id pci_bridge_ids[] = {
  1175. { .compatible = "pci-bridge" },
  1176. { }
  1177. };
  1178. U_BOOT_DRIVER(pci_bridge_drv) = {
  1179. .name = "pci_bridge_drv",
  1180. .id = UCLASS_PCI,
  1181. .of_match = pci_bridge_ids,
  1182. .ops = &pci_bridge_ops,
  1183. };
  1184. UCLASS_DRIVER(pci_generic) = {
  1185. .id = UCLASS_PCI_GENERIC,
  1186. .name = "pci_generic",
  1187. };
  1188. static const struct udevice_id pci_generic_ids[] = {
  1189. { .compatible = "pci-generic" },
  1190. { }
  1191. };
  1192. U_BOOT_DRIVER(pci_generic_drv) = {
  1193. .name = "pci_generic_drv",
  1194. .id = UCLASS_PCI_GENERIC,
  1195. .of_match = pci_generic_ids,
  1196. };
  1197. void pci_init(void)
  1198. {
  1199. struct udevice *bus;
  1200. /*
  1201. * Enumerate all known controller devices. Enumeration has the side-
  1202. * effect of probing them, so PCIe devices will be enumerated too.
  1203. */
  1204. for (uclass_first_device(UCLASS_PCI, &bus);
  1205. bus;
  1206. uclass_next_device(&bus)) {
  1207. ;
  1208. }
  1209. }