stxssa.h 15 KB

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  1. /*
  2. * (C) Copyright 2005 Embedded Alley Solutions, Inc.
  3. * Dan Malek <dan@embeddedalley.com>
  4. * Copied from STx GP3.
  5. * Updates for Silicon Tx GP3 SSA board.
  6. *
  7. * (C) Copyright 2002,2003 Motorola,Inc.
  8. * Xianghua Xiao <X.Xiao@motorola.com>
  9. *
  10. * See file CREDITS for list of people who contributed to this
  11. * project.
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License as
  15. * published by the Free Software Foundation; either version 2 of
  16. * the License, or (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26. * MA 02111-1307 USA
  27. */
  28. /* mpc8560ads board configuration file */
  29. /* please refer to doc/README.mpc85xx for more info */
  30. /* make sure you change the MAC address and other network params first,
  31. * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
  32. */
  33. #ifndef __CONFIG_H
  34. #define __CONFIG_H
  35. /* High Level Configuration Options */
  36. #define CONFIG_BOOKE 1 /* BOOKE */
  37. #define CONFIG_E500 1 /* BOOKE e500 family */
  38. #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
  39. #define CONFIG_CPM2 1 /* has CPM2 */
  40. #define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
  41. #define CONFIG_MPC8560 1
  42. #define CONFIG_SYS_TEXT_BASE 0xFFF80000
  43. #define CONFIG_PCI /* PCI ethernet support */
  44. #define CONFIG_TSEC_ENET /* tsec ethernet support*/
  45. #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
  46. #define CONFIG_ENV_OVERWRITE
  47. #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
  48. /* sysclk for MPC85xx
  49. */
  50. #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
  51. /* Blinkin' LEDs for Robert :-)
  52. */
  53. #define CONFIG_SHOW_ACTIVITY 1
  54. /*
  55. * These can be toggled for performance analysis, otherwise use default.
  56. */
  57. #define CONFIG_L2_CACHE /* toggle L2 cache */
  58. #define CONFIG_BTB /* toggle branch predition */
  59. #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
  60. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  61. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
  62. #define CONFIG_SYS_MEMTEST_END 0x00400000
  63. /* Localbus connector. There are many options that can be
  64. * connected here, including sdram or lots of flash.
  65. * This address, however, is used to configure a 256M local bus
  66. * window that includes the Config latch below.
  67. */
  68. #define CONFIG_SYS_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */
  69. #define CONFIG_SYS_LBC_OPTION_SIZE 256 /* 256MB */
  70. /* There are various flash options used, we configure for the largest,
  71. * which is 64Mbytes. The CFI works fine and will discover the proper
  72. * sizes.
  73. */
  74. #ifdef CONFIG_STXSSA_4M
  75. #define CONFIG_SYS_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */
  76. #else
  77. #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */
  78. #endif
  79. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x1801) /* port size 32bit */
  80. #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x0FF7)
  81. #define CONFIG_SYS_FLASH_CFI 1
  82. #define CONFIG_FLASH_CFI_DRIVER 1
  83. #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
  84. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  85. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  86. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
  87. #define CONFIG_SYS_FLASH_PROTECTION
  88. /* The configuration latch is Chip Select 1.
  89. * It's an 8-bit latch in the lower 8 bits of the word.
  90. */
  91. #define CONFIG_SYS_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */
  92. #define CONFIG_SYS_BR1_PRELIM 0xFB001801 /* 32-bit port */
  93. #define CONFIG_SYS_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */
  94. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  95. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  96. #define CONFIG_SYS_RAMBOOT
  97. #else
  98. #undef CONFIG_SYS_RAMBOOT
  99. #endif
  100. #ifdef CONFIG_SYS_RAMBOOT
  101. #define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
  102. #else
  103. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  104. #endif
  105. #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
  106. #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
  107. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  108. /* DDR Setup */
  109. #define CONFIG_FSL_DDR1
  110. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
  111. #define CONFIG_DDR_SPD
  112. #undef CONFIG_FSL_DDR_INTERACTIVE
  113. #undef CONFIG_DDR_ECC /* only for ECC DDR module */
  114. #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
  115. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  116. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  117. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  118. #define CONFIG_NUM_DDR_CONTROLLERS 1
  119. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  120. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  121. /* I2C addresses of SPD EEPROMs */
  122. #define SPD_EEPROM_ADDRESS 0x54 /* CTLR 0 DIMM 0 */
  123. #undef CONFIG_CLOCKS_IN_MHZ
  124. /* local bus definitions */
  125. #define CONFIG_SYS_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
  126. #define CONFIG_SYS_OR2_PRELIM 0xfc006901
  127. #define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq */
  128. #define CONFIG_SYS_LBC_LBCR 0x00000000
  129. #define CONFIG_SYS_LBC_LSRT 0x20000000
  130. #define CONFIG_SYS_LBC_MRTPR 0x20000000
  131. #define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
  132. #define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
  133. #define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
  134. #define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
  135. #define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
  136. #define CONFIG_SYS_INIT_RAM_LOCK 1
  137. #define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
  138. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
  139. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  140. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  141. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  142. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  143. /* Serial Port */
  144. #define CONFIG_CONS_INDEX 2
  145. #define CONFIG_SYS_NS16550
  146. #define CONFIG_SYS_NS16550_SERIAL
  147. #define CONFIG_SYS_NS16550_REG_SIZE 1
  148. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  149. #define CONFIG_SYS_BAUDRATE_TABLE \
  150. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  151. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  152. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  153. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  154. #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
  155. #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
  156. #ifdef CONFIG_SYS_HUSH_PARSER
  157. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  158. #endif
  159. /* pass open firmware flat tree */
  160. #define CONFIG_OF_LIBFDT 1
  161. #define CONFIG_OF_BOARD_SETUP 1
  162. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  163. /*
  164. * I2C
  165. */
  166. #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
  167. #define CONFIG_HARD_I2C /* I2C with hardware support*/
  168. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  169. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  170. #define CONFIG_SYS_I2C_SLAVE 0x7F
  171. #undef CONFIG_SYS_I2C_NOPROBES
  172. #define CONFIG_SYS_I2C_OFFSET 0x3000
  173. /* I2C RTC */
  174. #define CONFIG_RTC_DS1337 /* This is really a DS1339 RTC */
  175. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  176. /* I2C EEPROM. AT24C32, we keep our environment in here.
  177. */
  178. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 /* 1010001x */
  179. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  180. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
  181. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
  182. /*
  183. * Standard 8555 PCI mapping.
  184. * Addresses are mapped 1-1.
  185. */
  186. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  187. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  188. #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
  189. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  190. #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
  191. #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
  192. #define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
  193. #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
  194. #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
  195. #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
  196. #define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000
  197. #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
  198. #if defined(CONFIG_PCI) /* PCI Ethernet card */
  199. #define CONFIG_MPC85XX_PCI2 1
  200. #define CONFIG_NET_MULTI
  201. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  202. #define CONFIG_EEPRO100
  203. #define CONFIG_TULIP
  204. #if !defined(CONFIG_PCI_PNP)
  205. #define PCI_ENET0_IOADDR 0xe0000000
  206. #define PCI_ENET0_MEMADDR 0xe0000000
  207. #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
  208. #endif
  209. #define CONFIG_PCI_SCAN_SHOW
  210. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  211. #endif /* CONFIG_PCI */
  212. #if defined(CONFIG_TSEC_ENET)
  213. #ifndef CONFIG_NET_MULTI
  214. #define CONFIG_NET_MULTI 1
  215. #endif
  216. #define CONFIG_MII 1 /* MII PHY management */
  217. #define CONFIG_TSEC1 1
  218. #define CONFIG_TSEC1_NAME "TSEC0"
  219. #define CONFIG_TSEC2 1
  220. #define CONFIG_TSEC2_NAME "TSEC1"
  221. #define TSEC1_PHY_ADDR 2
  222. #define TSEC2_PHY_ADDR 4
  223. #define TSEC1_PHYIDX 0
  224. #define TSEC2_PHYIDX 0
  225. #define TSEC1_FLAGS TSEC_GIGABIT
  226. #define TSEC2_FLAGS TSEC_GIGABIT
  227. #define CONFIG_ETHPRIME "TSEC0"
  228. #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
  229. #define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
  230. #undef CONFIG_ETHER_NONE /* define if ether on something else */
  231. #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
  232. #if (CONFIG_ETHER_INDEX == 2)
  233. /*
  234. * - Rx-CLK is CLK13
  235. * - Tx-CLK is CLK14
  236. * - Select bus for bd/buffers
  237. * - Full duplex
  238. */
  239. #define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  240. #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  241. #define CONFIG_SYS_CPMFCR_RAMTYPE 0
  242. #if 0
  243. #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
  244. #else
  245. #define CONFIG_SYS_FCC_PSMR 0
  246. #endif
  247. #define FETH2_RST 0x01
  248. #elif (CONFIG_ETHER_INDEX == 3)
  249. /* need more definitions here for FE3 */
  250. #define FETH3_RST 0x80
  251. #endif /* CONFIG_ETHER_INDEX */
  252. /* MDIO is done through the TSEC0 control.
  253. */
  254. #define CONFIG_MII /* MII PHY management */
  255. #undef CONFIG_BITBANGMII /* bit-bang MII PHY management */
  256. #endif
  257. /* Environment - default config is in flash, see below */
  258. #if 0 /* in EEPROM */
  259. # define CONFIG_ENV_IS_IN_EEPROM 1
  260. # define CONFIG_ENV_OFFSET 0
  261. # define CONFIG_ENV_SIZE 2048
  262. #else /* in flash */
  263. # define CONFIG_ENV_IS_IN_FLASH 1
  264. # ifdef CONFIG_STXSSA_4M
  265. # define CONFIG_ENV_SECT_SIZE 0x20000
  266. # else /* default configuration - 64 MiB flash */
  267. # define CONFIG_ENV_SECT_SIZE 0x40000
  268. # endif
  269. # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  270. # define CONFIG_ENV_SIZE 0x4000
  271. # define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
  272. # define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  273. #endif
  274. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  275. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  276. #define CONFIG_TIMESTAMP /* Print image info with ts */
  277. /*
  278. * BOOTP options
  279. */
  280. #define CONFIG_BOOTP_BOOTFILESIZE
  281. #define CONFIG_BOOTP_BOOTPATH
  282. #define CONFIG_BOOTP_GATEWAY
  283. #define CONFIG_BOOTP_HOSTNAME
  284. /*
  285. * Command line configuration.
  286. */
  287. #include <config_cmd_default.h>
  288. #define CONFIG_CMD_DATE
  289. #define CONFIG_CMD_DHCP
  290. #define CONFIG_CMD_EEPROM
  291. #define CONFIG_CMD_I2C
  292. #define CONFIG_CMD_NFS
  293. #define CONFIG_CMD_PING
  294. #define CONFIG_CMD_SNTP
  295. #define CONFIG_CMD_REGINFO
  296. #if defined(CONFIG_PCI)
  297. #define CONFIG_CMD_PCI
  298. #endif
  299. #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
  300. #define CONFIG_CMD_MII
  301. #endif
  302. #if defined(CONFIG_SYS_RAMBOOT)
  303. #undef CONFIG_CMD_SAVEENV
  304. #undef CONFIG_CMD_LOADS
  305. #else
  306. #define CONFIG_CMD_ELF
  307. #endif
  308. #undef CONFIG_WATCHDOG /* watchdog disabled */
  309. /*
  310. * Miscellaneous configurable options
  311. */
  312. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  313. #define CONFIG_SYS_PROMPT "SSA=> " /* Monitor Command Prompt */
  314. #if defined(CONFIG_CMD_KGDB)
  315. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  316. #else
  317. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  318. #endif
  319. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  320. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  321. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  322. #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
  323. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  324. /*
  325. * For booting Linux, the board info and command line data
  326. * have to be in the first 8 MB of memory, since this is
  327. * the maximum mapped by the Linux kernel during initialization.
  328. */
  329. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  330. #if defined(CONFIG_CMD_KGDB)
  331. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  332. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  333. #endif
  334. /*Note: change below for your network setting!!! */
  335. #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
  336. #define CONFIG_HAS_ETH0
  337. #define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
  338. #define CONFIG_HAS_ETH1
  339. #define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
  340. #define CONFIG_HAS_ETH2
  341. #define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c
  342. #endif
  343. /*
  344. * Environment in EEPROM is compatible with different flash sector sizes,
  345. * but only little space is available, so we use a very simple setup.
  346. * With environment in flash, we use a more powerful default configuration.
  347. */
  348. #ifdef CONFIG_ENV_IS_IN_EEPROM /* use restricted "standard" environment */
  349. #define CONFIG_BAUDRATE 38400
  350. #define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
  351. #define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000"
  352. #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
  353. #define CONFIG_SERVERIP 192.168.85.1
  354. #define CONFIG_IPADDR 192.168.85.60
  355. #define CONFIG_GATEWAYIP 192.168.85.1
  356. #define CONFIG_NETMASK 255.255.255.0
  357. #define CONFIG_HOSTNAME STX_SSA
  358. #define CONFIG_ROOTPATH /gppproot
  359. #define CONFIG_BOOTFILE uImage
  360. #define CONFIG_LOADADDR 0x1000000
  361. #else /* ENV IS IN FLASH -- use a full-blown envionment */
  362. #define CONFIG_BAUDRATE 115200
  363. #define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
  364. #define CONFIG_PREBOOT "echo;" \
  365. "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  366. "echo"
  367. #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
  368. #define CONFIG_EXTRA_ENV_SETTINGS \
  369. "hostname=gp3ssa\0" \
  370. "bootfile=/tftpboot/gp3ssa/uImage\0" \
  371. "loadaddr=400000\0" \
  372. "netdev=eth0\0" \
  373. "consdev=ttyS1\0" \
  374. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  375. "nfsroot=$serverip:$rootpath\0" \
  376. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  377. "addip=setenv bootargs $bootargs " \
  378. "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
  379. ":$hostname:$netdev:off panic=1\0" \
  380. "addcons=setenv bootargs $bootargs " \
  381. "console=$consdev,$baudrate\0" \
  382. "flash_nfs=run nfsargs addip addcons;" \
  383. "bootm $kernel_addr\0" \
  384. "flash_self=run ramargs addip addcons;" \
  385. "bootm $kernel_addr $ramdisk_addr\0" \
  386. "net_nfs=tftp $loadaddr $bootfile;" \
  387. "run nfsargs addip addcons;bootm\0" \
  388. "rootpath=/opt/eldk/ppc_85xx\0" \
  389. "kernel_addr=FC000000\0" \
  390. "ramdisk_addr=FC200000\0" \
  391. ""
  392. #define CONFIG_BOOTCOMMAND "run flash_self"
  393. #endif /* CONFIG_ENV_IS_IN_EEPROM */
  394. #endif /* __CONFIG_H */