P1023RDS.h 18 KB

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  1. /*
  2. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  3. *
  4. * Authors: Roy Zang <tie-fei.zang@freescale.com>
  5. * Chunhe Lan <b25806@freescale.com>
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. /*
  26. * p1023rds board configuration file
  27. *
  28. */
  29. #ifndef __CONFIG_H
  30. #define __CONFIG_H
  31. #ifdef CONFIG_NAND
  32. #define CONFIG_NAND_U_BOOT
  33. #define CONFIG_RAMBOOT_NAND
  34. #endif
  35. #ifdef CONFIG_NAND_U_BOOT
  36. #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  37. #define CONFIG_SYS_TEXT_BASE 0x11001000
  38. #ifdef CONFIG_NAND_SPL
  39. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  40. #else
  41. #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
  42. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  43. #endif /* CONFIG_NAND_SPL */
  44. #endif
  45. #ifndef CONFIG_SYS_TEXT_BASE
  46. #define CONFIG_SYS_TEXT_BASE 0xeff80000
  47. #endif
  48. #ifndef CONFIG_SYS_MONITOR_BASE
  49. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  50. #endif
  51. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  52. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  53. #endif
  54. /* High Level Configuration Options */
  55. #define CONFIG_BOOKE /* BOOKE */
  56. #define CONFIG_E500 /* BOOKE e500 family */
  57. #define CONFIG_MPC85xx
  58. #define CONFIG_P1023
  59. #define CONFIG_P1023RDS
  60. #define CONFIG_MP /* support multiple processors */
  61. #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
  62. #define CONFIG_PCI /* Enable PCI/PCIE */
  63. #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
  64. #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
  65. #define CONFIG_PCIE3 /* PCIE controler 3 (slot 3) */
  66. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  67. #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
  68. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  69. #define CONFIG_FSL_LAW /* Use common FSL init code */
  70. #ifndef __ASSEMBLY__
  71. extern unsigned long get_clock_freq(void);
  72. #endif
  73. #define CONFIG_SYS_CLK_FREQ 66666666
  74. #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
  75. /*
  76. * These can be toggled for performance analysis, otherwise use default.
  77. */
  78. #define CONFIG_L2_CACHE /* toggle L2 cache */
  79. #define CONFIG_BTB /* toggle branch predition */
  80. #define CONFIG_HWCONFIG
  81. #define CONFIG_ENABLE_36BIT_PHYS
  82. #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
  83. #define CONFIG_SYS_MEMTEST_END 0x1fffffff /* fix me, only 1G */
  84. #define CONFIG_PANIC_HANG /* do not reset board on panic */
  85. #define CONFIG_SYS_LBC_LBCR 0x00000000 /* Implement conversion of
  86. addresses in the LBC */
  87. /*
  88. * Base addresses -- Note these are effective addresses where the
  89. * actual resources get mapped (not physical addresses)
  90. */
  91. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 /* CCSRBAR Default */
  92. #define CONFIG_SYS_CCSRBAR 0xff600000 /* relocated CCSRBAR */
  93. /* physical addr of CCSRBAR */
  94. #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
  95. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  96. /* DDR Setup */
  97. #define CONFIG_VERY_BIG_RAM
  98. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  99. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  100. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  101. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  102. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  103. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  104. /* These are used when DDR doesn't use SPD. */
  105. #define CONFIG_SYS_SDRAM_SIZE 2048u /* DDR is 2GB */
  106. /* Default settings for "stable" mode */
  107. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
  108. #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
  109. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
  110. #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
  111. #define CONFIG_SYS_DDR_TIMING_3 0x00020000
  112. #define CONFIG_SYS_DDR_TIMING_0 0x40110104
  113. #define CONFIG_SYS_DDR_TIMING_1 0x5C59E544
  114. #define CONFIG_SYS_DDR_TIMING_2 0x0fA888CA
  115. #define CONFIG_SYS_DDR_MODE_1 0x00441210
  116. #define CONFIG_SYS_DDR_MODE_2 0x00000000
  117. #define CONFIG_SYS_DDR_MODE_CTRL 0x00000000
  118. #define CONFIG_SYS_DDR_INTERVAL 0x0A280100
  119. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  120. #define CONFIG_SYS_DDR_CLK_CTRL 0x01800000
  121. #define CONFIG_SYS_DDR_TIMING_4 0x00000001
  122. #define CONFIG_SYS_DDR_TIMING_5 0x01401400
  123. #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
  124. #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F605
  125. #define CONFIG_SYS_DDR_CONTROL 0xC70C0008 /* Type = DDR3: No Interleaving */
  126. #define CONFIG_SYS_DDR_CONTROL2 0x24401010
  127. #define CONFIG_SYS_DDR_CDR1 0x00000000
  128. #define CONFIG_SYS_DDR_CDR2 0x00000000
  129. #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000
  130. #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
  131. #define CONFIG_SYS_DDR_SBE 0x00000000
  132. /* Settings that differ for "performance" mode */
  133. #define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */
  134. #define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */
  135. #define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014302
  136. #define CONFIG_SYS_DDR_TIMING_1_PERF 0x5C58E544
  137. #define CONFIG_SYS_DDR_TIMING_2_PERF 0x0FA888CA
  138. /* Type = DDR3: cs0-cs1 interleaving */
  139. #define CONFIG_SYS_DDR_CONTROL_PERF 0xC70C4008
  140. #define CONFIG_SYS_DDR_CDR_1 0x00000000
  141. #define CONFIG_SYS_DDR_CDR_2 0x00000000
  142. /*
  143. * Memory map
  144. *
  145. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  146. * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
  147. * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
  148. * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
  149. *
  150. * Localbus non-cacheable
  151. * 0xe000_0000 0xe003_ffff BCSR 256K BCSR
  152. * 0xee00_0000 0xefff_ffff NOR flash 32M NOR flash
  153. * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M
  154. * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
  155. * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
  156. * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
  157. */
  158. /*
  159. * Local Bus Definitions
  160. */
  161. #define CONFIG_SYS_BCSR_BASE 0xe0000000 /* start of on board FPGA */
  162. #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
  163. #ifndef CONFIG_NAND
  164. #define CONFIG_SYS_FLASH_BASE 0xee000000 /* start of FLASH 32M */
  165. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  166. #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
  167. | BR_PS_16 | BR_V)
  168. #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
  169. #define CONFIG_FLASH_CFI_DRIVER
  170. #define CONFIG_SYS_FLASH_CFI
  171. #define CONFIG_SYS_FLASH_EMPTY_INFO
  172. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  173. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
  174. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  175. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  176. #else
  177. #define CONFIG_SYS_NO_FLASH
  178. #endif
  179. #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
  180. #define CONFIG_SYS_RAMBOOT
  181. #endif
  182. #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f function */
  183. #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
  184. #define CONFIG_SYS_INIT_RAM_LOCK
  185. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
  186. #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
  187. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
  188. #define CONFIG_SYS_GBL_DATA_OFFSET \
  189. (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  190. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  191. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  192. #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
  193. #ifndef CONFIG_NAND_SPL
  194. #define CONFIG_SYS_NAND_BASE 0xffa00000
  195. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  196. #else
  197. #define CONFIG_SYS_NAND_BASE 0xfff00000
  198. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  199. #endif
  200. #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
  201. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  202. #define CONFIG_MTD_NAND_VERIFY_WRITE
  203. #define CONFIG_CMD_NAND
  204. #define CONFIG_NAND_FSL_ELBC
  205. #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
  206. /* NAND boot: 4K NAND loader config */
  207. #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
  208. #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SYS_NAND_SPL_SIZE)
  209. #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
  210. #define CONFIG_SYS_NAND_U_BOOT_START 0x11000000
  211. #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
  212. #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  213. #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
  214. /* NAND flash config */
  215. #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  216. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  217. | BR_PS_8 /* Port Size = 8bit */ \
  218. | BR_MS_FCM /* MSEL = FCM */ \
  219. | BR_V) /* valid */
  220. #define CONFIG_SYS_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
  221. | OR_FCM_CSCT \
  222. | OR_FCM_CST \
  223. | OR_FCM_CHT \
  224. | OR_FCM_SCY_1 \
  225. | OR_FCM_TRLX \
  226. | OR_FCM_EHTR)
  227. #ifdef CONFIG_RAMBOOT_NAND
  228. /* NAND Base Address */
  229. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
  230. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  231. /* chip select 1 - BCSR */
  232. #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \
  233. | BR_MS_GPCM | BR_PS_8 | BR_V)
  234. #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
  235. | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
  236. | OR_GPCM_EAD)
  237. #else
  238. #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  239. #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  240. /* chip select 1 - BCSR */
  241. #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \
  242. | BR_MS_GPCM | BR_PS_8 | BR_V)
  243. #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
  244. | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
  245. | OR_GPCM_EAD)
  246. #endif
  247. /* Serial Port
  248. * open - index 2
  249. * shorted - index 1
  250. */
  251. #define CONFIG_CONS_INDEX 1
  252. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  253. #define CONFIG_SYS_NS16550
  254. #define CONFIG_SYS_NS16550_SERIAL
  255. #define CONFIG_SYS_NS16550_REG_SIZE 1
  256. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  257. #ifdef CONFIG_NAND_SPL
  258. #define CONFIG_NS16550_MIN_FUNCTIONS
  259. #endif
  260. #define CONFIG_SYS_BAUDRATE_TABLE \
  261. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  262. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
  263. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
  264. /* Use the HUSH parser */
  265. #define CONFIG_SYS_HUSH_PARSER
  266. #ifdef CONFIG_SYS_HUSH_PARSER
  267. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  268. #endif
  269. /*
  270. * Pass open firmware flat tree
  271. */
  272. #define CONFIG_OF_LIBFDT
  273. #define CONFIG_OF_BOARD_SETUP
  274. #define CONFIG_OF_STDOUT_VIA_ALIAS
  275. #define CONFIG_SYS_64BIT_VSPRINTF
  276. #define CONFIG_SYS_64BIT_STRTOUL
  277. /* new uImage format support */
  278. #define CONFIG_FIT
  279. #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
  280. /* I2C */
  281. #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
  282. #define CONFIG_HARD_I2C /* I2C with hardware support */
  283. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  284. #define CONFIG_I2C_MULTI_BUS
  285. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  286. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
  287. #define CONFIG_SYS_I2C_SLAVE 0x7F
  288. #define CONFIG_SYS_I2C_OFFSET 0x3000
  289. #define CONFIG_SYS_I2C2_OFFSET 0x3100
  290. /*
  291. * I2C2 EEPROM
  292. */
  293. #define CONFIG_ID_EEPROM
  294. #ifdef CONFIG_ID_EEPROM
  295. #define CONFIG_SYS_I2C_EEPROM_NXID
  296. #endif
  297. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
  298. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  299. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  300. #define CONFIG_CMD_I2C
  301. /*
  302. * eSPI - Enhanced SPI
  303. */
  304. #define CONFIG_SPI_FLASH
  305. #define CONFIG_SPI_FLASH_ATMEL
  306. #define CONFIG_HARD_SPI
  307. #define CONFIG_FSL_ESPI
  308. #define CONFIG_CMD_SF
  309. #define CONFIG_SF_DEFAULT_SPEED 10000000
  310. #define CONFIG_SF_DEFAULT_MODE 0
  311. /*
  312. * General PCI
  313. * Memory space is mapped 1-1, but I/O space must start from 0.
  314. */
  315. /* controller 3, Slot 1, tgtid 3, Base address b000 */
  316. #define CONFIG_SYS_PCIE3_NAME "Slot 3"
  317. #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
  318. #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
  319. #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
  320. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  321. #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
  322. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  323. #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
  324. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  325. /* controller 2, direct to uli, tgtid 2, Base address 9000 */
  326. #define CONFIG_SYS_PCIE2_NAME "Slot 2"
  327. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  328. #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  329. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  330. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  331. #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
  332. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  333. #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
  334. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  335. /* controller 1, Slot 2, tgtid 1, Base address a000 */
  336. #define CONFIG_SYS_PCIE1_NAME "Slot 1"
  337. #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
  338. #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
  339. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
  340. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  341. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
  342. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  343. #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
  344. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  345. #if defined(CONFIG_PCI)
  346. #define CONFIG_E1000 /* Defind e1000 pci Ethernet card */
  347. #define CONFIG_NET_MULTI
  348. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  349. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  350. #endif /* CONFIG_PCI */
  351. #ifndef CONFIG_NET_MULTI
  352. #define CONFIG_NET_MULTI
  353. #endif
  354. /*
  355. * Environment
  356. */
  357. #define CONFIG_ENV_OVERWRITE
  358. #if defined(CONFIG_SYS_RAMBOOT)
  359. #if defined(CONFIG_RAMBOOT_NAND)
  360. #define CONFIG_ENV_IS_IN_NAND
  361. #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
  362. #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
  363. #else
  364. #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
  365. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x4000)
  366. #define CONFIG_ENV_SIZE 0x2000
  367. #endif
  368. #else
  369. #define CONFIG_ENV_IS_IN_FLASH
  370. #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
  371. #define CONFIG_ENV_ADDR 0xfff80000
  372. #else
  373. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  374. #endif
  375. #define CONFIG_ENV_SIZE 0x2000
  376. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  377. #endif
  378. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  379. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  380. /*
  381. * Command line configuration.
  382. */
  383. #include <config_cmd_default.h>
  384. #define CONFIG_CMD_IRQ
  385. #define CONFIG_CMD_PING
  386. #define CONFIG_CMD_MII
  387. #define CONFIG_CMD_ELF
  388. #define CONFIG_CMD_SETEXPR
  389. #define CONFIG_CMD_REGINFO
  390. #if defined(CONFIG_PCI)
  391. #define CONFIG_CMD_PCI
  392. #define CONFIG_CMD_NET
  393. #endif
  394. /*
  395. * USB
  396. */
  397. #define CONFIG_USB_EHCI
  398. #ifdef CONFIG_USB_EHCI
  399. #define CONFIG_CMD_USB
  400. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  401. #define CONFIG_USB_EHCI_FSL
  402. #define CONFIG_USB_STORAGE
  403. #define CONFIG_CMD_FAT
  404. #define CONFIG_CMD_EXT2
  405. #define CONFIG_CMD_FAT
  406. #define CONFIG_DOS_PARTITION
  407. #endif
  408. /*
  409. * Miscellaneous configurable options
  410. */
  411. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  412. #define CONFIG_CMDLINE_EDITING /* Command-line editing */
  413. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  414. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  415. #if defined(CONFIG_CMD_KGDB)
  416. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  417. #else
  418. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  419. #endif
  420. /* Print Buffer Size */
  421. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
  422. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  423. /* Boot Argument Buffer Size */
  424. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  425. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  426. /*
  427. * For booting Linux, the board info and command line data
  428. * have to be in the first 16 MB of memory, since this is
  429. * the maximum mapped by the Linux kernel during initialization.
  430. */
  431. #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
  432. #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
  433. #if defined(CONFIG_CMD_KGDB)
  434. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  435. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  436. #endif
  437. /*
  438. * Environment Configuration
  439. */
  440. #define CONFIG_BOOTFILE uImage
  441. #define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */
  442. /* default location for tftp and bootm */
  443. #define CONFIG_LOADADDR 1000000
  444. #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  445. #define CONFIG_BAUDRATE 115200
  446. /* Qman/Bman */
  447. #define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */
  448. #define CONFIG_SYS_QMAN_MEM_BASE 0xff000000
  449. #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
  450. #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
  451. #define CONFIG_SYS_BMAN_MEM_BASE 0xff200000
  452. #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
  453. #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
  454. /* For FM */
  455. #define CONFIG_SYS_DPAA_FMAN
  456. #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
  457. #ifdef CONFIG_SYS_DPAA_FMAN
  458. #define CONFIG_FMAN_ENET
  459. #endif
  460. #define CONFIG_SYS_FMAN_FW
  461. #ifndef CONFIG_NAND
  462. /* Default address of microcode for the Linux Fman driver */
  463. /* QE microcode/firmware address */
  464. #define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000
  465. #else
  466. #define CONFIG_SYS_QE_FW_IN_NAND 0x1f00000
  467. #endif
  468. #define CONFIG_SYS_FMAN_FW_LENGTH 0x10000
  469. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH)
  470. #ifdef CONFIG_FMAN_ENET
  471. #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
  472. #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x7
  473. #define CONFIG_SYS_TBIPA_VALUE 8
  474. #define CONFIG_MII /* MII PHY management */
  475. #define CONFIG_ETHPRIME "FM1@DTSEC1"
  476. #endif
  477. #define CONFIG_EXTRA_ENV_SETTINGS \
  478. "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
  479. #endif /* __CONFIG_H */