stxssa.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384
  1. /*
  2. * (C) Copyright 2005, Embedded Alley Solutions, Inc.
  3. * Dan Malek, <dan@embeddedalley.com>
  4. * Copied from STx GP3.
  5. * Updates for Silicon Tx GP3 SSA
  6. *
  7. * (C) Copyright 2003,Motorola Inc.
  8. * Xianghua Xiao, (X.Xiao@motorola.com)
  9. *
  10. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  11. *
  12. * See file CREDITS for list of people who contributed to this
  13. * project.
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation; either version 2 of
  18. * the License, or (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28. * MA 02111-1307 USA
  29. */
  30. #include <common.h>
  31. #include <pci.h>
  32. #include <asm/processor.h>
  33. #include <asm/mmu.h>
  34. #include <asm/immap_85xx.h>
  35. #include <asm/fsl_pci.h>
  36. #include <asm/fsl_ddr_sdram.h>
  37. #include <ioports.h>
  38. #include <asm/io.h>
  39. #include <spd_sdram.h>
  40. #include <miiphy.h>
  41. #include <netdev.h>
  42. /*
  43. * I/O Port configuration table
  44. *
  45. * if conf is 1, then that port pin will be configured at boot time
  46. * according to the five values podr/pdir/ppar/psor/pdat for that entry
  47. */
  48. const iop_conf_t iop_conf_tab[4][32] = {
  49. /* Port A configuration */
  50. { /* conf ppar psor pdir podr pdat */
  51. /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
  52. /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
  53. /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
  54. /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
  55. /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
  56. /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
  57. /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
  58. /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
  59. /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
  60. /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
  61. /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
  62. /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
  63. /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
  64. /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
  65. /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
  66. /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
  67. /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
  68. /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
  69. /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
  70. /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
  71. /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
  72. /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
  73. /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
  74. /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
  75. /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
  76. /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
  77. /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
  78. /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
  79. /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
  80. /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
  81. /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
  82. /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
  83. },
  84. /* Port B configuration */
  85. { /* conf ppar psor pdir podr pdat */
  86. /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
  87. /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
  88. /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
  89. /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
  90. /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
  91. /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
  92. /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
  93. /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
  94. /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
  95. /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
  96. /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
  97. /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
  98. /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
  99. /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
  100. /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
  101. /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
  102. /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
  103. /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
  104. /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
  105. /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
  106. /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
  107. /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
  108. /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
  109. /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
  110. /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
  111. /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
  112. /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
  113. /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
  114. /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  115. /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  116. /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  117. /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
  118. },
  119. /* Port C */
  120. { /* conf ppar psor pdir podr pdat */
  121. /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
  122. /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
  123. /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
  124. /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
  125. /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
  126. /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
  127. /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
  128. /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
  129. /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
  130. /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
  131. /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
  132. /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
  133. /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
  134. /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
  135. /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
  136. /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
  137. /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
  138. /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
  139. /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
  140. /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
  141. /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
  142. /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
  143. /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
  144. /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
  145. /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
  146. /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
  147. /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
  148. /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
  149. /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
  150. /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
  151. /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
  152. /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
  153. },
  154. /* Port D */
  155. { /* conf ppar psor pdir podr pdat */
  156. /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
  157. /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
  158. /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
  159. /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
  160. /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */
  161. /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
  162. /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
  163. /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
  164. /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
  165. /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
  166. /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
  167. /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
  168. /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
  169. /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
  170. /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
  171. /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
  172. /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
  173. /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */
  174. /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
  175. /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
  176. /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
  177. /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
  178. /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
  179. /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
  180. /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
  181. /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
  182. /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
  183. /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
  184. /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  185. /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  186. /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  187. /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
  188. }
  189. };
  190. static uint64_t next_led_update;
  191. static uint led_bit;
  192. void
  193. reset_phy(void)
  194. {
  195. volatile uint *blatch;
  196. #if 0
  197. int i;
  198. #endif
  199. blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE;
  200. /* reset Giga bit Ethernet port if needed here */
  201. #if 1
  202. *blatch &= ~0x000000c0;
  203. udelay(100);
  204. #else
  205. *blatch = 0;
  206. asm("eieio");
  207. for (i=0; i<1000; i++)
  208. udelay(1000);
  209. #endif
  210. *blatch = 0x000000c1; /* Light one led, too */
  211. udelay(1000);
  212. #if 0 /* This is the port we really want to use for debugging. */
  213. /* reset the CPM FEC port */
  214. #if (CONFIG_ETHER_INDEX == 2)
  215. bcsr->bcsr2 &= ~FETH2_RST;
  216. udelay(2);
  217. bcsr->bcsr2 |= FETH2_RST;
  218. udelay(1000);
  219. #elif (CONFIG_ETHER_INDEX == 3)
  220. bcsr->bcsr3 &= ~FETH3_RST;
  221. udelay(2);
  222. bcsr->bcsr3 |= FETH3_RST;
  223. udelay(1000);
  224. #endif
  225. #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
  226. /* reset PHY */
  227. miiphy_reset("FCC1", 0x0);
  228. /* change PHY address to 0x02 */
  229. bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);
  230. bb_miiphy_write(NULL, 0x02, MII_BMCR,
  231. BMCR_ANENABLE | BMCR_ANRESTART);
  232. #endif /* CONFIG_MII */
  233. #endif
  234. }
  235. #ifdef CONFIG_OF_BOARD_SETUP
  236. void ft_board_setup(void *blob, bd_t *bd)
  237. {
  238. ft_cpu_setup (blob, bd);
  239. }
  240. #endif /* CONFIG_OF_BOARD_SETUP */
  241. int
  242. board_early_init_f(void)
  243. {
  244. #if defined(CONFIG_PCI)
  245. volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
  246. pci->peer &= 0xffffffdf; /* disable master abort */
  247. #endif
  248. /* Why is the phy reset done _after_ the ethernet
  249. * initialization in arch/powerpc/lib/board.c?
  250. * Do it here so it's done before the TSECs are used.
  251. */
  252. reset_phy();
  253. return 0;
  254. }
  255. int
  256. checkboard(void)
  257. {
  258. printf ("Board: Silicon Tx GPPP SSA Board\n");
  259. return (0);
  260. }
  261. /* Blinkin' LEDS for Robert.
  262. */
  263. void
  264. show_activity(int flag)
  265. {
  266. volatile uint *blatch;
  267. if (next_led_update > get_ticks())
  268. return;
  269. blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE;
  270. led_bit >>= 1;
  271. if (led_bit == 0)
  272. led_bit = 0x08;
  273. *blatch = (0xc0 | led_bit);
  274. eieio();
  275. next_led_update += (get_tbclk() / 4);
  276. }
  277. #if defined(CONFIG_SYS_DRAM_TEST)
  278. int testdram (void)
  279. {
  280. uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
  281. uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
  282. uint *p;
  283. printf("SDRAM test phase 1:\n");
  284. for (p = pstart; p < pend; p++)
  285. *p = 0xaaaaaaaa;
  286. for (p = pstart; p < pend; p++) {
  287. if (*p != 0xaaaaaaaa) {
  288. printf ("SDRAM test fails at: %08x\n", (uint) p);
  289. return 1;
  290. }
  291. }
  292. printf("SDRAM test phase 2:\n");
  293. for (p = pstart; p < pend; p++)
  294. *p = 0x55555555;
  295. for (p = pstart; p < pend; p++) {
  296. if (*p != 0x55555555) {
  297. printf ("SDRAM test fails at: %08x\n", (uint) p);
  298. return 1;
  299. }
  300. }
  301. printf("SDRAM test passed.\n");
  302. return 0;
  303. }
  304. #endif
  305. #if defined(CONFIG_PCI)
  306. /*
  307. * Initialize PCI Devices, report devices found.
  308. */
  309. #ifndef CONFIG_PCI_PNP
  310. static struct pci_config_table pci_stxgp3_config_table[] = {
  311. { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  312. PCI_IDSEL_NUMBER, PCI_ANY_ID,
  313. pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
  314. PCI_ENET0_MEMADDR,
  315. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
  316. } },
  317. { }
  318. };
  319. #endif
  320. static struct pci_controller hose[] = {
  321. #ifndef CONFIG_PCI_PNP
  322. { config_table: pci_stxgp3_config_table,},
  323. #else
  324. {},
  325. #endif
  326. #ifdef CONFIG_MPC85XX_PCI2
  327. {},
  328. #endif
  329. };
  330. #endif /* CONFIG_PCI */
  331. void
  332. pci_init_board(void)
  333. {
  334. #ifdef CONFIG_PCI
  335. extern void pci_mpc85xx_init(struct pci_controller *hose);
  336. pci_mpc85xx_init(hose);
  337. #endif /* CONFIG_PCI */
  338. }
  339. int board_eth_init(bd_t *bis)
  340. {
  341. cpu_eth_init(bis); /* Initialize TSECs first */
  342. return pci_eth_init(bis);
  343. }