sbc8641d.c 6.5 KB

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  1. /*
  2. * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
  3. * Copyright 2007 Embedded Specialties, Inc.
  4. * Joe Hamman joe.hamman@embeddedspecialties.com
  5. *
  6. * Copyright 2004 Freescale Semiconductor.
  7. * Jeff Brown
  8. * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  9. *
  10. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  11. *
  12. * See file CREDITS for list of people who contributed to this
  13. * project.
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation; either version 2 of
  18. * the License, or (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28. * MA 02111-1307 USA
  29. */
  30. #include <common.h>
  31. #include <command.h>
  32. #include <pci.h>
  33. #include <asm/processor.h>
  34. #include <asm/immap_86xx.h>
  35. #include <asm/fsl_pci.h>
  36. #include <asm/fsl_ddr_sdram.h>
  37. #include <asm/fsl_serdes.h>
  38. #include <libfdt.h>
  39. #include <fdt_support.h>
  40. long int fixed_sdram (void);
  41. int board_early_init_f (void)
  42. {
  43. return 0;
  44. }
  45. int checkboard (void)
  46. {
  47. puts ("Board: Wind River SBC8641D\n");
  48. return 0;
  49. }
  50. phys_size_t initdram (int board_type)
  51. {
  52. long dram_size = 0;
  53. #if defined(CONFIG_SPD_EEPROM)
  54. dram_size = fsl_ddr_sdram();
  55. #else
  56. dram_size = fixed_sdram ();
  57. #endif
  58. debug (" DDR: ");
  59. return dram_size;
  60. }
  61. #if defined(CONFIG_SYS_DRAM_TEST)
  62. int testdram (void)
  63. {
  64. uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
  65. uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
  66. uint *p;
  67. puts ("SDRAM test phase 1:\n");
  68. for (p = pstart; p < pend; p++)
  69. *p = 0xaaaaaaaa;
  70. for (p = pstart; p < pend; p++) {
  71. if (*p != 0xaaaaaaaa) {
  72. printf ("SDRAM test fails at: %08x\n", (uint) p);
  73. return 1;
  74. }
  75. }
  76. puts ("SDRAM test phase 2:\n");
  77. for (p = pstart; p < pend; p++)
  78. *p = 0x55555555;
  79. for (p = pstart; p < pend; p++) {
  80. if (*p != 0x55555555) {
  81. printf ("SDRAM test fails at: %08x\n", (uint) p);
  82. return 1;
  83. }
  84. }
  85. puts ("SDRAM test passed.\n");
  86. return 0;
  87. }
  88. #endif
  89. #if !defined(CONFIG_SPD_EEPROM)
  90. /*
  91. * Fixed sdram init -- doesn't use serial presence detect.
  92. */
  93. long int fixed_sdram (void)
  94. {
  95. #if !defined(CONFIG_SYS_RAMBOOT)
  96. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  97. volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
  98. ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  99. ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
  100. ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
  101. ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
  102. ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  103. ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
  104. ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
  105. ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
  106. ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  107. ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  108. ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  109. ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  110. ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
  111. ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
  112. ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
  113. ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
  114. ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL;
  115. ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  116. ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
  117. ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
  118. asm ("sync;isync");
  119. udelay (500);
  120. ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
  121. asm ("sync; isync");
  122. udelay (500);
  123. ddr = &immap->im_ddr2;
  124. ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
  125. ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
  126. ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
  127. ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
  128. ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
  129. ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
  130. ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
  131. ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
  132. ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
  133. ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
  134. ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
  135. ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
  136. ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
  137. ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
  138. ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
  139. ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
  140. ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL;
  141. ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
  142. ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
  143. ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
  144. asm ("sync;isync");
  145. udelay (500);
  146. ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
  147. asm ("sync; isync");
  148. udelay (500);
  149. #endif
  150. return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  151. }
  152. #endif /* !defined(CONFIG_SPD_EEPROM) */
  153. #if defined(CONFIG_PCI)
  154. /*
  155. * Initialize PCI Devices, report devices found.
  156. */
  157. void pci_init_board(void)
  158. {
  159. fsl_pcie_init_board(0);
  160. }
  161. #endif /* CONFIG_PCI */
  162. #if defined(CONFIG_OF_BOARD_SETUP)
  163. void ft_board_setup (void *blob, bd_t *bd)
  164. {
  165. ft_cpu_setup(blob, bd);
  166. FT_FSL_PCI_SETUP;
  167. }
  168. #endif
  169. void sbc8641d_reset_board (void)
  170. {
  171. puts ("Resetting board....\n");
  172. }
  173. /*
  174. * get_board_sys_clk
  175. * Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
  176. */
  177. unsigned long get_board_sys_clk (ulong dummy)
  178. {
  179. int i;
  180. ulong val = 0;
  181. i = 5;
  182. i &= 0x07;
  183. switch (i) {
  184. case 0:
  185. val = 33000000;
  186. break;
  187. case 1:
  188. val = 40000000;
  189. break;
  190. case 2:
  191. val = 50000000;
  192. break;
  193. case 3:
  194. val = 66000000;
  195. break;
  196. case 4:
  197. val = 83000000;
  198. break;
  199. case 5:
  200. val = 100000000;
  201. break;
  202. case 6:
  203. val = 134000000;
  204. break;
  205. case 7:
  206. val = 166000000;
  207. break;
  208. }
  209. return val;
  210. }
  211. void board_reset(void)
  212. {
  213. #ifdef CONFIG_SYS_RESET_ADDRESS
  214. ulong addr = CONFIG_SYS_RESET_ADDRESS;
  215. /* flush and disable I/D cache */
  216. __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
  217. __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
  218. __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
  219. __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
  220. __asm__ __volatile__ ("sync");
  221. __asm__ __volatile__ ("mtspr 1008, 4");
  222. __asm__ __volatile__ ("isync");
  223. __asm__ __volatile__ ("sync");
  224. __asm__ __volatile__ ("mtspr 1008, 5");
  225. __asm__ __volatile__ ("isync");
  226. __asm__ __volatile__ ("sync");
  227. /*
  228. * SRR0 has system reset vector, SRR1 has default MSR value
  229. * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
  230. */
  231. __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
  232. __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
  233. __asm__ __volatile__ ("mtspr 27, 4");
  234. __asm__ __volatile__ ("rfi");
  235. #endif
  236. }