ddr.c 2.6 KB

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  1. /*
  2. * Copyright 2011 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * Version 2 as published by the Free Software Foundation.
  7. */
  8. #include <common.h>
  9. #include <i2c.h>
  10. #include <hwconfig.h>
  11. #include <asm/mmu.h>
  12. #include <asm/fsl_ddr_sdram.h>
  13. #include <asm/fsl_ddr_dimm_params.h>
  14. #include <asm/fsl_law.h>
  15. typedef struct {
  16. u32 datarate_mhz_low;
  17. u32 datarate_mhz_high;
  18. u32 n_ranks;
  19. u32 clk_adjust;
  20. u32 wrlvl_start;
  21. u32 cpo;
  22. u32 write_data_delay;
  23. u32 force_2T;
  24. } board_specific_parameters_t;
  25. /*
  26. * ranges for parameters:
  27. * wr_data_delay = 0-6
  28. * clk adjust = 0-8
  29. * cpo 2-0x1E (30)
  30. */
  31. const board_specific_parameters_t board_specific_parameters[] = {
  32. /*
  33. * memory controller 0
  34. * lo| hi| num| clk| wrlvl | cpo |wrdata|2T
  35. * mhz| mhz|ranks|adjst| start | delay|
  36. */
  37. { 1017, 1116, 2, 4, 6, 0xff, 2, 0},
  38. };
  39. void fsl_ddr_board_options(memctl_options_t *popts,
  40. dimm_params_t *pdimm,
  41. unsigned int ctrl_num)
  42. {
  43. const board_specific_parameters_t *pbsp =
  44. &board_specific_parameters[0];
  45. u32 num_params = ARRAY_SIZE(board_specific_parameters);
  46. u32 i;
  47. ulong ddr_freq;
  48. /*
  49. * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
  50. * freqency and n_banks specified in board_specific_parameters table.
  51. */
  52. ddr_freq = get_ddr_freq(0) / 1000000;
  53. for (i = 0; i < num_params; i++) {
  54. if (ddr_freq >= pbsp->datarate_mhz_low &&
  55. ddr_freq <= pbsp->datarate_mhz_high &&
  56. pdimm[0].n_ranks == pbsp->n_ranks) {
  57. popts->cpo_override = pbsp->cpo;
  58. popts->write_data_delay = pbsp->write_data_delay;
  59. popts->clk_adjust = pbsp->clk_adjust;
  60. popts->wrlvl_start = pbsp->wrlvl_start;
  61. popts->twoT_en = pbsp->force_2T;
  62. break;
  63. }
  64. pbsp++;
  65. }
  66. if (i == num_params) {
  67. printf("Warning: board specific timing not found "
  68. "for data rate %lu MT/s!\n", ddr_freq);
  69. }
  70. /*
  71. * Factors to consider for half-strength driver enable:
  72. * - number of DIMMs installed
  73. */
  74. popts->half_strength_driver_enable = 0;
  75. /* Write leveling override */
  76. popts->wrlvl_override = 1;
  77. popts->wrlvl_sample = 0xf;
  78. /* Rtt and Rtt_WR override */
  79. popts->rtt_override = 0;
  80. /* Enable ZQ calibration */
  81. popts->zq_en = 1;
  82. /* DHC_EN =1, ODT = 60 Ohm */
  83. popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
  84. }
  85. phys_size_t initdram(int board_type)
  86. {
  87. phys_size_t dram_size = 0;
  88. puts("Initializing....");
  89. if (fsl_use_spd()) {
  90. puts("using SPD\n");
  91. dram_size = fsl_ddr_sdram();
  92. } else {
  93. puts("no SPD and fixed parameters\n");
  94. return dram_size;
  95. }
  96. dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  97. dram_size *= 0x100000;
  98. debug(" DDR: ");
  99. return dram_size;
  100. }