mpc8641hpcn.c 5.6 KB

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  1. /*
  2. * Copyright 2006, 2007, 2010-2011 Freescale Semiconductor.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #include <common.h>
  23. #include <pci.h>
  24. #include <asm/processor.h>
  25. #include <asm/immap_86xx.h>
  26. #include <asm/fsl_pci.h>
  27. #include <asm/fsl_ddr_sdram.h>
  28. #include <asm/fsl_serdes.h>
  29. #include <asm/io.h>
  30. #include <libfdt.h>
  31. #include <fdt_support.h>
  32. #include <netdev.h>
  33. phys_size_t fixed_sdram(void);
  34. int checkboard(void)
  35. {
  36. u8 vboot;
  37. u8 *pixis_base = (u8 *)PIXIS_BASE;
  38. printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
  39. "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  40. in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
  41. in_8(pixis_base + PIXIS_PVER));
  42. vboot = in_8(pixis_base + PIXIS_VBOOT);
  43. if (vboot & PIXIS_VBOOT_FMAP)
  44. printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
  45. else
  46. puts ("Promjet\n");
  47. #ifdef CONFIG_PHYS_64BIT
  48. printf (" 36-bit physical address map\n");
  49. #endif
  50. return 0;
  51. }
  52. phys_size_t
  53. initdram(int board_type)
  54. {
  55. phys_size_t dram_size = 0;
  56. #if defined(CONFIG_SPD_EEPROM)
  57. dram_size = fsl_ddr_sdram();
  58. #else
  59. dram_size = fixed_sdram();
  60. #endif
  61. setup_ddr_bat(dram_size);
  62. debug(" DDR: ");
  63. return dram_size;
  64. }
  65. #if !defined(CONFIG_SPD_EEPROM)
  66. /*
  67. * Fixed sdram init -- doesn't use serial presence detect.
  68. */
  69. phys_size_t
  70. fixed_sdram(void)
  71. {
  72. #if !defined(CONFIG_SYS_RAMBOOT)
  73. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  74. volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
  75. ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  76. ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  77. ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  78. ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  79. ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  80. ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  81. ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
  82. ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
  83. ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  84. ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
  85. ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
  86. ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
  87. ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
  88. #if defined (CONFIG_DDR_ECC)
  89. ddr->err_disable = 0x0000008D;
  90. ddr->err_sbe = 0x00ff0000;
  91. #endif
  92. asm("sync;isync");
  93. udelay(500);
  94. #if defined (CONFIG_DDR_ECC)
  95. /* Enable ECC checking */
  96. ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
  97. #else
  98. ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
  99. ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
  100. #endif
  101. asm("sync; isync");
  102. udelay(500);
  103. #endif
  104. return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  105. }
  106. #endif /* !defined(CONFIG_SPD_EEPROM) */
  107. void pci_init_board(void)
  108. {
  109. fsl_pcie_init_board(0);
  110. #ifdef CONFIG_PCIE1
  111. /*
  112. * Activate ULI1575 legacy chip by performing a fake
  113. * memory access. Needed to make ULI RTC work.
  114. */
  115. in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
  116. + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
  117. #endif /* CONFIG_PCIE1 */
  118. }
  119. #if defined(CONFIG_OF_BOARD_SETUP)
  120. void
  121. ft_board_setup(void *blob, bd_t *bd)
  122. {
  123. int off;
  124. u64 *tmp;
  125. u32 *addrcells;
  126. ft_cpu_setup(blob, bd);
  127. FT_FSL_PCI_SETUP;
  128. /*
  129. * Warn if it looks like the device tree doesn't match u-boot.
  130. * This is just an estimation, based on the location of CCSR,
  131. * which is defined by the "reg" property in the soc node.
  132. */
  133. off = fdt_path_offset(blob, "/soc8641");
  134. addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
  135. tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
  136. if (tmp) {
  137. u64 addr;
  138. if (addrcells && (*addrcells == 1))
  139. addr = *(u32 *)tmp;
  140. else
  141. addr = *tmp;
  142. if (addr != CONFIG_SYS_CCSRBAR_PHYS)
  143. printf("WARNING: The CCSRBAR address in your .dts "
  144. "does not match the address of the CCSR "
  145. "in u-boot. This means your .dts might "
  146. "be old.\n");
  147. }
  148. }
  149. #endif
  150. /*
  151. * get_board_sys_clk
  152. * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
  153. */
  154. unsigned long
  155. get_board_sys_clk(ulong dummy)
  156. {
  157. u8 i, go_bit, rd_clks;
  158. ulong val = 0;
  159. u8 *pixis_base = (u8 *)PIXIS_BASE;
  160. go_bit = in_8(pixis_base + PIXIS_VCTL);
  161. go_bit &= 0x01;
  162. rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
  163. rd_clks &= 0x1C;
  164. /*
  165. * Only if both go bit and the SCLK bit in VCFGEN0 are set
  166. * should we be using the AUX register. Remember, we also set the
  167. * GO bit to boot from the alternate bank on the on-board flash
  168. */
  169. if (go_bit) {
  170. if (rd_clks == 0x1c)
  171. i = in_8(pixis_base + PIXIS_AUX);
  172. else
  173. i = in_8(pixis_base + PIXIS_SPD);
  174. } else {
  175. i = in_8(pixis_base + PIXIS_SPD);
  176. }
  177. i &= 0x07;
  178. switch (i) {
  179. case 0:
  180. val = 33000000;
  181. break;
  182. case 1:
  183. val = 40000000;
  184. break;
  185. case 2:
  186. val = 50000000;
  187. break;
  188. case 3:
  189. val = 66000000;
  190. break;
  191. case 4:
  192. val = 83000000;
  193. break;
  194. case 5:
  195. val = 100000000;
  196. break;
  197. case 6:
  198. val = 134000000;
  199. break;
  200. case 7:
  201. val = 166000000;
  202. break;
  203. }
  204. return val;
  205. }
  206. int board_eth_init(bd_t *bis)
  207. {
  208. /* Initialize TSECs */
  209. cpu_eth_init(bis);
  210. return pci_eth_init(bis);
  211. }
  212. void board_reset(void)
  213. {
  214. u8 *pixis_base = (u8 *)PIXIS_BASE;
  215. out_8(pixis_base + PIXIS_RST, 0);
  216. while (1)
  217. ;
  218. }