corenet_ds.c 6.3 KB

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  1. /*
  2. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #include <common.h>
  23. #include <command.h>
  24. #include <netdev.h>
  25. #include <linux/compiler.h>
  26. #include <asm/mmu.h>
  27. #include <asm/processor.h>
  28. #include <asm/cache.h>
  29. #include <asm/immap_85xx.h>
  30. #include <asm/fsl_law.h>
  31. #include <asm/fsl_serdes.h>
  32. #include <asm/fsl_portals.h>
  33. #include <asm/fsl_liodn.h>
  34. extern void pci_of_setup(void *blob, bd_t *bd);
  35. #include "../common/ngpixis.h"
  36. DECLARE_GLOBAL_DATA_PTR;
  37. int checkboard (void)
  38. {
  39. u8 sw;
  40. struct cpu_type *cpu = gd->cpu;
  41. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  42. unsigned int i;
  43. printf("Board: %sDS, ", cpu->name);
  44. printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  45. in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
  46. sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
  47. sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
  48. if (sw < 0x8)
  49. printf("vBank: %d\n", sw);
  50. else if (sw == 0x8)
  51. puts("Promjet\n");
  52. else if (sw == 0x9)
  53. puts("NAND\n");
  54. else
  55. printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
  56. #ifdef CONFIG_PHYS_64BIT
  57. puts("36-bit Addressing\n");
  58. #endif
  59. /* Display the RCW, so that no one gets confused as to what RCW
  60. * we're actually using for this boot.
  61. */
  62. puts("Reset Configuration Word (RCW):");
  63. for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
  64. u32 rcw = in_be32(&gur->rcwsr[i]);
  65. if ((i % 4) == 0)
  66. printf("\n %08x:", i * 4);
  67. printf(" %08x", rcw);
  68. }
  69. puts("\n");
  70. /* Display the actual SERDES reference clocks as configured by the
  71. * dip switches on the board. Note that the SWx registers could
  72. * technically be set to force the reference clocks to match the
  73. * values that the SERDES expects (or vice versa). For now, however,
  74. * we just display both values and hope the user notices when they
  75. * don't match.
  76. */
  77. puts("SERDES Reference Clocks: ");
  78. #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS)
  79. sw = in_8(&PIXIS_SW(5));
  80. for (i = 0; i < 3; i++) {
  81. static const char *freq[] = {"100", "125", "156.25", "212.5" };
  82. unsigned int clock = (sw >> (6 - (2 * i))) & 3;
  83. printf("Bank%u=%sMhz ", i+1, freq[clock]);
  84. }
  85. puts("\n");
  86. #else
  87. sw = in_8(&PIXIS_SW(3));
  88. printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100);
  89. printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125");
  90. printf("Bank3=%sMHz\n", (sw & 0x10) ? "156.25" : "125");
  91. #endif
  92. return 0;
  93. }
  94. int board_early_init_f(void)
  95. {
  96. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  97. /*
  98. * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3
  99. * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
  100. * the noise introduced by these unterminated and unused clock pairs.
  101. */
  102. setbits_be32(&gur->ddrclkdr, 0x001B001B);
  103. return 0;
  104. }
  105. int board_early_init_r(void)
  106. {
  107. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  108. const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  109. /*
  110. * Remap Boot flash + PROMJET region to caching-inhibited
  111. * so that flash can be erased properly.
  112. */
  113. /* Flush d-cache and invalidate i-cache of any FLASH data */
  114. flush_dcache();
  115. invalidate_icache();
  116. /* invalidate existing TLB entry for flash + promjet */
  117. disable_tlb(flash_esel);
  118. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
  119. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
  120. 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
  121. set_liodns();
  122. #ifdef CONFIG_SYS_DPAA_QBMAN
  123. setup_portals();
  124. #endif
  125. return 0;
  126. }
  127. static const char *serdes_clock_to_string(u32 clock)
  128. {
  129. switch(clock) {
  130. case SRDS_PLLCR0_RFCK_SEL_100:
  131. return "100";
  132. case SRDS_PLLCR0_RFCK_SEL_125:
  133. return "125";
  134. case SRDS_PLLCR0_RFCK_SEL_156_25:
  135. return "156.25";
  136. default:
  137. return "150";
  138. }
  139. }
  140. #define NUM_SRDS_BANKS 3
  141. int misc_init_r(void)
  142. {
  143. serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  144. u32 actual[NUM_SRDS_BANKS];
  145. unsigned int i;
  146. u8 sw;
  147. #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS)
  148. sw = in_8(&PIXIS_SW(5));
  149. for (i = 0; i < 3; i++) {
  150. unsigned int clock = (sw >> (6 - (2 * i))) & 3;
  151. switch (clock) {
  152. case 0:
  153. actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
  154. break;
  155. case 1:
  156. actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
  157. break;
  158. case 2:
  159. actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
  160. break;
  161. default:
  162. printf("Warning: SDREFCLK%u switch setting of '11' is "
  163. "unsupported\n", i + 1);
  164. break;
  165. }
  166. }
  167. #else
  168. /* Warn if the expected SERDES reference clocks don't match the
  169. * actual reference clocks. This needs to be done after calling
  170. * p4080_erratum_serdes8(), since that function may modify the clocks.
  171. */
  172. sw = in_8(&PIXIS_SW(3));
  173. actual[0] = (sw & 0x40) ?
  174. SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100;
  175. actual[1] = (sw & 0x20) ?
  176. SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
  177. actual[2] = (sw & 0x10) ?
  178. SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
  179. #endif
  180. for (i = 0; i < NUM_SRDS_BANKS; i++) {
  181. u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
  182. if (expected != actual[i]) {
  183. printf("Warning: SERDES bank %u expects reference clock"
  184. " %sMHz, but actual is %sMHz\n", i + 1,
  185. serdes_clock_to_string(expected),
  186. serdes_clock_to_string(actual[i]));
  187. }
  188. }
  189. return 0;
  190. }
  191. void ft_board_setup(void *blob, bd_t *bd)
  192. {
  193. phys_addr_t base;
  194. phys_size_t size;
  195. ft_cpu_setup(blob, bd);
  196. base = getenv_bootm_low();
  197. size = getenv_bootm_size();
  198. fdt_fixup_memory(blob, (u64)base, (u64)size);
  199. #ifdef CONFIG_PCI
  200. pci_of_setup(blob, bd);
  201. #endif
  202. fdt_fixup_liodn(blob);
  203. fdt_fixup_dr_usb(blob, bd);
  204. }
  205. int board_eth_init(bd_t *bis)
  206. {
  207. return pci_eth_init(bis);
  208. }