immap_85xx.h 79 KB

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  1. /*
  2. * MPC85xx Internal Memory Map
  3. *
  4. * Copyright 2007-2011 Freescale Semiconductor, Inc.
  5. *
  6. * Copyright(c) 2002,2003 Motorola Inc.
  7. * Xianghua Xiao (x.xiao@motorola.com)
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. */
  27. #ifndef __IMMAP_85xx__
  28. #define __IMMAP_85xx__
  29. #include <asm/types.h>
  30. #include <asm/fsl_dma.h>
  31. #include <asm/fsl_i2c.h>
  32. #include <asm/fsl_ifc.h>
  33. #include <asm/fsl_lbc.h>
  34. #include <asm/fsl_fman.h>
  35. typedef struct ccsr_local {
  36. u32 ccsrbarh; /* CCSR Base Addr High */
  37. u32 ccsrbarl; /* CCSR Base Addr Low */
  38. u32 ccsrar; /* CCSR Attr */
  39. #define CCSRAR_C 0x80000000 /* Commit */
  40. u8 res1[4];
  41. u32 altcbarh; /* Alternate Configuration Base Addr High */
  42. u32 altcbarl; /* Alternate Configuration Base Addr Low */
  43. u32 altcar; /* Alternate Configuration Attr */
  44. u8 res2[4];
  45. u32 bstrh; /* Boot space translation high */
  46. u32 bstrl; /* Boot space translation Low */
  47. u32 bstrar; /* Boot space translation attributes */
  48. u8 res3[0xbd4];
  49. struct {
  50. u32 lawbarh; /* LAWn base addr high */
  51. u32 lawbarl; /* LAWn base addr low */
  52. u32 lawar; /* LAWn attributes */
  53. u8 res4[4];
  54. } law[32];
  55. u8 res35[0x204];
  56. } ccsr_local_t;
  57. /* Local-Access Registers & ECM Registers */
  58. typedef struct ccsr_local_ecm {
  59. u32 ccsrbar; /* CCSR Base Addr */
  60. u8 res1[4];
  61. u32 altcbar; /* Alternate Configuration Base Addr */
  62. u8 res2[4];
  63. u32 altcar; /* Alternate Configuration Attr */
  64. u8 res3[12];
  65. u32 bptr; /* Boot Page Translation */
  66. u8 res4[3044];
  67. u32 lawbar0; /* Local Access Window 0 Base Addr */
  68. u8 res5[4];
  69. u32 lawar0; /* Local Access Window 0 Attrs */
  70. u8 res6[20];
  71. u32 lawbar1; /* Local Access Window 1 Base Addr */
  72. u8 res7[4];
  73. u32 lawar1; /* Local Access Window 1 Attrs */
  74. u8 res8[20];
  75. u32 lawbar2; /* Local Access Window 2 Base Addr */
  76. u8 res9[4];
  77. u32 lawar2; /* Local Access Window 2 Attrs */
  78. u8 res10[20];
  79. u32 lawbar3; /* Local Access Window 3 Base Addr */
  80. u8 res11[4];
  81. u32 lawar3; /* Local Access Window 3 Attrs */
  82. u8 res12[20];
  83. u32 lawbar4; /* Local Access Window 4 Base Addr */
  84. u8 res13[4];
  85. u32 lawar4; /* Local Access Window 4 Attrs */
  86. u8 res14[20];
  87. u32 lawbar5; /* Local Access Window 5 Base Addr */
  88. u8 res15[4];
  89. u32 lawar5; /* Local Access Window 5 Attrs */
  90. u8 res16[20];
  91. u32 lawbar6; /* Local Access Window 6 Base Addr */
  92. u8 res17[4];
  93. u32 lawar6; /* Local Access Window 6 Attrs */
  94. u8 res18[20];
  95. u32 lawbar7; /* Local Access Window 7 Base Addr */
  96. u8 res19[4];
  97. u32 lawar7; /* Local Access Window 7 Attrs */
  98. u8 res19_8a[20];
  99. u32 lawbar8; /* Local Access Window 8 Base Addr */
  100. u8 res19_8b[4];
  101. u32 lawar8; /* Local Access Window 8 Attrs */
  102. u8 res19_9a[20];
  103. u32 lawbar9; /* Local Access Window 9 Base Addr */
  104. u8 res19_9b[4];
  105. u32 lawar9; /* Local Access Window 9 Attrs */
  106. u8 res19_10a[20];
  107. u32 lawbar10; /* Local Access Window 10 Base Addr */
  108. u8 res19_10b[4];
  109. u32 lawar10; /* Local Access Window 10 Attrs */
  110. u8 res19_11a[20];
  111. u32 lawbar11; /* Local Access Window 11 Base Addr */
  112. u8 res19_11b[4];
  113. u32 lawar11; /* Local Access Window 11 Attrs */
  114. u8 res20[652];
  115. u32 eebacr; /* ECM CCB Addr Configuration */
  116. u8 res21[12];
  117. u32 eebpcr; /* ECM CCB Port Configuration */
  118. u8 res22[3564];
  119. u32 eedr; /* ECM Error Detect */
  120. u8 res23[4];
  121. u32 eeer; /* ECM Error Enable */
  122. u32 eeatr; /* ECM Error Attrs Capture */
  123. u32 eeadr; /* ECM Error Addr Capture */
  124. u8 res24[492];
  125. } ccsr_local_ecm_t;
  126. /* DDR memory controller registers */
  127. typedef struct ccsr_ddr {
  128. u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
  129. u8 res1[4];
  130. u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
  131. u8 res2[4];
  132. u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
  133. u8 res3[4];
  134. u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
  135. u8 res4[100];
  136. u32 cs0_config; /* Chip Select Configuration */
  137. u32 cs1_config; /* Chip Select Configuration */
  138. u32 cs2_config; /* Chip Select Configuration */
  139. u32 cs3_config; /* Chip Select Configuration */
  140. u8 res4a[48];
  141. u32 cs0_config_2; /* Chip Select Configuration 2 */
  142. u32 cs1_config_2; /* Chip Select Configuration 2 */
  143. u32 cs2_config_2; /* Chip Select Configuration 2 */
  144. u32 cs3_config_2; /* Chip Select Configuration 2 */
  145. u8 res5[48];
  146. u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
  147. u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
  148. u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
  149. u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
  150. u32 sdram_cfg; /* SDRAM Control Configuration */
  151. u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
  152. u32 sdram_mode; /* SDRAM Mode Configuration */
  153. u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
  154. u32 sdram_md_cntl; /* SDRAM Mode Control */
  155. u32 sdram_interval; /* SDRAM Interval Configuration */
  156. u32 sdram_data_init; /* SDRAM Data initialization */
  157. u8 res6[4];
  158. u32 sdram_clk_cntl; /* SDRAM Clock Control */
  159. u8 res7[20];
  160. u32 init_addr; /* training init addr */
  161. u32 init_ext_addr; /* training init extended addr */
  162. u8 res8_1[16];
  163. u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
  164. u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
  165. u8 reg8_1a[8];
  166. u32 ddr_zq_cntl; /* ZQ calibration control*/
  167. u32 ddr_wrlvl_cntl; /* write leveling control*/
  168. u8 reg8_1aa[4];
  169. u32 ddr_sr_cntr; /* self refresh counter */
  170. u32 ddr_sdram_rcw_1; /* Control Words 1 */
  171. u32 ddr_sdram_rcw_2; /* Control Words 2 */
  172. u8 reg_1ab[8];
  173. u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
  174. u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
  175. u8 res8_1b[104];
  176. u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
  177. u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
  178. u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
  179. u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
  180. u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
  181. u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
  182. u8 res8_1ba[0x908];
  183. u32 ddr_dsr1; /* Debug Status 1 */
  184. u32 ddr_dsr2; /* Debug Status 2 */
  185. u32 ddr_cdr1; /* Control Driver 1 */
  186. u32 ddr_cdr2; /* Control Driver 2 */
  187. u8 res8_1c[200];
  188. u32 ip_rev1; /* IP Block Revision 1 */
  189. u32 ip_rev2; /* IP Block Revision 2 */
  190. u32 eor; /* Enhanced Optimization Register */
  191. u8 res8_2[252];
  192. u32 mtcr; /* Memory Test Control Register */
  193. u8 res8_3[28];
  194. u32 mtp1; /* Memory Test Pattern 1 */
  195. u32 mtp2; /* Memory Test Pattern 2 */
  196. u32 mtp3; /* Memory Test Pattern 3 */
  197. u32 mtp4; /* Memory Test Pattern 4 */
  198. u32 mtp5; /* Memory Test Pattern 5 */
  199. u32 mtp6; /* Memory Test Pattern 6 */
  200. u32 mtp7; /* Memory Test Pattern 7 */
  201. u32 mtp8; /* Memory Test Pattern 8 */
  202. u32 mtp9; /* Memory Test Pattern 9 */
  203. u32 mtp10; /* Memory Test Pattern 10 */
  204. u8 res8_4[184];
  205. u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
  206. u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
  207. u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
  208. u8 res9[20];
  209. u32 capture_data_hi; /* Data Path Read Capture High */
  210. u32 capture_data_lo; /* Data Path Read Capture Low */
  211. u32 capture_ecc; /* Data Path Read Capture ECC */
  212. u8 res10[20];
  213. u32 err_detect; /* Error Detect */
  214. u32 err_disable; /* Error Disable */
  215. u32 err_int_en;
  216. u32 capture_attributes; /* Error Attrs Capture */
  217. u32 capture_address; /* Error Addr Capture */
  218. u32 capture_ext_address; /* Error Extended Addr Capture */
  219. u32 err_sbe; /* Single-Bit ECC Error Management */
  220. u8 res11[164];
  221. u32 debug[32]; /* debug_1 to debug_32 */
  222. u8 res12[128];
  223. } ccsr_ddr_t;
  224. #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
  225. #define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */
  226. /* I2C Registers */
  227. typedef struct ccsr_i2c {
  228. struct fsl_i2c i2c[1];
  229. u8 res[4096 - 1 * sizeof(struct fsl_i2c)];
  230. } ccsr_i2c_t;
  231. #if defined(CONFIG_MPC8540) \
  232. || defined(CONFIG_MPC8541) \
  233. || defined(CONFIG_MPC8548) \
  234. || defined(CONFIG_MPC8555)
  235. /* DUART Registers */
  236. typedef struct ccsr_duart {
  237. u8 res1[1280];
  238. /* URBR1, UTHR1, UDLB1 with the same addr */
  239. u8 urbr1_uthr1_udlb1;
  240. /* UIER1, UDMB1 with the same addr01 */
  241. u8 uier1_udmb1;
  242. /* UIIR1, UFCR1, UAFR1 with the same addr */
  243. u8 uiir1_ufcr1_uafr1;
  244. u8 ulcr1; /* UART1 Line Control */
  245. u8 umcr1; /* UART1 Modem Control */
  246. u8 ulsr1; /* UART1 Line Status */
  247. u8 umsr1; /* UART1 Modem Status */
  248. u8 uscr1; /* UART1 Scratch */
  249. u8 res2[8];
  250. u8 udsr1; /* UART1 DMA Status */
  251. u8 res3[239];
  252. /* URBR2, UTHR2, UDLB2 with the same addr */
  253. u8 urbr2_uthr2_udlb2;
  254. /* UIER2, UDMB2 with the same addr */
  255. u8 uier2_udmb2;
  256. /* UIIR2, UFCR2, UAFR2 with the same addr */
  257. u8 uiir2_ufcr2_uafr2;
  258. u8 ulcr2; /* UART2 Line Control */
  259. u8 umcr2; /* UART2 Modem Control */
  260. u8 ulsr2; /* UART2 Line Status */
  261. u8 umsr2; /* UART2 Modem Status */
  262. u8 uscr2; /* UART2 Scratch */
  263. u8 res4[8];
  264. u8 udsr2; /* UART2 DMA Status */
  265. u8 res5[2543];
  266. } ccsr_duart_t;
  267. #else /* MPC8560 uses UART on its CPM */
  268. typedef struct ccsr_duart {
  269. u8 res[4096];
  270. } ccsr_duart_t;
  271. #endif
  272. /* eSPI Registers */
  273. typedef struct ccsr_espi {
  274. u32 mode; /* eSPI mode */
  275. u32 event; /* eSPI event */
  276. u32 mask; /* eSPI mask */
  277. u32 com; /* eSPI command */
  278. u32 tx; /* eSPI transmit FIFO access */
  279. u32 rx; /* eSPI receive FIFO access */
  280. u8 res1[8]; /* reserved */
  281. u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */
  282. u8 res2[4048]; /* fill up to 0x1000 */
  283. } ccsr_espi_t;
  284. /* PCI Registers */
  285. typedef struct ccsr_pcix {
  286. u32 cfg_addr; /* PCIX Configuration Addr */
  287. u32 cfg_data; /* PCIX Configuration Data */
  288. u32 int_ack; /* PCIX IRQ Acknowledge */
  289. u8 res1[3060];
  290. u32 potar0; /* PCIX Outbound Transaction Addr 0 */
  291. u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */
  292. u32 powbar0; /* PCIX Outbound Window Base Addr 0 */
  293. u32 powbear0; /* PCIX Outbound Window Base Extended Addr 0 */
  294. u32 powar0; /* PCIX Outbound Window Attrs 0 */
  295. u8 res2[12];
  296. u32 potar1; /* PCIX Outbound Transaction Addr 1 */
  297. u32 potear1; /* PCIX Outbound Translation Extended Addr 1 */
  298. u32 powbar1; /* PCIX Outbound Window Base Addr 1 */
  299. u32 powbear1; /* PCIX Outbound Window Base Extended Addr 1 */
  300. u32 powar1; /* PCIX Outbound Window Attrs 1 */
  301. u8 res3[12];
  302. u32 potar2; /* PCIX Outbound Transaction Addr 2 */
  303. u32 potear2; /* PCIX Outbound Translation Extended Addr 2 */
  304. u32 powbar2; /* PCIX Outbound Window Base Addr 2 */
  305. u32 powbear2; /* PCIX Outbound Window Base Extended Addr 2 */
  306. u32 powar2; /* PCIX Outbound Window Attrs 2 */
  307. u8 res4[12];
  308. u32 potar3; /* PCIX Outbound Transaction Addr 3 */
  309. u32 potear3; /* PCIX Outbound Translation Extended Addr 3 */
  310. u32 powbar3; /* PCIX Outbound Window Base Addr 3 */
  311. u32 powbear3; /* PCIX Outbound Window Base Extended Addr 3 */
  312. u32 powar3; /* PCIX Outbound Window Attrs 3 */
  313. u8 res5[12];
  314. u32 potar4; /* PCIX Outbound Transaction Addr 4 */
  315. u32 potear4; /* PCIX Outbound Translation Extended Addr 4 */
  316. u32 powbar4; /* PCIX Outbound Window Base Addr 4 */
  317. u32 powbear4; /* PCIX Outbound Window Base Extended Addr 4 */
  318. u32 powar4; /* PCIX Outbound Window Attrs 4 */
  319. u8 res6[268];
  320. u32 pitar3; /* PCIX Inbound Translation Addr 3 */
  321. u32 pitear3; /* PCIX Inbound Translation Extended Addr 3 */
  322. u32 piwbar3; /* PCIX Inbound Window Base Addr 3 */
  323. u32 piwbear3; /* PCIX Inbound Window Base Extended Addr 3 */
  324. u32 piwar3; /* PCIX Inbound Window Attrs 3 */
  325. u8 res7[12];
  326. u32 pitar2; /* PCIX Inbound Translation Addr 2 */
  327. u32 pitear2; /* PCIX Inbound Translation Extended Addr 2 */
  328. u32 piwbar2; /* PCIX Inbound Window Base Addr 2 */
  329. u32 piwbear2; /* PCIX Inbound Window Base Extended Addr 2 */
  330. u32 piwar2; /* PCIX Inbound Window Attrs 2 */
  331. u8 res8[12];
  332. u32 pitar1; /* PCIX Inbound Translation Addr 1 */
  333. u32 pitear1; /* PCIX Inbound Translation Extended Addr 1 */
  334. u32 piwbar1; /* PCIX Inbound Window Base Addr 1 */
  335. u8 res9[4];
  336. u32 piwar1; /* PCIX Inbound Window Attrs 1 */
  337. u8 res10[12];
  338. u32 pedr; /* PCIX Error Detect */
  339. u32 pecdr; /* PCIX Error Capture Disable */
  340. u32 peer; /* PCIX Error Enable */
  341. u32 peattrcr; /* PCIX Error Attrs Capture */
  342. u32 peaddrcr; /* PCIX Error Addr Capture */
  343. u32 peextaddrcr; /* PCIX Error Extended Addr Capture */
  344. u32 pedlcr; /* PCIX Error Data Low Capture */
  345. u32 pedhcr; /* PCIX Error Error Data High Capture */
  346. u32 gas_timr; /* PCIX Gasket Timer */
  347. u8 res11[476];
  348. } ccsr_pcix_t;
  349. #define PCIX_COMMAND 0x62
  350. #define POWAR_EN 0x80000000
  351. #define POWAR_IO_READ 0x00080000
  352. #define POWAR_MEM_READ 0x00040000
  353. #define POWAR_IO_WRITE 0x00008000
  354. #define POWAR_MEM_WRITE 0x00004000
  355. #define POWAR_MEM_512M 0x0000001c
  356. #define POWAR_IO_1M 0x00000013
  357. #define PIWAR_EN 0x80000000
  358. #define PIWAR_PF 0x20000000
  359. #define PIWAR_LOCAL 0x00f00000
  360. #define PIWAR_READ_SNOOP 0x00050000
  361. #define PIWAR_WRITE_SNOOP 0x00005000
  362. #define PIWAR_MEM_2G 0x0000001e
  363. typedef struct ccsr_gpio {
  364. u32 gpdir;
  365. u32 gpodr;
  366. u32 gpdat;
  367. u32 gpier;
  368. u32 gpimr;
  369. u32 gpicr;
  370. } ccsr_gpio_t;
  371. /* L2 Cache Registers */
  372. typedef struct ccsr_l2cache {
  373. u32 l2ctl; /* L2 configuration 0 */
  374. u8 res1[12];
  375. u32 l2cewar0; /* L2 cache external write addr 0 */
  376. u8 res2[4];
  377. u32 l2cewcr0; /* L2 cache external write control 0 */
  378. u8 res3[4];
  379. u32 l2cewar1; /* L2 cache external write addr 1 */
  380. u8 res4[4];
  381. u32 l2cewcr1; /* L2 cache external write control 1 */
  382. u8 res5[4];
  383. u32 l2cewar2; /* L2 cache external write addr 2 */
  384. u8 res6[4];
  385. u32 l2cewcr2; /* L2 cache external write control 2 */
  386. u8 res7[4];
  387. u32 l2cewar3; /* L2 cache external write addr 3 */
  388. u8 res8[4];
  389. u32 l2cewcr3; /* L2 cache external write control 3 */
  390. u8 res9[180];
  391. u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */
  392. u8 res10[4];
  393. u32 l2srbar1; /* L2 memory-mapped SRAM base addr 1 */
  394. u8 res11[3316];
  395. u32 l2errinjhi; /* L2 error injection mask high */
  396. u32 l2errinjlo; /* L2 error injection mask low */
  397. u32 l2errinjctl; /* L2 error injection tag/ECC control */
  398. u8 res12[20];
  399. u32 l2captdatahi; /* L2 error data high capture */
  400. u32 l2captdatalo; /* L2 error data low capture */
  401. u32 l2captecc; /* L2 error ECC capture */
  402. u8 res13[20];
  403. u32 l2errdet; /* L2 error detect */
  404. u32 l2errdis; /* L2 error disable */
  405. u32 l2errinten; /* L2 error interrupt enable */
  406. u32 l2errattr; /* L2 error attributes capture */
  407. u32 l2erraddr; /* L2 error addr capture */
  408. u8 res14[4];
  409. u32 l2errctl; /* L2 error control */
  410. u8 res15[420];
  411. } ccsr_l2cache_t;
  412. #define MPC85xx_L2CTL_L2E 0x80000000
  413. #define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000
  414. #define MPC85xx_L2ERRDIS_MBECC 0x00000008
  415. #define MPC85xx_L2ERRDIS_SBECC 0x00000004
  416. /* DMA Registers */
  417. typedef struct ccsr_dma {
  418. u8 res1[256];
  419. struct fsl_dma dma[4];
  420. u32 dgsr; /* DMA General Status */
  421. u8 res2[11516];
  422. } ccsr_dma_t;
  423. /* tsec */
  424. typedef struct ccsr_tsec {
  425. u8 res1[16];
  426. u32 ievent; /* IRQ Event */
  427. u32 imask; /* IRQ Mask */
  428. u32 edis; /* Error Disabled */
  429. u8 res2[4];
  430. u32 ecntrl; /* Ethernet Control */
  431. u32 minflr; /* Minimum Frame Len */
  432. u32 ptv; /* Pause Time Value */
  433. u32 dmactrl; /* DMA Control */
  434. u32 tbipa; /* TBI PHY Addr */
  435. u8 res3[88];
  436. u32 fifo_tx_thr; /* FIFO transmit threshold */
  437. u8 res4[8];
  438. u32 fifo_tx_starve; /* FIFO transmit starve */
  439. u32 fifo_tx_starve_shutoff; /* FIFO transmit starve shutoff */
  440. u8 res5[96];
  441. u32 tctrl; /* TX Control */
  442. u32 tstat; /* TX Status */
  443. u8 res6[4];
  444. u32 tbdlen; /* TX Buffer Desc Data Len */
  445. u8 res7[16];
  446. u32 ctbptrh; /* Current TX Buffer Desc Ptr High */
  447. u32 ctbptr; /* Current TX Buffer Desc Ptr */
  448. u8 res8[88];
  449. u32 tbptrh; /* TX Buffer Desc Ptr High */
  450. u32 tbptr; /* TX Buffer Desc Ptr Low */
  451. u8 res9[120];
  452. u32 tbaseh; /* TX Desc Base Addr High */
  453. u32 tbase; /* TX Desc Base Addr */
  454. u8 res10[168];
  455. u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */
  456. u32 ostbdp; /* OOS TX Data Buffer Ptr */
  457. u32 os32tbdp; /* OOS 32 Bytes TX Data Buffer Ptr Low */
  458. u32 os32iptrh; /* OOS 32 Bytes TX Insert Ptr High */
  459. u32 os32iptrl; /* OOS 32 Bytes TX Insert Ptr Low */
  460. u32 os32tbdr; /* OOS 32 Bytes TX Reserved */
  461. u32 os32iil; /* OOS 32 Bytes TX Insert Idx/Len */
  462. u8 res11[52];
  463. u32 rctrl; /* RX Control */
  464. u32 rstat; /* RX Status */
  465. u8 res12[4];
  466. u32 rbdlen; /* RxBD Data Len */
  467. u8 res13[16];
  468. u32 crbptrh; /* Current RX Buffer Desc Ptr High */
  469. u32 crbptr; /* Current RX Buffer Desc Ptr */
  470. u8 res14[24];
  471. u32 mrblr; /* Maximum RX Buffer Len */
  472. u32 mrblr2r3; /* Maximum RX Buffer Len R2R3 */
  473. u8 res15[56];
  474. u32 rbptrh; /* RX Buffer Desc Ptr High 0 */
  475. u32 rbptr; /* RX Buffer Desc Ptr */
  476. u32 rbptrh1; /* RX Buffer Desc Ptr High 1 */
  477. u32 rbptrl1; /* RX Buffer Desc Ptr Low 1 */
  478. u32 rbptrh2; /* RX Buffer Desc Ptr High 2 */
  479. u32 rbptrl2; /* RX Buffer Desc Ptr Low 2 */
  480. u32 rbptrh3; /* RX Buffer Desc Ptr High 3 */
  481. u32 rbptrl3; /* RX Buffer Desc Ptr Low 3 */
  482. u8 res16[96];
  483. u32 rbaseh; /* RX Desc Base Addr High 0 */
  484. u32 rbase; /* RX Desc Base Addr */
  485. u32 rbaseh1; /* RX Desc Base Addr High 1 */
  486. u32 rbasel1; /* RX Desc Base Addr Low 1 */
  487. u32 rbaseh2; /* RX Desc Base Addr High 2 */
  488. u32 rbasel2; /* RX Desc Base Addr Low 2 */
  489. u32 rbaseh3; /* RX Desc Base Addr High 3 */
  490. u32 rbasel3; /* RX Desc Base Addr Low 3 */
  491. u8 res17[224];
  492. u32 maccfg1; /* MAC Configuration 1 */
  493. u32 maccfg2; /* MAC Configuration 2 */
  494. u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */
  495. u32 hafdup; /* Half Duplex */
  496. u32 maxfrm; /* Maximum Frame Len */
  497. u8 res18[12];
  498. u32 miimcfg; /* MII Management Configuration */
  499. u32 miimcom; /* MII Management Cmd */
  500. u32 miimadd; /* MII Management Addr */
  501. u32 miimcon; /* MII Management Control */
  502. u32 miimstat; /* MII Management Status */
  503. u32 miimind; /* MII Management Indicator */
  504. u8 res19[4];
  505. u32 ifstat; /* Interface Status */
  506. u32 macstnaddr1; /* Station Addr Part 1 */
  507. u32 macstnaddr2; /* Station Addr Part 2 */
  508. u8 res20[312];
  509. u32 tr64; /* TX & RX 64-byte Frame Counter */
  510. u32 tr127; /* TX & RX 65-127 byte Frame Counter */
  511. u32 tr255; /* TX & RX 128-255 byte Frame Counter */
  512. u32 tr511; /* TX & RX 256-511 byte Frame Counter */
  513. u32 tr1k; /* TX & RX 512-1023 byte Frame Counter */
  514. u32 trmax; /* TX & RX 1024-1518 byte Frame Counter */
  515. u32 trmgv; /* TX & RX 1519-1522 byte Good VLAN Frame */
  516. u32 rbyt; /* RX Byte Counter */
  517. u32 rpkt; /* RX Packet Counter */
  518. u32 rfcs; /* RX FCS Error Counter */
  519. u32 rmca; /* RX Multicast Packet Counter */
  520. u32 rbca; /* RX Broadcast Packet Counter */
  521. u32 rxcf; /* RX Control Frame Packet Counter */
  522. u32 rxpf; /* RX Pause Frame Packet Counter */
  523. u32 rxuo; /* RX Unknown OP Code Counter */
  524. u32 raln; /* RX Alignment Error Counter */
  525. u32 rflr; /* RX Frame Len Error Counter */
  526. u32 rcde; /* RX Code Error Counter */
  527. u32 rcse; /* RX Carrier Sense Error Counter */
  528. u32 rund; /* RX Undersize Packet Counter */
  529. u32 rovr; /* RX Oversize Packet Counter */
  530. u32 rfrg; /* RX Fragments Counter */
  531. u32 rjbr; /* RX Jabber Counter */
  532. u32 rdrp; /* RX Drop Counter */
  533. u32 tbyt; /* TX Byte Counter Counter */
  534. u32 tpkt; /* TX Packet Counter */
  535. u32 tmca; /* TX Multicast Packet Counter */
  536. u32 tbca; /* TX Broadcast Packet Counter */
  537. u32 txpf; /* TX Pause Control Frame Counter */
  538. u32 tdfr; /* TX Deferral Packet Counter */
  539. u32 tedf; /* TX Excessive Deferral Packet Counter */
  540. u32 tscl; /* TX Single Collision Packet Counter */
  541. u32 tmcl; /* TX Multiple Collision Packet Counter */
  542. u32 tlcl; /* TX Late Collision Packet Counter */
  543. u32 txcl; /* TX Excessive Collision Packet Counter */
  544. u32 tncl; /* TX Total Collision Counter */
  545. u8 res21[4];
  546. u32 tdrp; /* TX Drop Frame Counter */
  547. u32 tjbr; /* TX Jabber Frame Counter */
  548. u32 tfcs; /* TX FCS Error Counter */
  549. u32 txcf; /* TX Control Frame Counter */
  550. u32 tovr; /* TX Oversize Frame Counter */
  551. u32 tund; /* TX Undersize Frame Counter */
  552. u32 tfrg; /* TX Fragments Frame Counter */
  553. u32 car1; /* Carry One */
  554. u32 car2; /* Carry Two */
  555. u32 cam1; /* Carry Mask One */
  556. u32 cam2; /* Carry Mask Two */
  557. u8 res22[192];
  558. u32 iaddr0; /* Indivdual addr 0 */
  559. u32 iaddr1; /* Indivdual addr 1 */
  560. u32 iaddr2; /* Indivdual addr 2 */
  561. u32 iaddr3; /* Indivdual addr 3 */
  562. u32 iaddr4; /* Indivdual addr 4 */
  563. u32 iaddr5; /* Indivdual addr 5 */
  564. u32 iaddr6; /* Indivdual addr 6 */
  565. u32 iaddr7; /* Indivdual addr 7 */
  566. u8 res23[96];
  567. u32 gaddr0; /* Global addr 0 */
  568. u32 gaddr1; /* Global addr 1 */
  569. u32 gaddr2; /* Global addr 2 */
  570. u32 gaddr3; /* Global addr 3 */
  571. u32 gaddr4; /* Global addr 4 */
  572. u32 gaddr5; /* Global addr 5 */
  573. u32 gaddr6; /* Global addr 6 */
  574. u32 gaddr7; /* Global addr 7 */
  575. u8 res24[96];
  576. u32 pmd0; /* Pattern Match Data */
  577. u8 res25[4];
  578. u32 pmask0; /* Pattern Mask */
  579. u8 res26[4];
  580. u32 pcntrl0; /* Pattern Match Control */
  581. u8 res27[4];
  582. u32 pattrb0; /* Pattern Match Attrs */
  583. u32 pattrbeli0; /* Pattern Match Attrs Extract Len & Idx */
  584. u32 pmd1; /* Pattern Match Data */
  585. u8 res28[4];
  586. u32 pmask1; /* Pattern Mask */
  587. u8 res29[4];
  588. u32 pcntrl1; /* Pattern Match Control */
  589. u8 res30[4];
  590. u32 pattrb1; /* Pattern Match Attrs */
  591. u32 pattrbeli1; /* Pattern Match Attrs Extract Len & Idx */
  592. u32 pmd2; /* Pattern Match Data */
  593. u8 res31[4];
  594. u32 pmask2; /* Pattern Mask */
  595. u8 res32[4];
  596. u32 pcntrl2; /* Pattern Match Control */
  597. u8 res33[4];
  598. u32 pattrb2; /* Pattern Match Attrs */
  599. u32 pattrbeli2; /* Pattern Match Attrs Extract Len & Idx */
  600. u32 pmd3; /* Pattern Match Data */
  601. u8 res34[4];
  602. u32 pmask3; /* Pattern Mask */
  603. u8 res35[4];
  604. u32 pcntrl3; /* Pattern Match Control */
  605. u8 res36[4];
  606. u32 pattrb3; /* Pattern Match Attrs */
  607. u32 pattrbeli3; /* Pattern Match Attrs Extract Len & Idx */
  608. u32 pmd4; /* Pattern Match Data */
  609. u8 res37[4];
  610. u32 pmask4; /* Pattern Mask */
  611. u8 res38[4];
  612. u32 pcntrl4; /* Pattern Match Control */
  613. u8 res39[4];
  614. u32 pattrb4; /* Pattern Match Attrs */
  615. u32 pattrbeli4; /* Pattern Match Attrs Extract Len & Idx */
  616. u32 pmd5; /* Pattern Match Data */
  617. u8 res40[4];
  618. u32 pmask5; /* Pattern Mask */
  619. u8 res41[4];
  620. u32 pcntrl5; /* Pattern Match Control */
  621. u8 res42[4];
  622. u32 pattrb5; /* Pattern Match Attrs */
  623. u32 pattrbeli5; /* Pattern Match Attrs Extract Len & Idx */
  624. u32 pmd6; /* Pattern Match Data */
  625. u8 res43[4];
  626. u32 pmask6; /* Pattern Mask */
  627. u8 res44[4];
  628. u32 pcntrl6; /* Pattern Match Control */
  629. u8 res45[4];
  630. u32 pattrb6; /* Pattern Match Attrs */
  631. u32 pattrbeli6; /* Pattern Match Attrs Extract Len & Idx */
  632. u32 pmd7; /* Pattern Match Data */
  633. u8 res46[4];
  634. u32 pmask7; /* Pattern Mask */
  635. u8 res47[4];
  636. u32 pcntrl7; /* Pattern Match Control */
  637. u8 res48[4];
  638. u32 pattrb7; /* Pattern Match Attrs */
  639. u32 pattrbeli7; /* Pattern Match Attrs Extract Len & Idx */
  640. u32 pmd8; /* Pattern Match Data */
  641. u8 res49[4];
  642. u32 pmask8; /* Pattern Mask */
  643. u8 res50[4];
  644. u32 pcntrl8; /* Pattern Match Control */
  645. u8 res51[4];
  646. u32 pattrb8; /* Pattern Match Attrs */
  647. u32 pattrbeli8; /* Pattern Match Attrs Extract Len & Idx */
  648. u32 pmd9; /* Pattern Match Data */
  649. u8 res52[4];
  650. u32 pmask9; /* Pattern Mask */
  651. u8 res53[4];
  652. u32 pcntrl9; /* Pattern Match Control */
  653. u8 res54[4];
  654. u32 pattrb9; /* Pattern Match Attrs */
  655. u32 pattrbeli9; /* Pattern Match Attrs Extract Len & Idx */
  656. u32 pmd10; /* Pattern Match Data */
  657. u8 res55[4];
  658. u32 pmask10; /* Pattern Mask */
  659. u8 res56[4];
  660. u32 pcntrl10; /* Pattern Match Control */
  661. u8 res57[4];
  662. u32 pattrb10; /* Pattern Match Attrs */
  663. u32 pattrbeli10; /* Pattern Match Attrs Extract Len & Idx */
  664. u32 pmd11; /* Pattern Match Data */
  665. u8 res58[4];
  666. u32 pmask11; /* Pattern Mask */
  667. u8 res59[4];
  668. u32 pcntrl11; /* Pattern Match Control */
  669. u8 res60[4];
  670. u32 pattrb11; /* Pattern Match Attrs */
  671. u32 pattrbeli11; /* Pattern Match Attrs Extract Len & Idx */
  672. u32 pmd12; /* Pattern Match Data */
  673. u8 res61[4];
  674. u32 pmask12; /* Pattern Mask */
  675. u8 res62[4];
  676. u32 pcntrl12; /* Pattern Match Control */
  677. u8 res63[4];
  678. u32 pattrb12; /* Pattern Match Attrs */
  679. u32 pattrbeli12; /* Pattern Match Attrs Extract Len & Idx */
  680. u32 pmd13; /* Pattern Match Data */
  681. u8 res64[4];
  682. u32 pmask13; /* Pattern Mask */
  683. u8 res65[4];
  684. u32 pcntrl13; /* Pattern Match Control */
  685. u8 res66[4];
  686. u32 pattrb13; /* Pattern Match Attrs */
  687. u32 pattrbeli13; /* Pattern Match Attrs Extract Len & Idx */
  688. u32 pmd14; /* Pattern Match Data */
  689. u8 res67[4];
  690. u32 pmask14; /* Pattern Mask */
  691. u8 res68[4];
  692. u32 pcntrl14; /* Pattern Match Control */
  693. u8 res69[4];
  694. u32 pattrb14; /* Pattern Match Attrs */
  695. u32 pattrbeli14; /* Pattern Match Attrs Extract Len & Idx */
  696. u32 pmd15; /* Pattern Match Data */
  697. u8 res70[4];
  698. u32 pmask15; /* Pattern Mask */
  699. u8 res71[4];
  700. u32 pcntrl15; /* Pattern Match Control */
  701. u8 res72[4];
  702. u32 pattrb15; /* Pattern Match Attrs */
  703. u32 pattrbeli15; /* Pattern Match Attrs Extract Len & Idx */
  704. u8 res73[248];
  705. u32 attr; /* Attrs */
  706. u32 attreli; /* Attrs Extract Len & Idx */
  707. u8 res74[1024];
  708. } ccsr_tsec_t;
  709. /* PIC Registers */
  710. typedef struct ccsr_pic {
  711. u8 res1[64];
  712. u32 ipidr0; /* Interprocessor IRQ Dispatch 0 */
  713. u8 res2[12];
  714. u32 ipidr1; /* Interprocessor IRQ Dispatch 1 */
  715. u8 res3[12];
  716. u32 ipidr2; /* Interprocessor IRQ Dispatch 2 */
  717. u8 res4[12];
  718. u32 ipidr3; /* Interprocessor IRQ Dispatch 3 */
  719. u8 res5[12];
  720. u32 ctpr; /* Current Task Priority */
  721. u8 res6[12];
  722. u32 whoami; /* Who Am I */
  723. u8 res7[12];
  724. u32 iack; /* IRQ Acknowledge */
  725. u8 res8[12];
  726. u32 eoi; /* End Of IRQ */
  727. u8 res9[3916];
  728. u32 frr; /* Feature Reporting */
  729. u8 res10[28];
  730. u32 gcr; /* Global Configuration */
  731. #define MPC85xx_PICGCR_RST 0x80000000
  732. #define MPC85xx_PICGCR_M 0x20000000
  733. u8 res11[92];
  734. u32 vir; /* Vendor Identification */
  735. u8 res12[12];
  736. u32 pir; /* Processor Initialization */
  737. u8 res13[12];
  738. u32 ipivpr0; /* IPI Vector/Priority 0 */
  739. u8 res14[12];
  740. u32 ipivpr1; /* IPI Vector/Priority 1 */
  741. u8 res15[12];
  742. u32 ipivpr2; /* IPI Vector/Priority 2 */
  743. u8 res16[12];
  744. u32 ipivpr3; /* IPI Vector/Priority 3 */
  745. u8 res17[12];
  746. u32 svr; /* Spurious Vector */
  747. u8 res18[12];
  748. u32 tfrr; /* Timer Frequency Reporting */
  749. u8 res19[12];
  750. u32 gtccr0; /* Global Timer Current Count 0 */
  751. u8 res20[12];
  752. u32 gtbcr0; /* Global Timer Base Count 0 */
  753. u8 res21[12];
  754. u32 gtvpr0; /* Global Timer Vector/Priority 0 */
  755. u8 res22[12];
  756. u32 gtdr0; /* Global Timer Destination 0 */
  757. u8 res23[12];
  758. u32 gtccr1; /* Global Timer Current Count 1 */
  759. u8 res24[12];
  760. u32 gtbcr1; /* Global Timer Base Count 1 */
  761. u8 res25[12];
  762. u32 gtvpr1; /* Global Timer Vector/Priority 1 */
  763. u8 res26[12];
  764. u32 gtdr1; /* Global Timer Destination 1 */
  765. u8 res27[12];
  766. u32 gtccr2; /* Global Timer Current Count 2 */
  767. u8 res28[12];
  768. u32 gtbcr2; /* Global Timer Base Count 2 */
  769. u8 res29[12];
  770. u32 gtvpr2; /* Global Timer Vector/Priority 2 */
  771. u8 res30[12];
  772. u32 gtdr2; /* Global Timer Destination 2 */
  773. u8 res31[12];
  774. u32 gtccr3; /* Global Timer Current Count 3 */
  775. u8 res32[12];
  776. u32 gtbcr3; /* Global Timer Base Count 3 */
  777. u8 res33[12];
  778. u32 gtvpr3; /* Global Timer Vector/Priority 3 */
  779. u8 res34[12];
  780. u32 gtdr3; /* Global Timer Destination 3 */
  781. u8 res35[268];
  782. u32 tcr; /* Timer Control */
  783. u8 res36[12];
  784. u32 irqsr0; /* IRQ_OUT Summary 0 */
  785. u8 res37[12];
  786. u32 irqsr1; /* IRQ_OUT Summary 1 */
  787. u8 res38[12];
  788. u32 cisr0; /* Critical IRQ Summary 0 */
  789. u8 res39[12];
  790. u32 cisr1; /* Critical IRQ Summary 1 */
  791. u8 res40[188];
  792. u32 msgr0; /* Message 0 */
  793. u8 res41[12];
  794. u32 msgr1; /* Message 1 */
  795. u8 res42[12];
  796. u32 msgr2; /* Message 2 */
  797. u8 res43[12];
  798. u32 msgr3; /* Message 3 */
  799. u8 res44[204];
  800. u32 mer; /* Message Enable */
  801. u8 res45[12];
  802. u32 msr; /* Message Status */
  803. u8 res46[60140];
  804. u32 eivpr0; /* External IRQ Vector/Priority 0 */
  805. u8 res47[12];
  806. u32 eidr0; /* External IRQ Destination 0 */
  807. u8 res48[12];
  808. u32 eivpr1; /* External IRQ Vector/Priority 1 */
  809. u8 res49[12];
  810. u32 eidr1; /* External IRQ Destination 1 */
  811. u8 res50[12];
  812. u32 eivpr2; /* External IRQ Vector/Priority 2 */
  813. u8 res51[12];
  814. u32 eidr2; /* External IRQ Destination 2 */
  815. u8 res52[12];
  816. u32 eivpr3; /* External IRQ Vector/Priority 3 */
  817. u8 res53[12];
  818. u32 eidr3; /* External IRQ Destination 3 */
  819. u8 res54[12];
  820. u32 eivpr4; /* External IRQ Vector/Priority 4 */
  821. u8 res55[12];
  822. u32 eidr4; /* External IRQ Destination 4 */
  823. u8 res56[12];
  824. u32 eivpr5; /* External IRQ Vector/Priority 5 */
  825. u8 res57[12];
  826. u32 eidr5; /* External IRQ Destination 5 */
  827. u8 res58[12];
  828. u32 eivpr6; /* External IRQ Vector/Priority 6 */
  829. u8 res59[12];
  830. u32 eidr6; /* External IRQ Destination 6 */
  831. u8 res60[12];
  832. u32 eivpr7; /* External IRQ Vector/Priority 7 */
  833. u8 res61[12];
  834. u32 eidr7; /* External IRQ Destination 7 */
  835. u8 res62[12];
  836. u32 eivpr8; /* External IRQ Vector/Priority 8 */
  837. u8 res63[12];
  838. u32 eidr8; /* External IRQ Destination 8 */
  839. u8 res64[12];
  840. u32 eivpr9; /* External IRQ Vector/Priority 9 */
  841. u8 res65[12];
  842. u32 eidr9; /* External IRQ Destination 9 */
  843. u8 res66[12];
  844. u32 eivpr10; /* External IRQ Vector/Priority 10 */
  845. u8 res67[12];
  846. u32 eidr10; /* External IRQ Destination 10 */
  847. u8 res68[12];
  848. u32 eivpr11; /* External IRQ Vector/Priority 11 */
  849. u8 res69[12];
  850. u32 eidr11; /* External IRQ Destination 11 */
  851. u8 res70[140];
  852. u32 iivpr0; /* Internal IRQ Vector/Priority 0 */
  853. u8 res71[12];
  854. u32 iidr0; /* Internal IRQ Destination 0 */
  855. u8 res72[12];
  856. u32 iivpr1; /* Internal IRQ Vector/Priority 1 */
  857. u8 res73[12];
  858. u32 iidr1; /* Internal IRQ Destination 1 */
  859. u8 res74[12];
  860. u32 iivpr2; /* Internal IRQ Vector/Priority 2 */
  861. u8 res75[12];
  862. u32 iidr2; /* Internal IRQ Destination 2 */
  863. u8 res76[12];
  864. u32 iivpr3; /* Internal IRQ Vector/Priority 3 */
  865. u8 res77[12];
  866. u32 iidr3; /* Internal IRQ Destination 3 */
  867. u8 res78[12];
  868. u32 iivpr4; /* Internal IRQ Vector/Priority 4 */
  869. u8 res79[12];
  870. u32 iidr4; /* Internal IRQ Destination 4 */
  871. u8 res80[12];
  872. u32 iivpr5; /* Internal IRQ Vector/Priority 5 */
  873. u8 res81[12];
  874. u32 iidr5; /* Internal IRQ Destination 5 */
  875. u8 res82[12];
  876. u32 iivpr6; /* Internal IRQ Vector/Priority 6 */
  877. u8 res83[12];
  878. u32 iidr6; /* Internal IRQ Destination 6 */
  879. u8 res84[12];
  880. u32 iivpr7; /* Internal IRQ Vector/Priority 7 */
  881. u8 res85[12];
  882. u32 iidr7; /* Internal IRQ Destination 7 */
  883. u8 res86[12];
  884. u32 iivpr8; /* Internal IRQ Vector/Priority 8 */
  885. u8 res87[12];
  886. u32 iidr8; /* Internal IRQ Destination 8 */
  887. u8 res88[12];
  888. u32 iivpr9; /* Internal IRQ Vector/Priority 9 */
  889. u8 res89[12];
  890. u32 iidr9; /* Internal IRQ Destination 9 */
  891. u8 res90[12];
  892. u32 iivpr10; /* Internal IRQ Vector/Priority 10 */
  893. u8 res91[12];
  894. u32 iidr10; /* Internal IRQ Destination 10 */
  895. u8 res92[12];
  896. u32 iivpr11; /* Internal IRQ Vector/Priority 11 */
  897. u8 res93[12];
  898. u32 iidr11; /* Internal IRQ Destination 11 */
  899. u8 res94[12];
  900. u32 iivpr12; /* Internal IRQ Vector/Priority 12 */
  901. u8 res95[12];
  902. u32 iidr12; /* Internal IRQ Destination 12 */
  903. u8 res96[12];
  904. u32 iivpr13; /* Internal IRQ Vector/Priority 13 */
  905. u8 res97[12];
  906. u32 iidr13; /* Internal IRQ Destination 13 */
  907. u8 res98[12];
  908. u32 iivpr14; /* Internal IRQ Vector/Priority 14 */
  909. u8 res99[12];
  910. u32 iidr14; /* Internal IRQ Destination 14 */
  911. u8 res100[12];
  912. u32 iivpr15; /* Internal IRQ Vector/Priority 15 */
  913. u8 res101[12];
  914. u32 iidr15; /* Internal IRQ Destination 15 */
  915. u8 res102[12];
  916. u32 iivpr16; /* Internal IRQ Vector/Priority 16 */
  917. u8 res103[12];
  918. u32 iidr16; /* Internal IRQ Destination 16 */
  919. u8 res104[12];
  920. u32 iivpr17; /* Internal IRQ Vector/Priority 17 */
  921. u8 res105[12];
  922. u32 iidr17; /* Internal IRQ Destination 17 */
  923. u8 res106[12];
  924. u32 iivpr18; /* Internal IRQ Vector/Priority 18 */
  925. u8 res107[12];
  926. u32 iidr18; /* Internal IRQ Destination 18 */
  927. u8 res108[12];
  928. u32 iivpr19; /* Internal IRQ Vector/Priority 19 */
  929. u8 res109[12];
  930. u32 iidr19; /* Internal IRQ Destination 19 */
  931. u8 res110[12];
  932. u32 iivpr20; /* Internal IRQ Vector/Priority 20 */
  933. u8 res111[12];
  934. u32 iidr20; /* Internal IRQ Destination 20 */
  935. u8 res112[12];
  936. u32 iivpr21; /* Internal IRQ Vector/Priority 21 */
  937. u8 res113[12];
  938. u32 iidr21; /* Internal IRQ Destination 21 */
  939. u8 res114[12];
  940. u32 iivpr22; /* Internal IRQ Vector/Priority 22 */
  941. u8 res115[12];
  942. u32 iidr22; /* Internal IRQ Destination 22 */
  943. u8 res116[12];
  944. u32 iivpr23; /* Internal IRQ Vector/Priority 23 */
  945. u8 res117[12];
  946. u32 iidr23; /* Internal IRQ Destination 23 */
  947. u8 res118[12];
  948. u32 iivpr24; /* Internal IRQ Vector/Priority 24 */
  949. u8 res119[12];
  950. u32 iidr24; /* Internal IRQ Destination 24 */
  951. u8 res120[12];
  952. u32 iivpr25; /* Internal IRQ Vector/Priority 25 */
  953. u8 res121[12];
  954. u32 iidr25; /* Internal IRQ Destination 25 */
  955. u8 res122[12];
  956. u32 iivpr26; /* Internal IRQ Vector/Priority 26 */
  957. u8 res123[12];
  958. u32 iidr26; /* Internal IRQ Destination 26 */
  959. u8 res124[12];
  960. u32 iivpr27; /* Internal IRQ Vector/Priority 27 */
  961. u8 res125[12];
  962. u32 iidr27; /* Internal IRQ Destination 27 */
  963. u8 res126[12];
  964. u32 iivpr28; /* Internal IRQ Vector/Priority 28 */
  965. u8 res127[12];
  966. u32 iidr28; /* Internal IRQ Destination 28 */
  967. u8 res128[12];
  968. u32 iivpr29; /* Internal IRQ Vector/Priority 29 */
  969. u8 res129[12];
  970. u32 iidr29; /* Internal IRQ Destination 29 */
  971. u8 res130[12];
  972. u32 iivpr30; /* Internal IRQ Vector/Priority 30 */
  973. u8 res131[12];
  974. u32 iidr30; /* Internal IRQ Destination 30 */
  975. u8 res132[12];
  976. u32 iivpr31; /* Internal IRQ Vector/Priority 31 */
  977. u8 res133[12];
  978. u32 iidr31; /* Internal IRQ Destination 31 */
  979. u8 res134[4108];
  980. u32 mivpr0; /* Messaging IRQ Vector/Priority 0 */
  981. u8 res135[12];
  982. u32 midr0; /* Messaging IRQ Destination 0 */
  983. u8 res136[12];
  984. u32 mivpr1; /* Messaging IRQ Vector/Priority 1 */
  985. u8 res137[12];
  986. u32 midr1; /* Messaging IRQ Destination 1 */
  987. u8 res138[12];
  988. u32 mivpr2; /* Messaging IRQ Vector/Priority 2 */
  989. u8 res139[12];
  990. u32 midr2; /* Messaging IRQ Destination 2 */
  991. u8 res140[12];
  992. u32 mivpr3; /* Messaging IRQ Vector/Priority 3 */
  993. u8 res141[12];
  994. u32 midr3; /* Messaging IRQ Destination 3 */
  995. u8 res142[59852];
  996. u32 ipi0dr0; /* Processor 0 Interprocessor IRQ Dispatch 0 */
  997. u8 res143[12];
  998. u32 ipi0dr1; /* Processor 0 Interprocessor IRQ Dispatch 1 */
  999. u8 res144[12];
  1000. u32 ipi0dr2; /* Processor 0 Interprocessor IRQ Dispatch 2 */
  1001. u8 res145[12];
  1002. u32 ipi0dr3; /* Processor 0 Interprocessor IRQ Dispatch 3 */
  1003. u8 res146[12];
  1004. u32 ctpr0; /* Current Task Priority for Processor 0 */
  1005. u8 res147[12];
  1006. u32 whoami0; /* Who Am I for Processor 0 */
  1007. u8 res148[12];
  1008. u32 iack0; /* IRQ Acknowledge for Processor 0 */
  1009. u8 res149[12];
  1010. u32 eoi0; /* End Of IRQ for Processor 0 */
  1011. u8 res150[130892];
  1012. } ccsr_pic_t;
  1013. /* CPM Block */
  1014. #ifndef CONFIG_CPM2
  1015. typedef struct ccsr_cpm {
  1016. u8 res[262144];
  1017. } ccsr_cpm_t;
  1018. #else
  1019. /*
  1020. * DPARM
  1021. * General SIU
  1022. */
  1023. typedef struct ccsr_cpm_siu {
  1024. u8 res1[80];
  1025. u32 smaer;
  1026. u32 smser;
  1027. u32 smevr;
  1028. u8 res2[4];
  1029. u32 lmaer;
  1030. u32 lmser;
  1031. u32 lmevr;
  1032. u8 res3[2964];
  1033. } ccsr_cpm_siu_t;
  1034. /* IRQ Controller */
  1035. typedef struct ccsr_cpm_intctl {
  1036. u16 sicr;
  1037. u8 res1[2];
  1038. u32 sivec;
  1039. u32 sipnrh;
  1040. u32 sipnrl;
  1041. u32 siprr;
  1042. u32 scprrh;
  1043. u32 scprrl;
  1044. u32 simrh;
  1045. u32 simrl;
  1046. u32 siexr;
  1047. u8 res2[88];
  1048. u32 sccr;
  1049. u8 res3[124];
  1050. } ccsr_cpm_intctl_t;
  1051. /* input/output port */
  1052. typedef struct ccsr_cpm_iop {
  1053. u32 pdira;
  1054. u32 ppara;
  1055. u32 psora;
  1056. u32 podra;
  1057. u32 pdata;
  1058. u8 res1[12];
  1059. u32 pdirb;
  1060. u32 pparb;
  1061. u32 psorb;
  1062. u32 podrb;
  1063. u32 pdatb;
  1064. u8 res2[12];
  1065. u32 pdirc;
  1066. u32 pparc;
  1067. u32 psorc;
  1068. u32 podrc;
  1069. u32 pdatc;
  1070. u8 res3[12];
  1071. u32 pdird;
  1072. u32 ppard;
  1073. u32 psord;
  1074. u32 podrd;
  1075. u32 pdatd;
  1076. u8 res4[12];
  1077. } ccsr_cpm_iop_t;
  1078. /* CPM timers */
  1079. typedef struct ccsr_cpm_timer {
  1080. u8 tgcr1;
  1081. u8 res1[3];
  1082. u8 tgcr2;
  1083. u8 res2[11];
  1084. u16 tmr1;
  1085. u16 tmr2;
  1086. u16 trr1;
  1087. u16 trr2;
  1088. u16 tcr1;
  1089. u16 tcr2;
  1090. u16 tcn1;
  1091. u16 tcn2;
  1092. u16 tmr3;
  1093. u16 tmr4;
  1094. u16 trr3;
  1095. u16 trr4;
  1096. u16 tcr3;
  1097. u16 tcr4;
  1098. u16 tcn3;
  1099. u16 tcn4;
  1100. u16 ter1;
  1101. u16 ter2;
  1102. u16 ter3;
  1103. u16 ter4;
  1104. u8 res3[608];
  1105. } ccsr_cpm_timer_t;
  1106. /* SDMA */
  1107. typedef struct ccsr_cpm_sdma {
  1108. u8 sdsr;
  1109. u8 res1[3];
  1110. u8 sdmr;
  1111. u8 res2[739];
  1112. } ccsr_cpm_sdma_t;
  1113. /* FCC1 */
  1114. typedef struct ccsr_cpm_fcc1 {
  1115. u32 gfmr;
  1116. u32 fpsmr;
  1117. u16 ftodr;
  1118. u8 res1[2];
  1119. u16 fdsr;
  1120. u8 res2[2];
  1121. u16 fcce;
  1122. u8 res3[2];
  1123. u16 fccm;
  1124. u8 res4[2];
  1125. u8 fccs;
  1126. u8 res5[3];
  1127. u8 ftirr_phy[4];
  1128. } ccsr_cpm_fcc1_t;
  1129. /* FCC2 */
  1130. typedef struct ccsr_cpm_fcc2 {
  1131. u32 gfmr;
  1132. u32 fpsmr;
  1133. u16 ftodr;
  1134. u8 res1[2];
  1135. u16 fdsr;
  1136. u8 res2[2];
  1137. u16 fcce;
  1138. u8 res3[2];
  1139. u16 fccm;
  1140. u8 res4[2];
  1141. u8 fccs;
  1142. u8 res5[3];
  1143. u8 ftirr_phy[4];
  1144. } ccsr_cpm_fcc2_t;
  1145. /* FCC3 */
  1146. typedef struct ccsr_cpm_fcc3 {
  1147. u32 gfmr;
  1148. u32 fpsmr;
  1149. u16 ftodr;
  1150. u8 res1[2];
  1151. u16 fdsr;
  1152. u8 res2[2];
  1153. u16 fcce;
  1154. u8 res3[2];
  1155. u16 fccm;
  1156. u8 res4[2];
  1157. u8 fccs;
  1158. u8 res5[3];
  1159. u8 res[36];
  1160. } ccsr_cpm_fcc3_t;
  1161. /* FCC1 extended */
  1162. typedef struct ccsr_cpm_fcc1_ext {
  1163. u32 firper;
  1164. u32 firer;
  1165. u32 firsr_h;
  1166. u32 firsr_l;
  1167. u8 gfemr;
  1168. u8 res[15];
  1169. } ccsr_cpm_fcc1_ext_t;
  1170. /* FCC2 extended */
  1171. typedef struct ccsr_cpm_fcc2_ext {
  1172. u32 firper;
  1173. u32 firer;
  1174. u32 firsr_h;
  1175. u32 firsr_l;
  1176. u8 gfemr;
  1177. u8 res[31];
  1178. } ccsr_cpm_fcc2_ext_t;
  1179. /* FCC3 extended */
  1180. typedef struct ccsr_cpm_fcc3_ext {
  1181. u8 gfemr;
  1182. u8 res[47];
  1183. } ccsr_cpm_fcc3_ext_t;
  1184. /* TC layers */
  1185. typedef struct ccsr_cpm_tmp1 {
  1186. u8 res[496];
  1187. } ccsr_cpm_tmp1_t;
  1188. /* BRGs:5,6,7,8 */
  1189. typedef struct ccsr_cpm_brg2 {
  1190. u32 brgc5;
  1191. u32 brgc6;
  1192. u32 brgc7;
  1193. u32 brgc8;
  1194. u8 res[608];
  1195. } ccsr_cpm_brg2_t;
  1196. /* I2C */
  1197. typedef struct ccsr_cpm_i2c {
  1198. u8 i2mod;
  1199. u8 res1[3];
  1200. u8 i2add;
  1201. u8 res2[3];
  1202. u8 i2brg;
  1203. u8 res3[3];
  1204. u8 i2com;
  1205. u8 res4[3];
  1206. u8 i2cer;
  1207. u8 res5[3];
  1208. u8 i2cmr;
  1209. u8 res6[331];
  1210. } ccsr_cpm_i2c_t;
  1211. /* CPM core */
  1212. typedef struct ccsr_cpm_cp {
  1213. u32 cpcr;
  1214. u32 rccr;
  1215. u8 res1[14];
  1216. u16 rter;
  1217. u8 res2[2];
  1218. u16 rtmr;
  1219. u16 rtscr;
  1220. u8 res3[2];
  1221. u32 rtsr;
  1222. u8 res4[12];
  1223. } ccsr_cpm_cp_t;
  1224. /* BRGs:1,2,3,4 */
  1225. typedef struct ccsr_cpm_brg1 {
  1226. u32 brgc1;
  1227. u32 brgc2;
  1228. u32 brgc3;
  1229. u32 brgc4;
  1230. } ccsr_cpm_brg1_t;
  1231. /* SCC1-SCC4 */
  1232. typedef struct ccsr_cpm_scc {
  1233. u32 gsmrl;
  1234. u32 gsmrh;
  1235. u16 psmr;
  1236. u8 res1[2];
  1237. u16 todr;
  1238. u16 dsr;
  1239. u16 scce;
  1240. u8 res2[2];
  1241. u16 sccm;
  1242. u8 res3;
  1243. u8 sccs;
  1244. u8 res4[8];
  1245. } ccsr_cpm_scc_t;
  1246. typedef struct ccsr_cpm_tmp2 {
  1247. u8 res[32];
  1248. } ccsr_cpm_tmp2_t;
  1249. /* SPI */
  1250. typedef struct ccsr_cpm_spi {
  1251. u16 spmode;
  1252. u8 res1[4];
  1253. u8 spie;
  1254. u8 res2[3];
  1255. u8 spim;
  1256. u8 res3[2];
  1257. u8 spcom;
  1258. u8 res4[82];
  1259. } ccsr_cpm_spi_t;
  1260. /* CPM MUX */
  1261. typedef struct ccsr_cpm_mux {
  1262. u8 cmxsi1cr;
  1263. u8 res1;
  1264. u8 cmxsi2cr;
  1265. u8 res2;
  1266. u32 cmxfcr;
  1267. u32 cmxscr;
  1268. u8 res3[2];
  1269. u16 cmxuar;
  1270. u8 res4[16];
  1271. } ccsr_cpm_mux_t;
  1272. /* SI,MCC,etc */
  1273. typedef struct ccsr_cpm_tmp3 {
  1274. u8 res[58592];
  1275. } ccsr_cpm_tmp3_t;
  1276. typedef struct ccsr_cpm_iram {
  1277. u32 iram[8192];
  1278. u8 res[98304];
  1279. } ccsr_cpm_iram_t;
  1280. typedef struct ccsr_cpm {
  1281. /* Some references are into the unique & known dpram spaces,
  1282. * others are from the generic base.
  1283. */
  1284. #define im_dprambase im_dpram1
  1285. u8 im_dpram1[16*1024];
  1286. u8 res1[16*1024];
  1287. u8 im_dpram2[16*1024];
  1288. u8 res2[16*1024];
  1289. ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
  1290. ccsr_cpm_intctl_t im_cpm_intctl; /* IRQ Controller */
  1291. ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
  1292. ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
  1293. ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
  1294. ccsr_cpm_fcc1_t im_cpm_fcc1;
  1295. ccsr_cpm_fcc2_t im_cpm_fcc2;
  1296. ccsr_cpm_fcc3_t im_cpm_fcc3;
  1297. ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext;
  1298. ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext;
  1299. ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext;
  1300. ccsr_cpm_tmp1_t im_cpm_tmp1;
  1301. ccsr_cpm_brg2_t im_cpm_brg2;
  1302. ccsr_cpm_i2c_t im_cpm_i2c;
  1303. ccsr_cpm_cp_t im_cpm_cp;
  1304. ccsr_cpm_brg1_t im_cpm_brg1;
  1305. ccsr_cpm_scc_t im_cpm_scc[4];
  1306. ccsr_cpm_tmp2_t im_cpm_tmp2;
  1307. ccsr_cpm_spi_t im_cpm_spi;
  1308. ccsr_cpm_mux_t im_cpm_mux;
  1309. ccsr_cpm_tmp3_t im_cpm_tmp3;
  1310. ccsr_cpm_iram_t im_cpm_iram;
  1311. } ccsr_cpm_t;
  1312. #endif
  1313. /* RapidIO Registers */
  1314. typedef struct ccsr_rio {
  1315. u32 didcar; /* Device Identity Capability */
  1316. u32 dicar; /* Device Information Capability */
  1317. u32 aidcar; /* Assembly Identity Capability */
  1318. u32 aicar; /* Assembly Information Capability */
  1319. u32 pefcar; /* Processing Element Features Capability */
  1320. u32 spicar; /* Switch Port Information Capability */
  1321. u32 socar; /* Source Operations Capability */
  1322. u32 docar; /* Destination Operations Capability */
  1323. u8 res1[32];
  1324. u32 msr; /* Mailbox Cmd And Status */
  1325. u32 pwdcsr; /* Port-Write & Doorbell Cmd And Status */
  1326. u8 res2[4];
  1327. u32 pellccsr; /* Processing Element Logic Layer CCSR */
  1328. u8 res3[12];
  1329. u32 lcsbacsr; /* Local Cfg Space Base Addr Cmd & Status */
  1330. u32 bdidcsr; /* Base Device ID Cmd & Status */
  1331. u8 res4[4];
  1332. u32 hbdidlcsr; /* Host Base Device ID Lock Cmd & Status */
  1333. u32 ctcsr; /* Component Tag Cmd & Status */
  1334. u8 res5[144];
  1335. u32 pmbh0csr; /* Port Maint. Block Hdr 0 Cmd & Status */
  1336. u8 res6[28];
  1337. u32 pltoccsr; /* Port Link Time-out Ctrl Cmd & Status */
  1338. u32 prtoccsr; /* Port Response Time-out Ctrl Cmd & Status */
  1339. u8 res7[20];
  1340. u32 pgccsr; /* Port General Cmd & Status */
  1341. u32 plmreqcsr; /* Port Link Maint. Request Cmd & Status */
  1342. u32 plmrespcsr; /* Port Link Maint. Response Cmd & Status */
  1343. u32 plascsr; /* Port Local Ackid Status Cmd & Status */
  1344. u8 res8[12];
  1345. u32 pescsr; /* Port Error & Status Cmd & Status */
  1346. u32 pccsr; /* Port Control Cmd & Status */
  1347. u8 res9[65184];
  1348. u32 cr; /* Port Control Cmd & Status */
  1349. u8 res10[12];
  1350. u32 pcr; /* Port Configuration */
  1351. u32 peir; /* Port Error Injection */
  1352. u8 res11[3048];
  1353. u32 rowtar0; /* RIO Outbound Window Translation Addr 0 */
  1354. u8 res12[12];
  1355. u32 rowar0; /* RIO Outbound Attrs 0 */
  1356. u8 res13[12];
  1357. u32 rowtar1; /* RIO Outbound Window Translation Addr 1 */
  1358. u8 res14[4];
  1359. u32 rowbar1; /* RIO Outbound Window Base Addr 1 */
  1360. u8 res15[4];
  1361. u32 rowar1; /* RIO Outbound Attrs 1 */
  1362. u8 res16[12];
  1363. u32 rowtar2; /* RIO Outbound Window Translation Addr 2 */
  1364. u8 res17[4];
  1365. u32 rowbar2; /* RIO Outbound Window Base Addr 2 */
  1366. u8 res18[4];
  1367. u32 rowar2; /* RIO Outbound Attrs 2 */
  1368. u8 res19[12];
  1369. u32 rowtar3; /* RIO Outbound Window Translation Addr 3 */
  1370. u8 res20[4];
  1371. u32 rowbar3; /* RIO Outbound Window Base Addr 3 */
  1372. u8 res21[4];
  1373. u32 rowar3; /* RIO Outbound Attrs 3 */
  1374. u8 res22[12];
  1375. u32 rowtar4; /* RIO Outbound Window Translation Addr 4 */
  1376. u8 res23[4];
  1377. u32 rowbar4; /* RIO Outbound Window Base Addr 4 */
  1378. u8 res24[4];
  1379. u32 rowar4; /* RIO Outbound Attrs 4 */
  1380. u8 res25[12];
  1381. u32 rowtar5; /* RIO Outbound Window Translation Addr 5 */
  1382. u8 res26[4];
  1383. u32 rowbar5; /* RIO Outbound Window Base Addr 5 */
  1384. u8 res27[4];
  1385. u32 rowar5; /* RIO Outbound Attrs 5 */
  1386. u8 res28[12];
  1387. u32 rowtar6; /* RIO Outbound Window Translation Addr 6 */
  1388. u8 res29[4];
  1389. u32 rowbar6; /* RIO Outbound Window Base Addr 6 */
  1390. u8 res30[4];
  1391. u32 rowar6; /* RIO Outbound Attrs 6 */
  1392. u8 res31[12];
  1393. u32 rowtar7; /* RIO Outbound Window Translation Addr 7 */
  1394. u8 res32[4];
  1395. u32 rowbar7; /* RIO Outbound Window Base Addr 7 */
  1396. u8 res33[4];
  1397. u32 rowar7; /* RIO Outbound Attrs 7 */
  1398. u8 res34[12];
  1399. u32 rowtar8; /* RIO Outbound Window Translation Addr 8 */
  1400. u8 res35[4];
  1401. u32 rowbar8; /* RIO Outbound Window Base Addr 8 */
  1402. u8 res36[4];
  1403. u32 rowar8; /* RIO Outbound Attrs 8 */
  1404. u8 res37[76];
  1405. u32 riwtar4; /* RIO Inbound Window Translation Addr 4 */
  1406. u8 res38[4];
  1407. u32 riwbar4; /* RIO Inbound Window Base Addr 4 */
  1408. u8 res39[4];
  1409. u32 riwar4; /* RIO Inbound Attrs 4 */
  1410. u8 res40[12];
  1411. u32 riwtar3; /* RIO Inbound Window Translation Addr 3 */
  1412. u8 res41[4];
  1413. u32 riwbar3; /* RIO Inbound Window Base Addr 3 */
  1414. u8 res42[4];
  1415. u32 riwar3; /* RIO Inbound Attrs 3 */
  1416. u8 res43[12];
  1417. u32 riwtar2; /* RIO Inbound Window Translation Addr 2 */
  1418. u8 res44[4];
  1419. u32 riwbar2; /* RIO Inbound Window Base Addr 2 */
  1420. u8 res45[4];
  1421. u32 riwar2; /* RIO Inbound Attrs 2 */
  1422. u8 res46[12];
  1423. u32 riwtar1; /* RIO Inbound Window Translation Addr 1 */
  1424. u8 res47[4];
  1425. u32 riwbar1; /* RIO Inbound Window Base Addr 1 */
  1426. u8 res48[4];
  1427. u32 riwar1; /* RIO Inbound Attrs 1 */
  1428. u8 res49[12];
  1429. u32 riwtar0; /* RIO Inbound Window Translation Addr 0 */
  1430. u8 res50[12];
  1431. u32 riwar0; /* RIO Inbound Attrs 0 */
  1432. u8 res51[12];
  1433. u32 pnfedr; /* Port Notification/Fatal Error Detect */
  1434. u32 pnfedir; /* Port Notification/Fatal Error Detect */
  1435. u32 pnfeier; /* Port Notification/Fatal Error IRQ Enable */
  1436. u32 pecr; /* Port Error Control */
  1437. u32 pepcsr0; /* Port Error Packet/Control Symbol 0 */
  1438. u32 pepr1; /* Port Error Packet 1 */
  1439. u32 pepr2; /* Port Error Packet 2 */
  1440. u8 res52[4];
  1441. u32 predr; /* Port Recoverable Error Detect */
  1442. u8 res53[4];
  1443. u32 pertr; /* Port Error Recovery Threshold */
  1444. u32 prtr; /* Port Retry Threshold */
  1445. u8 res54[464];
  1446. u32 omr; /* Outbound Mode */
  1447. u32 osr; /* Outbound Status */
  1448. u32 eodqtpar; /* Extended Outbound Desc Queue Tail Ptr Addr */
  1449. u32 odqtpar; /* Outbound Desc Queue Tail Ptr Addr */
  1450. u32 eosar; /* Extended Outbound Unit Source Addr */
  1451. u32 osar; /* Outbound Unit Source Addr */
  1452. u32 odpr; /* Outbound Destination Port */
  1453. u32 odatr; /* Outbound Destination Attrs */
  1454. u32 odcr; /* Outbound Doubleword Count */
  1455. u32 eodqhpar; /* Extended Outbound Desc Queue Head Ptr Addr */
  1456. u32 odqhpar; /* Outbound Desc Queue Head Ptr Addr */
  1457. u8 res55[52];
  1458. u32 imr; /* Outbound Mode */
  1459. u32 isr; /* Inbound Status */
  1460. u32 eidqtpar; /* Extended Inbound Desc Queue Tail Ptr Addr */
  1461. u32 idqtpar; /* Inbound Desc Queue Tail Ptr Addr */
  1462. u32 eifqhpar; /* Extended Inbound Frame Queue Head Ptr Addr */
  1463. u32 ifqhpar; /* Inbound Frame Queue Head Ptr Addr */
  1464. u8 res56[1000];
  1465. u32 dmr; /* Doorbell Mode */
  1466. u32 dsr; /* Doorbell Status */
  1467. u32 edqtpar; /* Extended Doorbell Queue Tail Ptr Addr */
  1468. u32 dqtpar; /* Doorbell Queue Tail Ptr Addr */
  1469. u32 edqhpar; /* Extended Doorbell Queue Head Ptr Addr */
  1470. u32 dqhpar; /* Doorbell Queue Head Ptr Addr */
  1471. u8 res57[104];
  1472. u32 pwmr; /* Port-Write Mode */
  1473. u32 pwsr; /* Port-Write Status */
  1474. u32 epwqbar; /* Extended Port-Write Queue Base Addr */
  1475. u32 pwqbar; /* Port-Write Queue Base Addr */
  1476. u8 res58[60176];
  1477. } ccsr_rio_t;
  1478. /* Quick Engine Block Pin Muxing Registers */
  1479. typedef struct par_io {
  1480. u32 cpodr;
  1481. u32 cpdat;
  1482. u32 cpdir1;
  1483. u32 cpdir2;
  1484. u32 cppar1;
  1485. u32 cppar2;
  1486. u8 res[8];
  1487. } par_io_t;
  1488. #ifdef CONFIG_SYS_FSL_CPC
  1489. /*
  1490. * Define a single offset that is the start of all the CPC register
  1491. * blocks - if there is more than one CPC, we expect these to be
  1492. * contiguous 4k regions
  1493. */
  1494. typedef struct cpc_corenet {
  1495. u32 cpccsr0; /* Config/status reg */
  1496. u32 res1;
  1497. u32 cpccfg0; /* Configuration register */
  1498. u32 res2;
  1499. u32 cpcewcr0; /* External Write reg 0 */
  1500. u32 cpcewabr0; /* External write base reg 0 */
  1501. u32 res3[2];
  1502. u32 cpcewcr1; /* External Write reg 1 */
  1503. u32 cpcewabr1; /* External write base reg 1 */
  1504. u32 res4[54];
  1505. u32 cpcsrcr1; /* SRAM control reg 1 */
  1506. u32 cpcsrcr0; /* SRAM control reg 0 */
  1507. u32 res5[62];
  1508. struct {
  1509. u32 id; /* partition ID */
  1510. u32 res;
  1511. u32 alloc; /* partition allocation */
  1512. u32 way; /* partition way */
  1513. } partition_regs[16];
  1514. u32 res6[704];
  1515. u32 cpcerrinjhi; /* Error injection high */
  1516. u32 cpcerrinjlo; /* Error injection lo */
  1517. u32 cpcerrinjctl; /* Error injection control */
  1518. u32 res7[5];
  1519. u32 cpccaptdatahi; /* capture data high */
  1520. u32 cpccaptdatalo; /* capture data low */
  1521. u32 cpcaptecc; /* capture ECC */
  1522. u32 res8[5];
  1523. u32 cpcerrdet; /* error detect */
  1524. u32 cpcerrdis; /* error disable */
  1525. u32 cpcerrinten; /* errir interrupt enable */
  1526. u32 cpcerrattr; /* error attribute */
  1527. u32 cpcerreaddr; /* error extended address */
  1528. u32 cpcerraddr; /* error address */
  1529. u32 cpcerrctl; /* error control */
  1530. u32 res9[41]; /* pad out to 4k */
  1531. u32 cpchdbcr0; /* hardware debug control register 0 */
  1532. u32 res10[63]; /* pad out to 4k */
  1533. } cpc_corenet_t;
  1534. #define CPC_CSR0_CE 0x80000000 /* Cache Enable */
  1535. #define CPC_CSR0_PE 0x40000000 /* Enable ECC */
  1536. #define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */
  1537. #define CPC_CSR0_WT 0x00080000 /* Write-through mode */
  1538. #define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */
  1539. #define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */
  1540. #define CPC_CFG0_SZ_MASK 0x00003fff
  1541. #define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6)
  1542. #define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1)
  1543. #define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32)
  1544. #define CPC_SRCR1_SRBARU_MASK 0x0000ffff
  1545. #define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \
  1546. & CPC_SRCR1_SRBARU_MASK)
  1547. #define CPC_SRCR0_SRBARL_MASK 0xffff8000
  1548. #define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK)
  1549. #define CPC_SRCR0_INTLVEN 0x00000100
  1550. #define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000
  1551. #define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002
  1552. #define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004
  1553. #define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006
  1554. #define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008
  1555. #define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
  1556. #define CPC_SRCR0_SRAMEN 0x00000001
  1557. #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
  1558. #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
  1559. #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000
  1560. #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000
  1561. #endif /* CONFIG_SYS_FSL_CPC */
  1562. /* Global Utilities Block */
  1563. #ifdef CONFIG_FSL_CORENET
  1564. typedef struct ccsr_gur {
  1565. u32 porsr1; /* POR status */
  1566. u8 res1[28];
  1567. u32 gpporcr1; /* General-purpose POR configuration */
  1568. u8 res2[12];
  1569. u32 gpiocr; /* GPIO control */
  1570. u8 res3[12];
  1571. u32 gpoutdr; /* General-purpose output data */
  1572. u8 res4[12];
  1573. u32 gpindr; /* General-purpose input data */
  1574. u8 res5[12];
  1575. u32 alt_pmuxcr; /* Alt function signal multiplex control */
  1576. u8 res6[12];
  1577. u32 devdisr; /* Device disable control */
  1578. #define FSL_CORENET_DEVDISR_PCIE1 0x80000000
  1579. #define FSL_CORENET_DEVDISR_PCIE2 0x40000000
  1580. #define FSL_CORENET_DEVDISR_PCIE3 0x20000000
  1581. #define FSL_CORENET_DEVDISR_PCIE4 0x10000000
  1582. #define FSL_CORENET_DEVDISR_RMU 0x08000000
  1583. #define FSL_CORENET_DEVDISR_SRIO1 0x04000000
  1584. #define FSL_CORENET_DEVDISR_SRIO2 0x02000000
  1585. #define FSL_CORENET_DEVDISR_DMA1 0x00400000
  1586. #define FSL_CORENET_DEVDISR_DMA2 0x00200000
  1587. #define FSL_CORENET_DEVDISR_DDR1 0x00100000
  1588. #define FSL_CORENET_DEVDISR_DDR2 0x00080000
  1589. #define FSL_CORENET_DEVDISR_DBG 0x00010000
  1590. #define FSL_CORENET_DEVDISR_NAL 0x00008000
  1591. #define FSL_CORENET_DEVDISR_SATA1 0x00004000
  1592. #define FSL_CORENET_DEVDISR_SATA2 0x00002000
  1593. #define FSL_CORENET_DEVDISR_ELBC 0x00001000
  1594. #define FSL_CORENET_DEVDISR_USB1 0x00000800
  1595. #define FSL_CORENET_DEVDISR_USB2 0x00000400
  1596. #define FSL_CORENET_DEVDISR_ESDHC 0x00000100
  1597. #define FSL_CORENET_DEVDISR_GPIO 0x00000080
  1598. #define FSL_CORENET_DEVDISR_ESPI 0x00000040
  1599. #define FSL_CORENET_DEVDISR_I2C1 0x00000020
  1600. #define FSL_CORENET_DEVDISR_I2C2 0x00000010
  1601. #define FSL_CORENET_DEVDISR_DUART1 0x00000002
  1602. #define FSL_CORENET_DEVDISR_DUART2 0x00000001
  1603. u32 devdisr2; /* Device disable control 2 */
  1604. #define FSL_CORENET_DEVDISR2_PME 0x80000000
  1605. #define FSL_CORENET_DEVDISR2_SEC 0x40000000
  1606. #define FSL_CORENET_DEVDISR2_QMBM 0x08000000
  1607. #define FSL_CORENET_DEVDISR2_FM1 0x02000000
  1608. #define FSL_CORENET_DEVDISR2_10GEC1 0x01000000
  1609. #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000
  1610. #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000
  1611. #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000
  1612. #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000
  1613. #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000
  1614. #define FSL_CORENET_DEVDISR2_FM2 0x00020000
  1615. #define FSL_CORENET_DEVDISR2_10GEC2 0x00010000
  1616. #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000
  1617. #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
  1618. #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
  1619. #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
  1620. #define FSL_CORENET_NUM_DEVDISR 2
  1621. u8 res7[8];
  1622. u32 powmgtcsr; /* Power management status & control */
  1623. u8 res8[12];
  1624. u32 coredisru; /* uppper portion for support of 64 cores */
  1625. u32 coredisrl; /* lower portion for support of 64 cores */
  1626. u8 res9[8];
  1627. u32 pvr; /* Processor version */
  1628. u32 svr; /* System version */
  1629. u8 res10[8];
  1630. u32 rstcr; /* Reset control */
  1631. u32 rstrqpblsr; /* Reset request preboot loader status */
  1632. u8 res11[8];
  1633. u32 rstrqmr1; /* Reset request mask */
  1634. u8 res12[4];
  1635. u32 rstrqsr1; /* Reset request status */
  1636. u8 res13[4];
  1637. u8 res14[4];
  1638. u32 rstrqwdtmrl; /* Reset request WDT mask */
  1639. u8 res15[4];
  1640. u32 rstrqwdtsrl; /* Reset request WDT status */
  1641. u8 res16[4];
  1642. u32 brrl; /* Boot release */
  1643. u8 res17[24];
  1644. u32 rcwsr[16]; /* Reset control word status */
  1645. #define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
  1646. #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
  1647. #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
  1648. #define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
  1649. #define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */
  1650. #define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */
  1651. #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
  1652. #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
  1653. #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
  1654. #define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
  1655. #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
  1656. #define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
  1657. #define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
  1658. #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000
  1659. #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
  1660. #define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
  1661. u8 res18[192];
  1662. u32 scratchrw[4]; /* Scratch Read/Write */
  1663. u8 res19[240];
  1664. u32 scratchw1r[4]; /* Scratch Read (Write once) */
  1665. u8 res20[240];
  1666. u32 scrtsr[8]; /* Core reset status */
  1667. u8 res21[224];
  1668. u32 pex1liodnr; /* PCI Express 1 LIODN */
  1669. u32 pex2liodnr; /* PCI Express 2 LIODN */
  1670. u32 pex3liodnr; /* PCI Express 3 LIODN */
  1671. u32 pex4liodnr; /* PCI Express 4 LIODN */
  1672. u32 rio1liodnr; /* RIO 1 LIODN */
  1673. u32 rio2liodnr; /* RIO 2 LIODN */
  1674. u32 rio3liodnr; /* RIO 3 LIODN */
  1675. u32 rio4liodnr; /* RIO 4 LIODN */
  1676. u32 usb1liodnr; /* USB 1 LIODN */
  1677. u32 usb2liodnr; /* USB 2 LIODN */
  1678. u32 usb3liodnr; /* USB 3 LIODN */
  1679. u32 usb4liodnr; /* USB 4 LIODN */
  1680. u32 sdmmc1liodnr; /* SD/MMC 1 LIODN */
  1681. u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */
  1682. u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */
  1683. u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */
  1684. u32 rio1maintliodnr;/* RIO 1 Maintenance LIODN */
  1685. u32 rio2maintliodnr;/* RIO 2 Maintenance LIODN */
  1686. u32 rio3maintliodnr;/* RIO 3 Maintenance LIODN */
  1687. u32 rio4maintliodnr;/* RIO 4 Maintenance LIODN */
  1688. u32 sata1liodnr; /* SATA 1 LIODN */
  1689. u32 sata2liodnr; /* SATA 2 LIODN */
  1690. u32 sata3liodnr; /* SATA 3 LIODN */
  1691. u32 sata4liodnr; /* SATA 4 LIODN */
  1692. u8 res22[32];
  1693. u32 dma1liodnr; /* DMA 1 LIODN */
  1694. u32 dma2liodnr; /* DMA 2 LIODN */
  1695. u32 dma3liodnr; /* DMA 3 LIODN */
  1696. u32 dma4liodnr; /* DMA 4 LIODN */
  1697. u8 res23[48];
  1698. u8 res24[64];
  1699. u32 pblsr; /* Preboot loader status */
  1700. u32 pamubypenr; /* PAMU bypass enable */
  1701. u32 dmacr1; /* DMA control */
  1702. u8 res25[4];
  1703. u32 gensr1; /* General status */
  1704. u8 res26[12];
  1705. u32 gencr1; /* General control */
  1706. u8 res27[12];
  1707. u8 res28[4];
  1708. u32 cgensrl; /* Core general status */
  1709. u8 res29[8];
  1710. u8 res30[4];
  1711. u32 cgencrl; /* Core general control */
  1712. u8 res31[184];
  1713. u32 sriopstecr; /* SRIO prescaler timer enable control */
  1714. u32 dcsrcr; /* DCSR Control register */
  1715. u8 res32[1784];
  1716. u32 pmuxcr; /* Pin multiplexing control */
  1717. u8 res33[60];
  1718. u32 iovselsr; /* I/O voltage selection status */
  1719. u8 res34[28];
  1720. u32 ddrclkdr; /* DDR clock disable */
  1721. u8 res35;
  1722. u32 elbcclkdr; /* eLBC clock disable */
  1723. u8 res36[20];
  1724. u32 sdhcpcr; /* eSDHC polarity configuration */
  1725. u8 res37[380];
  1726. } ccsr_gur_t;
  1727. #define FSL_CORENET_DCSR_SZ_MASK 0x00000003
  1728. #define FSL_CORENET_DCSR_SZ_4M 0x0
  1729. #define FSL_CORENET_DCSR_SZ_1G 0x3
  1730. /*
  1731. * On p4080 we have an LIODN for msg unit (rmu) but not maintenance
  1732. * everything after has RMan thus msg unit LIODN is used for maintenance
  1733. */
  1734. #define rmuliodnr rio1maintliodnr
  1735. typedef struct ccsr_clk {
  1736. u32 clkc0csr; /* Core 0 Clock control/status */
  1737. u8 res1[0x1c];
  1738. u32 clkc1csr; /* Core 1 Clock control/status */
  1739. u8 res2[0x1c];
  1740. u32 clkc2csr; /* Core 2 Clock control/status */
  1741. u8 res3[0x1c];
  1742. u32 clkc3csr; /* Core 3 Clock control/status */
  1743. u8 res4[0x1c];
  1744. u32 clkc4csr; /* Core 4 Clock control/status */
  1745. u8 res5[0x1c];
  1746. u32 clkc5csr; /* Core 5 Clock control/status */
  1747. u8 res6[0x1c];
  1748. u32 clkc6csr; /* Core 6 Clock control/status */
  1749. u8 res7[0x1c];
  1750. u32 clkc7csr; /* Core 7 Clock control/status */
  1751. u8 res8[0x71c];
  1752. u32 pllc1gsr; /* Cluster PLL 1 General Status */
  1753. u8 res10[0x1c];
  1754. u32 pllc2gsr; /* Cluster PLL 2 General Status */
  1755. u8 res11[0x1c];
  1756. u32 pllc3gsr; /* Cluster PLL 3 General Status */
  1757. u8 res12[0x1c];
  1758. u32 pllc4gsr; /* Cluster PLL 4 General Status */
  1759. u8 res13[0x39c];
  1760. u32 pllpgsr; /* Platform PLL General Status */
  1761. u8 res14[0x1c];
  1762. u32 plldgsr; /* DDR PLL General Status */
  1763. u8 res15[0x3dc];
  1764. } ccsr_clk_t;
  1765. typedef struct ccsr_rcpm {
  1766. u8 res1[4];
  1767. u32 cdozsrl; /* Core Doze Status */
  1768. u8 res2[4];
  1769. u32 cdozcrl; /* Core Doze Control */
  1770. u8 res3[4];
  1771. u32 cnapsrl; /* Core Nap Status */
  1772. u8 res4[4];
  1773. u32 cnapcrl; /* Core Nap Control */
  1774. u8 res5[4];
  1775. u32 cdozpsrl; /* Core Doze Previous Status */
  1776. u8 res6[4];
  1777. u32 cdozpcrl; /* Core Doze Previous Control */
  1778. u8 res7[4];
  1779. u32 cwaitsrl; /* Core Wait Status */
  1780. u8 res8[8];
  1781. u32 powmgtcsr; /* Power Mangement Control & Status */
  1782. u8 res9[12];
  1783. u32 ippdexpcr0; /* IP Powerdown Exception Control 0 */
  1784. u8 res10[12];
  1785. u8 res11[4];
  1786. u32 cpmimrl; /* Core PM IRQ Masking */
  1787. u8 res12[4];
  1788. u32 cpmcimrl; /* Core PM Critical IRQ Masking */
  1789. u8 res13[4];
  1790. u32 cpmmcimrl; /* Core PM Machine Check IRQ Masking */
  1791. u8 res14[4];
  1792. u32 cpmnmimrl; /* Core PM NMI Masking */
  1793. u8 res15[4];
  1794. u32 ctbenrl; /* Core Time Base Enable */
  1795. u8 res16[4];
  1796. u32 ctbclkselrl; /* Core Time Base Clock Select */
  1797. u8 res17[4];
  1798. u32 ctbhltcrl; /* Core Time Base Halt Control */
  1799. u8 res18[0xf68];
  1800. } ccsr_rcpm_t;
  1801. #else
  1802. typedef struct ccsr_gur {
  1803. u32 porpllsr; /* POR PLL ratio status */
  1804. #ifdef CONFIG_MPC8536
  1805. #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
  1806. #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
  1807. #else
  1808. #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
  1809. #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
  1810. #endif
  1811. #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
  1812. #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
  1813. #define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e
  1814. #define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1
  1815. u32 porbmsr; /* POR boot mode status */
  1816. #define MPC85xx_PORBMSR_HA 0x00070000
  1817. #define MPC85xx_PORBMSR_HA_SHIFT 16
  1818. u32 porimpscr; /* POR I/O impedance status & control */
  1819. u32 pordevsr; /* POR I/O device status regsiter */
  1820. #if defined(CONFIG_P1017) || defined(CONFIG_P1023)
  1821. #define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000
  1822. #define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000
  1823. #else
  1824. #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
  1825. #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
  1826. #endif
  1827. #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
  1828. #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
  1829. #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
  1830. #define MPC85xx_PORDEVSR_PCI1 0x00800000
  1831. #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
  1832. #define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
  1833. #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
  1834. #elif defined(CONFIG_P1017) || defined(CONFIG_P1023)
  1835. #define MPC85xx_PORDEVSR_IO_SEL 0x00600000
  1836. #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
  1837. #else
  1838. #if defined(CONFIG_P1010)
  1839. #define MPC85xx_PORDEVSR_IO_SEL 0x00600000
  1840. #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
  1841. #else
  1842. #define MPC85xx_PORDEVSR_IO_SEL 0x00780000
  1843. #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
  1844. #endif /* if defined(CONFIG_P1010) */
  1845. #endif
  1846. #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
  1847. #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
  1848. #define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
  1849. #define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
  1850. #define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
  1851. #define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
  1852. #define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
  1853. #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
  1854. u32 pordbgmsr; /* POR debug mode status */
  1855. u32 pordevsr2; /* POR I/O device status 2 */
  1856. /* The 8544 RM says this is bit 26, but it's really bit 24 */
  1857. #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
  1858. u8 res1[8];
  1859. u32 gpporcr; /* General-purpose POR configuration */
  1860. u8 res2[12];
  1861. u32 gpiocr; /* GPIO control */
  1862. u8 res3[12];
  1863. #if defined(CONFIG_MPC8569)
  1864. u32 plppar1; /* Platform port pin assignment 1 */
  1865. u32 plppar2; /* Platform port pin assignment 2 */
  1866. u32 plpdir1; /* Platform port pin direction 1 */
  1867. u32 plpdir2; /* Platform port pin direction 2 */
  1868. #else
  1869. u32 gpoutdr; /* General-purpose output data */
  1870. u8 res4[12];
  1871. #endif
  1872. u32 gpindr; /* General-purpose input data */
  1873. u8 res5[12];
  1874. u32 pmuxcr; /* Alt. function signal multiplex control */
  1875. #if defined(CONFIG_P1010) || defined(CONFIG_P1014)
  1876. #define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000
  1877. #define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000
  1878. #define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000
  1879. #define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000
  1880. #define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000
  1881. #define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000
  1882. #define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000
  1883. #define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000
  1884. #define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000
  1885. #define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000
  1886. #define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000
  1887. #define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000
  1888. #define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000
  1889. #define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000
  1890. #define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000
  1891. #define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000
  1892. #define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000
  1893. #define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000
  1894. #define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000
  1895. #define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000
  1896. #define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000
  1897. #define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000
  1898. #define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000
  1899. #define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000
  1900. #define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000
  1901. #define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000
  1902. #define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000
  1903. #define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000
  1904. #define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400
  1905. #define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800
  1906. #define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00
  1907. #define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300
  1908. #define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200
  1909. #define MPC85xx_PMUXCR_LCLK_RES 0x00000040
  1910. #define MPC85xx_PMUXCR_LCLK_USB 0x00000080
  1911. #define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0
  1912. #define MPC85xx_PMUXCR_SPI_RES 0x00000030
  1913. #define MPC85xx_PMUXCR_SPI_GPIO 0x00000020
  1914. #define MPC85xx_PMUXCR_CAN1_UART 0x00000004
  1915. #define MPC85xx_PMUXCR_CAN1_TDM 0x00000008
  1916. #define MPC85xx_PMUXCR_CAN1_RES 0x0000000C
  1917. #define MPC85xx_PMUXCR_CAN2_UART 0x00000001
  1918. #define MPC85xx_PMUXCR_CAN2_TDM 0x00000002
  1919. #define MPC85xx_PMUXCR_CAN2_RES 0x00000003
  1920. #endif
  1921. #define MPC85xx_PMUXCR_SD_DATA 0x80000000
  1922. #define MPC85xx_PMUXCR_SDHC_CD 0x40000000
  1923. #define MPC85xx_PMUXCR_SDHC_WP 0x20000000
  1924. #define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON 0x01000000
  1925. #define MPC85xx_PMUXCR_TDM_ENA 0x00800000
  1926. #define MPC85xx_PMUXCR_QE0 0x00008000
  1927. #define MPC85xx_PMUXCR_QE1 0x00004000
  1928. #define MPC85xx_PMUXCR_QE2 0x00002000
  1929. #define MPC85xx_PMUXCR_QE3 0x00001000
  1930. #define MPC85xx_PMUXCR_QE4 0x00000800
  1931. #define MPC85xx_PMUXCR_QE5 0x00000400
  1932. #define MPC85xx_PMUXCR_QE6 0x00000200
  1933. #define MPC85xx_PMUXCR_QE7 0x00000100
  1934. #define MPC85xx_PMUXCR_QE8 0x00000080
  1935. #define MPC85xx_PMUXCR_QE9 0x00000040
  1936. #define MPC85xx_PMUXCR_QE10 0x00000020
  1937. #define MPC85xx_PMUXCR_QE11 0x00000010
  1938. #define MPC85xx_PMUXCR_QE12 0x00000008
  1939. #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
  1940. #define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00
  1941. #define MPC85xx_PMUXCR_TDM 0x00014800
  1942. #define MPC85xx_PMUXCR_SPI_MASK 0x00600000
  1943. #define MPC85xx_PMUXCR_SPI 0x00000000
  1944. #endif
  1945. u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
  1946. #if defined(CONFIG_P1010) || defined(CONFIG_P1014)
  1947. #define MPC85xx_PMUXCR2_UART_GPIO 0x40000000
  1948. #define MPC85xx_PMUXCR2_UART_TDM 0x80000000
  1949. #define MPC85xx_PMUXCR2_UART_RES 0xC0000000
  1950. #define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000
  1951. #define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000
  1952. #define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000
  1953. #define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000
  1954. #define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000
  1955. #define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000
  1956. #define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000
  1957. #define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000
  1958. #define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000
  1959. #define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000
  1960. #define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000
  1961. #define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000
  1962. #define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000
  1963. #define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000
  1964. #define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000
  1965. #define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000
  1966. #define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000
  1967. #define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000
  1968. #define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000
  1969. #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000
  1970. #endif
  1971. #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
  1972. #define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000
  1973. #define MPC85xx_PMUXCR2_USB 0x00150000
  1974. #endif
  1975. u8 res6[8];
  1976. u32 devdisr; /* Device disable control */
  1977. #define MPC85xx_DEVDISR_PCI1 0x80000000
  1978. #define MPC85xx_DEVDISR_PCI2 0x40000000
  1979. #define MPC85xx_DEVDISR_PCIE 0x20000000
  1980. #define MPC85xx_DEVDISR_LBC 0x08000000
  1981. #define MPC85xx_DEVDISR_PCIE2 0x04000000
  1982. #define MPC85xx_DEVDISR_PCIE3 0x02000000
  1983. #define MPC85xx_DEVDISR_SEC 0x01000000
  1984. #define MPC85xx_DEVDISR_SRIO 0x00080000
  1985. #define MPC85xx_DEVDISR_RMSG 0x00040000
  1986. #define MPC85xx_DEVDISR_DDR 0x00010000
  1987. #define MPC85xx_DEVDISR_CPU 0x00008000
  1988. #define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
  1989. #define MPC85xx_DEVDISR_TB 0x00004000
  1990. #define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
  1991. #define MPC85xx_DEVDISR_CPU1 0x00002000
  1992. #define MPC85xx_DEVDISR_TB1 0x00001000
  1993. #define MPC85xx_DEVDISR_DMA 0x00000400
  1994. #define MPC85xx_DEVDISR_TSEC1 0x00000080
  1995. #define MPC85xx_DEVDISR_TSEC2 0x00000040
  1996. #define MPC85xx_DEVDISR_TSEC3 0x00000020
  1997. #define MPC85xx_DEVDISR_TSEC4 0x00000010
  1998. #define MPC85xx_DEVDISR_I2C 0x00000004
  1999. #define MPC85xx_DEVDISR_DUART 0x00000002
  2000. u8 res7[12];
  2001. u32 powmgtcsr; /* Power management status & control */
  2002. u8 res8[12];
  2003. u32 mcpsumr; /* Machine check summary */
  2004. u8 res9[12];
  2005. u32 pvr; /* Processor version */
  2006. u32 svr; /* System version */
  2007. u8 res10[8];
  2008. u32 rstcr; /* Reset control */
  2009. #if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
  2010. u8 res11a[76];
  2011. par_io_t qe_par_io[7];
  2012. u8 res11b[1600];
  2013. #elif defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
  2014. defined(CONFIG_P1021) || defined(CONFIG_P1025)
  2015. u8 res11a[12];
  2016. u32 iovselsr;
  2017. u8 res11b[60];
  2018. par_io_t qe_par_io[3];
  2019. u8 res11c[1496];
  2020. #else
  2021. u8 res11a[1868];
  2022. #endif
  2023. u32 clkdvdr; /* Clock Divide register */
  2024. u8 res12[1532];
  2025. u32 clkocr; /* Clock out select */
  2026. u8 res13[12];
  2027. u32 ddrdllcr; /* DDR DLL control */
  2028. u8 res14[12];
  2029. u32 lbcdllcr; /* LBC DLL control */
  2030. u8 res15[248];
  2031. u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */
  2032. u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */
  2033. u32 ddrioovcr; /* DDR IO Override Control */
  2034. u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */
  2035. u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */
  2036. u8 res16[52];
  2037. u32 sdhcdcr; /* SDHC debug control register */
  2038. u8 res17[61592];
  2039. } ccsr_gur_t;
  2040. #endif
  2041. #define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */
  2042. typedef struct serdes_corenet {
  2043. struct {
  2044. u32 rstctl; /* Reset Control Register */
  2045. #define SRDS_RSTCTL_RST 0x80000000
  2046. #define SRDS_RSTCTL_RSTDONE 0x40000000
  2047. #define SRDS_RSTCTL_RSTERR 0x20000000
  2048. #define SRDS_RSTCTL_SDPD 0x00000020
  2049. u32 pllcr0; /* PLL Control Register 0 */
  2050. #define SRDS_PLLCR0_RFCK_SEL_MASK 0x30000000
  2051. #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
  2052. #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
  2053. #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
  2054. #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
  2055. #define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000
  2056. #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
  2057. #define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000
  2058. u32 pllcr1; /* PLL Control Register 1 */
  2059. #define SRDS_PLLCR1_PLL_BWSEL 0x08000000
  2060. u32 res[5];
  2061. } bank[3];
  2062. u32 res1[12];
  2063. u32 srdstcalcr; /* TX Calibration Control */
  2064. u32 res2[3];
  2065. u32 srdsrcalcr; /* RX Calibration Control */
  2066. u32 res3[3];
  2067. u32 srdsgr0; /* General Register 0 */
  2068. u32 res4[11];
  2069. u32 srdspccr0; /* Protocol Converter Config 0 */
  2070. u32 srdspccr1; /* Protocol Converter Config 1 */
  2071. u32 srdspccr2; /* Protocol Converter Config 2 */
  2072. #define SRDS_PCCR2_RST_XGMII1 0x00800000
  2073. #define SRDS_PCCR2_RST_XGMII2 0x00400000
  2074. u32 res5[197];
  2075. struct {
  2076. u32 gcr0; /* General Control Register 0 */
  2077. #define SRDS_GCR0_RRST 0x00400000
  2078. #define SRDS_GCR0_1STLANE 0x00010000
  2079. u32 gcr1; /* General Control Register 1 */
  2080. #define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000
  2081. #define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000
  2082. #define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000
  2083. #define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000
  2084. #define SRDS_GCR1_OPAD_CTL 0x04000000
  2085. u32 res1[4];
  2086. u32 tecr0; /* TX Equalization Control Reg 0 */
  2087. #define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000
  2088. #define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000
  2089. u32 res3;
  2090. u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */
  2091. #define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000
  2092. #define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000
  2093. #define SRDS_TTLCR0_PM_DIS 0x00004000
  2094. u32 res4[7];
  2095. } lane[24];
  2096. u32 res6[384];
  2097. } serdes_corenet_t;
  2098. enum {
  2099. FSL_SRDS_B1_LANE_A = 0,
  2100. FSL_SRDS_B1_LANE_B = 1,
  2101. FSL_SRDS_B1_LANE_C = 2,
  2102. FSL_SRDS_B1_LANE_D = 3,
  2103. FSL_SRDS_B1_LANE_E = 4,
  2104. FSL_SRDS_B1_LANE_F = 5,
  2105. FSL_SRDS_B1_LANE_G = 6,
  2106. FSL_SRDS_B1_LANE_H = 7,
  2107. FSL_SRDS_B1_LANE_I = 8,
  2108. FSL_SRDS_B1_LANE_J = 9,
  2109. FSL_SRDS_B2_LANE_A = 16,
  2110. FSL_SRDS_B2_LANE_B = 17,
  2111. FSL_SRDS_B2_LANE_C = 18,
  2112. FSL_SRDS_B2_LANE_D = 19,
  2113. FSL_SRDS_B3_LANE_A = 20,
  2114. FSL_SRDS_B3_LANE_B = 21,
  2115. FSL_SRDS_B3_LANE_C = 22,
  2116. FSL_SRDS_B3_LANE_D = 23,
  2117. };
  2118. /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
  2119. #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
  2120. typedef struct ccsr_sec {
  2121. u32 res0;
  2122. u32 mcfgr; /* Master CFG Register */
  2123. u8 res1[0x8];
  2124. struct {
  2125. u32 ms; /* Job Ring LIODN Register, MS */
  2126. u32 ls; /* Job Ring LIODN Register, LS */
  2127. } jrliodnr[4];
  2128. u8 res2[0x30];
  2129. struct {
  2130. u32 ms; /* RTIC LIODN Register, MS */
  2131. u32 ls; /* RTIC LIODN Register, LS */
  2132. } rticliodnr[4];
  2133. u8 res3[0x1c];
  2134. u32 decorr; /* DECO Request Register */
  2135. struct {
  2136. u32 ms; /* DECO LIODN Register, MS */
  2137. u32 ls; /* DECO LIODN Register, LS */
  2138. } decoliodnr[5];
  2139. u8 res4[0x58];
  2140. u32 dar; /* DECO Avail Register */
  2141. u32 drr; /* DECO Reset Register */
  2142. u8 res5[0xe78];
  2143. u32 crnr_ms; /* CHA Revision Number Register, MS */
  2144. u32 crnr_ls; /* CHA Revision Number Register, LS */
  2145. u32 ctpr_ms; /* Compile Time Parameters Register, MS */
  2146. u32 ctpr_ls; /* Compile Time Parameters Register, LS */
  2147. u8 res6[0x10];
  2148. u32 far_ms; /* Fault Address Register, MS */
  2149. u32 far_ls; /* Fault Address Register, LS */
  2150. u32 falr; /* Fault Address LIODN Register */
  2151. u32 fadr; /* Fault Address Detail Register */
  2152. u8 res7[0x4];
  2153. u32 csta; /* CAAM Status Register */
  2154. u8 res8[0x8];
  2155. u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
  2156. u32 ccbvid; /* CHA Cluster Block Version ID Register */
  2157. u32 chavid_ms; /* CHA Version ID Register, MS */
  2158. u32 chavid_ls; /* CHA Version ID Register, LS */
  2159. u32 chanum_ms; /* CHA Number Register, MS */
  2160. u32 chanum_ls; /* CHA Number Register, LS */
  2161. u32 secvid_ms; /* SEC Version ID Register, MS */
  2162. u32 secvid_ls; /* SEC Version ID Register, LS */
  2163. u8 res9[0x6020];
  2164. u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
  2165. u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
  2166. u8 res10[0x8fd8];
  2167. } ccsr_sec_t;
  2168. #define SEC_CTPR_MS_AXI_LIODN 0x08000000
  2169. #define SEC_CTPR_MS_QI 0x02000000
  2170. #define SEC_RVID_MA 0x0f000000
  2171. #define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
  2172. #define SEC_CHANUM_MS_JRNUM_SHIFT 28
  2173. #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
  2174. #define SEC_CHANUM_MS_DECONUM_SHIFT 24
  2175. #endif
  2176. typedef struct ccsr_qman {
  2177. struct {
  2178. u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
  2179. u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
  2180. u32 res;
  2181. u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg */
  2182. } qcsp[32];
  2183. /* Not actually reserved, but irrelevant to u-boot */
  2184. u8 res[0xbf8 - 0x200];
  2185. u32 ip_rev_1;
  2186. u32 ip_rev_2;
  2187. u32 fqd_bare; /* FQD Extended Base Addr Register */
  2188. u32 fqd_bar; /* FQD Base Addr Register */
  2189. u8 res1[0x8];
  2190. u32 fqd_ar; /* FQD Attributes Register */
  2191. u8 res2[0xc];
  2192. u32 pfdr_bare; /* PFDR Extended Base Addr Register */
  2193. u32 pfdr_bar; /* PFDR Base Addr Register */
  2194. u8 res3[0x8];
  2195. u32 pfdr_ar; /* PFDR Attributes Register */
  2196. u8 res4[0x4c];
  2197. u32 qcsp_bare; /* QCSP Extended Base Addr Register */
  2198. u32 qcsp_bar; /* QCSP Base Addr Register */
  2199. u8 res5[0x78];
  2200. u32 ci_sched_cfg; /* Initiator Scheduling Configuration */
  2201. u32 srcidr; /* Source ID Register */
  2202. u32 liodnr; /* LIODN Register */
  2203. u8 res6[4];
  2204. u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */
  2205. u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */
  2206. u8 res7[0x2e8];
  2207. } ccsr_qman_t;
  2208. typedef struct ccsr_bman {
  2209. /* Not actually reserved, but irrelevant to u-boot */
  2210. u8 res[0xbf8];
  2211. u32 ip_rev_1;
  2212. u32 ip_rev_2;
  2213. u32 fbpr_bare; /* FBPR Extended Base Addr Register */
  2214. u32 fbpr_bar; /* FBPR Base Addr Register */
  2215. u8 res1[0x8];
  2216. u32 fbpr_ar; /* FBPR Attributes Register */
  2217. u8 res2[0xf0];
  2218. u32 srcidr; /* Source ID Register */
  2219. u32 liodnr; /* LIODN Register */
  2220. u8 res7[0x2f4];
  2221. } ccsr_bman_t;
  2222. typedef struct ccsr_pme {
  2223. u8 res0[0x804];
  2224. u32 liodnbr; /* LIODN Base Register */
  2225. u8 res1[0x1f8];
  2226. u32 srcidr; /* Source ID Register */
  2227. u8 res2[8];
  2228. u32 liodnr; /* LIODN Register */
  2229. u8 res3[0x1e8];
  2230. u32 pm_ip_rev_1; /* PME IP Block Revision Reg 1*/
  2231. u32 pm_ip_rev_2; /* PME IP Block Revision Reg 1*/
  2232. u8 res4[0x400];
  2233. } ccsr_pme_t;
  2234. typedef struct ccsr_usb_phy {
  2235. u8 res0[0x18];
  2236. u32 usb_enable_override;
  2237. u8 res[0xe4];
  2238. } ccsr_usb_phy_t;
  2239. #define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
  2240. #ifdef CONFIG_FSL_CORENET
  2241. #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
  2242. #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000
  2243. #define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000
  2244. #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
  2245. #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
  2246. #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
  2247. #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
  2248. #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
  2249. #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
  2250. #define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
  2251. #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
  2252. #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
  2253. #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
  2254. #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
  2255. #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
  2256. #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
  2257. #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
  2258. #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
  2259. #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000
  2260. #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
  2261. #define CONFIG_SYS_MPC85xx_USB_OFFSET CONFIG_SYS_MPC85xx_USB1_OFFSET
  2262. #define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
  2263. #define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
  2264. #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000
  2265. #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
  2266. #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
  2267. #define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
  2268. #define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
  2269. #define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
  2270. #define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
  2271. #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
  2272. #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
  2273. #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
  2274. #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
  2275. #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
  2276. #define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
  2277. #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
  2278. #define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
  2279. #define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
  2280. #define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
  2281. #define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
  2282. #define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
  2283. #define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
  2284. #define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
  2285. #else
  2286. #define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
  2287. #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000
  2288. #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
  2289. #define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x6000
  2290. #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
  2291. #define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
  2292. #define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
  2293. #define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000
  2294. #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
  2295. #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
  2296. #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
  2297. #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
  2298. #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
  2299. #else
  2300. #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
  2301. #endif
  2302. #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
  2303. #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
  2304. #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
  2305. #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000
  2306. #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
  2307. #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
  2308. #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000
  2309. #ifdef CONFIG_TSECV2
  2310. #define CONFIG_SYS_TSEC1_OFFSET 0xB0000
  2311. #else
  2312. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  2313. #endif
  2314. #define CONFIG_SYS_MDIO1_OFFSET 0x24000
  2315. #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
  2316. #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
  2317. #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
  2318. #define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000
  2319. #define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
  2320. #define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000
  2321. #define CONFIG_SYS_FSL_FM1_OFFSET 0x100000
  2322. #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
  2323. #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
  2324. #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
  2325. #endif
  2326. #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
  2327. #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
  2328. #define CONFIG_SYS_FSL_CPC_ADDR \
  2329. (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
  2330. #define CONFIG_SYS_FSL_QMAN_ADDR \
  2331. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
  2332. #define CONFIG_SYS_FSL_BMAN_ADDR \
  2333. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
  2334. #define CONFIG_SYS_FSL_CORENET_PME_ADDR \
  2335. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
  2336. #define CONFIG_SYS_MPC85xx_GUTS_ADDR \
  2337. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
  2338. #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
  2339. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
  2340. #define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
  2341. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
  2342. #define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
  2343. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
  2344. #define CONFIG_SYS_MPC85xx_ECM_ADDR \
  2345. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
  2346. #define CONFIG_SYS_MPC85xx_DDR_ADDR \
  2347. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET)
  2348. #define CONFIG_SYS_MPC85xx_DDR2_ADDR \
  2349. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
  2350. #define CONFIG_SYS_LBC_ADDR \
  2351. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
  2352. #define CONFIG_SYS_IFC_ADDR \
  2353. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
  2354. #define CONFIG_SYS_MPC85xx_ESPI_ADDR \
  2355. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
  2356. #define CONFIG_SYS_MPC85xx_PCIX_ADDR \
  2357. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
  2358. #define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
  2359. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
  2360. #define CONFIG_SYS_MPC85xx_GPIO_ADDR \
  2361. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
  2362. #define CONFIG_SYS_MPC85xx_SATA1_ADDR \
  2363. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
  2364. #define CONFIG_SYS_MPC85xx_SATA2_ADDR \
  2365. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
  2366. #define CONFIG_SYS_MPC85xx_L2_ADDR \
  2367. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
  2368. #define CONFIG_SYS_MPC85xx_DMA_ADDR \
  2369. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
  2370. #define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
  2371. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
  2372. #define CONFIG_SYS_MPC8xxx_PIC_ADDR \
  2373. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
  2374. #define CONFIG_SYS_MPC85xx_CPM_ADDR \
  2375. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
  2376. #define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
  2377. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
  2378. #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
  2379. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
  2380. #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
  2381. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
  2382. #define CONFIG_SYS_MPC85xx_USB_ADDR \
  2383. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
  2384. #define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
  2385. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
  2386. #define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
  2387. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
  2388. #define CONFIG_SYS_FSL_SEC_ADDR \
  2389. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
  2390. #define CONFIG_SYS_FSL_FM1_ADDR \
  2391. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
  2392. #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
  2393. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
  2394. #define CONFIG_SYS_FSL_FM2_ADDR \
  2395. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
  2396. #define CONFIG_SYS_PCI1_ADDR \
  2397. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
  2398. #define CONFIG_SYS_PCI2_ADDR \
  2399. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
  2400. #define CONFIG_SYS_PCIE1_ADDR \
  2401. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
  2402. #define CONFIG_SYS_PCIE2_ADDR \
  2403. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
  2404. #define CONFIG_SYS_PCIE3_ADDR \
  2405. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
  2406. #define CONFIG_SYS_PCIE4_ADDR \
  2407. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
  2408. #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
  2409. #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
  2410. #endif /*__IMMAP_85xx__*/