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  1. /*
  2. * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
  3. * Copyright (C) 2003 Motorola,Inc.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
  24. *
  25. * The processor starts at 0xfffffffc and the code is first executed in the
  26. * last 4K page(0xfffff000-0xffffffff) in flash/rom.
  27. *
  28. */
  29. #include <asm-offsets.h>
  30. #include <config.h>
  31. #include <mpc85xx.h>
  32. #include <version.h>
  33. #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
  34. #include <ppc_asm.tmpl>
  35. #include <ppc_defs.h>
  36. #include <asm/cache.h>
  37. #include <asm/mmu.h>
  38. #undef MSR_KERNEL
  39. #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
  40. /*
  41. * Set up GOT: Global Offset Table
  42. *
  43. * Use r12 to access the GOT
  44. */
  45. START_GOT
  46. GOT_ENTRY(_GOT2_TABLE_)
  47. GOT_ENTRY(_FIXUP_TABLE_)
  48. #ifndef CONFIG_NAND_SPL
  49. GOT_ENTRY(_start)
  50. GOT_ENTRY(_start_of_vectors)
  51. GOT_ENTRY(_end_of_vectors)
  52. GOT_ENTRY(transfer_to_handler)
  53. #endif
  54. GOT_ENTRY(__init_end)
  55. GOT_ENTRY(__bss_end__)
  56. GOT_ENTRY(__bss_start)
  57. END_GOT
  58. /*
  59. * e500 Startup -- after reset only the last 4KB of the effective
  60. * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
  61. * section is located at THIS LAST page and basically does three
  62. * things: clear some registers, set up exception tables and
  63. * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
  64. * continue the boot procedure.
  65. * Once the boot rom is mapped by TLB entries we can proceed
  66. * with normal startup.
  67. *
  68. */
  69. .section .bootpg,"ax"
  70. .globl _start_e500
  71. _start_e500:
  72. /* clear registers/arrays not reset by hardware */
  73. /* L1 */
  74. li r0,2
  75. mtspr L1CSR0,r0 /* invalidate d-cache */
  76. mtspr L1CSR1,r0 /* invalidate i-cache */
  77. mfspr r1,DBSR
  78. mtspr DBSR,r1 /* Clear all valid bits */
  79. /*
  80. * Enable L1 Caches early
  81. *
  82. */
  83. #if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
  84. /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
  85. li r2,(32 + 0)
  86. mtspr L1CSR2,r2
  87. #endif
  88. /* Enable/invalidate the I-Cache */
  89. lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
  90. ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
  91. mtspr SPRN_L1CSR1,r2
  92. 1:
  93. mfspr r3,SPRN_L1CSR1
  94. and. r1,r3,r2
  95. bne 1b
  96. lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
  97. ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
  98. mtspr SPRN_L1CSR1,r3
  99. isync
  100. 2:
  101. mfspr r3,SPRN_L1CSR1
  102. andi. r1,r3,L1CSR1_ICE@l
  103. beq 2b
  104. /* Enable/invalidate the D-Cache */
  105. lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
  106. ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
  107. mtspr SPRN_L1CSR0,r2
  108. 1:
  109. mfspr r3,SPRN_L1CSR0
  110. and. r1,r3,r2
  111. bne 1b
  112. lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
  113. ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
  114. mtspr SPRN_L1CSR0,r3
  115. isync
  116. 2:
  117. mfspr r3,SPRN_L1CSR0
  118. andi. r1,r3,L1CSR0_DCE@l
  119. beq 2b
  120. /* Setup interrupt vectors */
  121. lis r1,CONFIG_SYS_MONITOR_BASE@h
  122. mtspr IVPR,r1
  123. li r1,0x0100
  124. mtspr IVOR0,r1 /* 0: Critical input */
  125. li r1,0x0200
  126. mtspr IVOR1,r1 /* 1: Machine check */
  127. li r1,0x0300
  128. mtspr IVOR2,r1 /* 2: Data storage */
  129. li r1,0x0400
  130. mtspr IVOR3,r1 /* 3: Instruction storage */
  131. li r1,0x0500
  132. mtspr IVOR4,r1 /* 4: External interrupt */
  133. li r1,0x0600
  134. mtspr IVOR5,r1 /* 5: Alignment */
  135. li r1,0x0700
  136. mtspr IVOR6,r1 /* 6: Program check */
  137. li r1,0x0800
  138. mtspr IVOR7,r1 /* 7: floating point unavailable */
  139. li r1,0x0900
  140. mtspr IVOR8,r1 /* 8: System call */
  141. /* 9: Auxiliary processor unavailable(unsupported) */
  142. li r1,0x0a00
  143. mtspr IVOR10,r1 /* 10: Decrementer */
  144. li r1,0x0b00
  145. mtspr IVOR11,r1 /* 11: Interval timer */
  146. li r1,0x0c00
  147. mtspr IVOR12,r1 /* 12: Watchdog timer */
  148. li r1,0x0d00
  149. mtspr IVOR13,r1 /* 13: Data TLB error */
  150. li r1,0x0e00
  151. mtspr IVOR14,r1 /* 14: Instruction TLB error */
  152. li r1,0x0f00
  153. mtspr IVOR15,r1 /* 15: Debug */
  154. /* Clear and set up some registers. */
  155. li r0,0x0000
  156. lis r1,0xffff
  157. mtspr DEC,r0 /* prevent dec exceptions */
  158. mttbl r0 /* prevent fit & wdt exceptions */
  159. mttbu r0
  160. mtspr TSR,r1 /* clear all timer exception status */
  161. mtspr TCR,r0 /* disable all */
  162. mtspr ESR,r0 /* clear exception syndrome register */
  163. mtspr MCSR,r0 /* machine check syndrome register */
  164. mtxer r0 /* clear integer exception register */
  165. #ifdef CONFIG_SYS_BOOK3E_HV
  166. mtspr MAS8,r0 /* make sure MAS8 is clear */
  167. #endif
  168. /* Enable Time Base and Select Time Base Clock */
  169. lis r0,HID0_EMCP@h /* Enable machine check */
  170. #if defined(CONFIG_ENABLE_36BIT_PHYS)
  171. ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
  172. #endif
  173. #ifndef CONFIG_E500MC
  174. ori r0,r0,HID0_TBEN@l /* Enable Timebase */
  175. #endif
  176. mtspr HID0,r0
  177. #ifndef CONFIG_E500MC
  178. li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
  179. mfspr r3,PVR
  180. andi. r3,r3, 0xff
  181. cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
  182. blt 1f
  183. /* Set MBDD bit also */
  184. ori r0, r0, HID1_MBDD@l
  185. 1:
  186. mtspr HID1,r0
  187. #endif
  188. /* Enable Branch Prediction */
  189. #if defined(CONFIG_BTB)
  190. lis r0,BUCSR_ENABLE@h
  191. ori r0,r0,BUCSR_ENABLE@l
  192. mtspr SPRN_BUCSR,r0
  193. #endif
  194. #if defined(CONFIG_SYS_INIT_DBCR)
  195. lis r1,0xffff
  196. ori r1,r1,0xffff
  197. mtspr DBSR,r1 /* Clear all status bits */
  198. lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
  199. ori r0,r0,CONFIG_SYS_INIT_DBCR@l
  200. mtspr DBCR0,r0
  201. #endif
  202. #ifdef CONFIG_MPC8569
  203. #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
  204. #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
  205. /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
  206. * use address space which is more than 12bits, and it must be done in
  207. * the 4K boot page. So we set this bit here.
  208. */
  209. /* create a temp mapping TLB0[0] for LBCR */
  210. lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h
  211. ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l
  212. lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
  213. ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
  214. lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h
  215. ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l
  216. lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
  217. (MAS3_SX|MAS3_SW|MAS3_SR))@h
  218. ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
  219. (MAS3_SX|MAS3_SW|MAS3_SR))@l
  220. mtspr MAS0,r6
  221. mtspr MAS1,r7
  222. mtspr MAS2,r8
  223. mtspr MAS3,r9
  224. isync
  225. msync
  226. tlbwe
  227. /* Set LBCR register */
  228. lis r4,CONFIG_SYS_LBCR_ADDR@h
  229. ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
  230. lis r5,CONFIG_SYS_LBC_LBCR@h
  231. ori r5,r5,CONFIG_SYS_LBC_LBCR@l
  232. stw r5,0(r4)
  233. isync
  234. /* invalidate this temp TLB */
  235. lis r4,CONFIG_SYS_LBC_ADDR@h
  236. ori r4,r4,CONFIG_SYS_LBC_ADDR@l
  237. tlbivax 0,r4
  238. isync
  239. #endif /* CONFIG_MPC8569 */
  240. lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
  241. ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
  242. #ifndef CONFIG_SYS_RAMBOOT
  243. /* create a temp mapping in AS=1 to the 4M boot window */
  244. lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
  245. ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
  246. lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
  247. ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
  248. /* The 85xx has the default boot window 0xff800000 - 0xffffffff */
  249. lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
  250. ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
  251. #else
  252. /*
  253. * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
  254. * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
  255. */
  256. lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
  257. ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
  258. lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
  259. ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
  260. lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
  261. ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
  262. #endif
  263. mtspr MAS0,r6
  264. mtspr MAS1,r7
  265. mtspr MAS2,r8
  266. mtspr MAS3,r9
  267. isync
  268. msync
  269. tlbwe
  270. /* create a temp mapping in AS=1 to the stack */
  271. lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h
  272. ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l
  273. lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
  274. ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
  275. lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h
  276. ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l
  277. #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
  278. defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
  279. lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
  280. (MAS3_SX|MAS3_SW|MAS3_SR))@h
  281. ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
  282. (MAS3_SX|MAS3_SW|MAS3_SR))@l
  283. li r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH
  284. mtspr MAS7,r10
  285. #else
  286. lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
  287. ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
  288. #endif
  289. mtspr MAS0,r6
  290. mtspr MAS1,r7
  291. mtspr MAS2,r8
  292. mtspr MAS3,r9
  293. isync
  294. msync
  295. tlbwe
  296. lis r6,MSR_IS|MSR_DS@h
  297. ori r6,r6,MSR_IS|MSR_DS@l
  298. lis r7,switch_as@h
  299. ori r7,r7,switch_as@l
  300. mtspr SPRN_SRR0,r7
  301. mtspr SPRN_SRR1,r6
  302. rfi
  303. switch_as:
  304. /* L1 DCache is used for initial RAM */
  305. /* Allocate Initial RAM in data cache.
  306. */
  307. lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
  308. ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
  309. mfspr r2, L1CFG0
  310. andi. r2, r2, 0x1ff
  311. /* cache size * 1024 / (2 * L1 line size) */
  312. slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
  313. mtctr r2
  314. li r0,0
  315. 1:
  316. dcbz r0,r3
  317. dcbtls 0,r0,r3
  318. addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
  319. bdnz 1b
  320. /* Jump out the last 4K page and continue to 'normal' start */
  321. #ifdef CONFIG_SYS_RAMBOOT
  322. b _start_cont
  323. #else
  324. /* Calculate absolute address in FLASH and jump there */
  325. /*--------------------------------------------------------------*/
  326. lis r3,CONFIG_SYS_MONITOR_BASE@h
  327. ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
  328. addi r3,r3,_start_cont - _start + _START_OFFSET
  329. mtlr r3
  330. blr
  331. #endif
  332. .text
  333. .globl _start
  334. _start:
  335. .long 0x27051956 /* U-BOOT Magic Number */
  336. .globl version_string
  337. version_string:
  338. .ascii U_BOOT_VERSION_STRING, "\0"
  339. .align 4
  340. .globl _start_cont
  341. _start_cont:
  342. /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
  343. lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
  344. ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
  345. li r0,0
  346. stwu r0,-4(r1)
  347. stwu r0,-4(r1) /* Terminate call chain */
  348. stwu r1,-8(r1) /* Save back chain and move SP */
  349. lis r0,RESET_VECTOR@h /* Address of reset vector */
  350. ori r0,r0,RESET_VECTOR@l
  351. stwu r1,-8(r1) /* Save back chain and move SP */
  352. stw r0,+12(r1) /* Save return addr (underflow vect) */
  353. GET_GOT
  354. bl cpu_init_early_f
  355. /* switch back to AS = 0 */
  356. lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
  357. ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
  358. mtmsr r3
  359. isync
  360. bl cpu_init_f
  361. bl board_init_f
  362. isync
  363. /* NOTREACHED - board_init_f() does not return */
  364. #ifndef CONFIG_NAND_SPL
  365. . = EXC_OFF_SYS_RESET
  366. .globl _start_of_vectors
  367. _start_of_vectors:
  368. /* Critical input. */
  369. CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
  370. /* Machine check */
  371. MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
  372. /* Data Storage exception. */
  373. STD_EXCEPTION(0x0300, DataStorage, UnknownException)
  374. /* Instruction Storage exception. */
  375. STD_EXCEPTION(0x0400, InstStorage, UnknownException)
  376. /* External Interrupt exception. */
  377. STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
  378. /* Alignment exception. */
  379. . = 0x0600
  380. Alignment:
  381. EXCEPTION_PROLOG(SRR0, SRR1)
  382. mfspr r4,DAR
  383. stw r4,_DAR(r21)
  384. mfspr r5,DSISR
  385. stw r5,_DSISR(r21)
  386. addi r3,r1,STACK_FRAME_OVERHEAD
  387. EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
  388. /* Program check exception */
  389. . = 0x0700
  390. ProgramCheck:
  391. EXCEPTION_PROLOG(SRR0, SRR1)
  392. addi r3,r1,STACK_FRAME_OVERHEAD
  393. EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
  394. MSR_KERNEL, COPY_EE)
  395. /* No FPU on MPC85xx. This exception is not supposed to happen.
  396. */
  397. STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
  398. . = 0x0900
  399. /*
  400. * r0 - SYSCALL number
  401. * r3-... arguments
  402. */
  403. SystemCall:
  404. addis r11,r0,0 /* get functions table addr */
  405. ori r11,r11,0 /* Note: this code is patched in trap_init */
  406. addis r12,r0,0 /* get number of functions */
  407. ori r12,r12,0
  408. cmplw 0,r0,r12
  409. bge 1f
  410. rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
  411. add r11,r11,r0
  412. lwz r11,0(r11)
  413. li r20,0xd00-4 /* Get stack pointer */
  414. lwz r12,0(r20)
  415. subi r12,r12,12 /* Adjust stack pointer */
  416. li r0,0xc00+_end_back-SystemCall
  417. cmplw 0,r0,r12 /* Check stack overflow */
  418. bgt 1f
  419. stw r12,0(r20)
  420. mflr r0
  421. stw r0,0(r12)
  422. mfspr r0,SRR0
  423. stw r0,4(r12)
  424. mfspr r0,SRR1
  425. stw r0,8(r12)
  426. li r12,0xc00+_back-SystemCall
  427. mtlr r12
  428. mtspr SRR0,r11
  429. 1: SYNC
  430. rfi
  431. _back:
  432. mfmsr r11 /* Disable interrupts */
  433. li r12,0
  434. ori r12,r12,MSR_EE
  435. andc r11,r11,r12
  436. SYNC /* Some chip revs need this... */
  437. mtmsr r11
  438. SYNC
  439. li r12,0xd00-4 /* restore regs */
  440. lwz r12,0(r12)
  441. lwz r11,0(r12)
  442. mtlr r11
  443. lwz r11,4(r12)
  444. mtspr SRR0,r11
  445. lwz r11,8(r12)
  446. mtspr SRR1,r11
  447. addi r12,r12,12 /* Adjust stack pointer */
  448. li r20,0xd00-4
  449. stw r12,0(r20)
  450. SYNC
  451. rfi
  452. _end_back:
  453. STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
  454. STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
  455. STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
  456. STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
  457. STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
  458. CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
  459. .globl _end_of_vectors
  460. _end_of_vectors:
  461. . = . + (0x100 - ( . & 0xff )) /* align for debug */
  462. /*
  463. * This code finishes saving the registers to the exception frame
  464. * and jumps to the appropriate handler for the exception.
  465. * Register r21 is pointer into trap frame, r1 has new stack pointer.
  466. */
  467. .globl transfer_to_handler
  468. transfer_to_handler:
  469. stw r22,_NIP(r21)
  470. lis r22,MSR_POW@h
  471. andc r23,r23,r22
  472. stw r23,_MSR(r21)
  473. SAVE_GPR(7, r21)
  474. SAVE_4GPRS(8, r21)
  475. SAVE_8GPRS(12, r21)
  476. SAVE_8GPRS(24, r21)
  477. mflr r23
  478. andi. r24,r23,0x3f00 /* get vector offset */
  479. stw r24,TRAP(r21)
  480. li r22,0
  481. stw r22,RESULT(r21)
  482. mtspr SPRG2,r22 /* r1 is now kernel sp */
  483. lwz r24,0(r23) /* virtual address of handler */
  484. lwz r23,4(r23) /* where to go when done */
  485. mtspr SRR0,r24
  486. mtspr SRR1,r20
  487. mtlr r23
  488. SYNC
  489. rfi /* jump to handler, enable MMU */
  490. int_return:
  491. mfmsr r28 /* Disable interrupts */
  492. li r4,0
  493. ori r4,r4,MSR_EE
  494. andc r28,r28,r4
  495. SYNC /* Some chip revs need this... */
  496. mtmsr r28
  497. SYNC
  498. lwz r2,_CTR(r1)
  499. lwz r0,_LINK(r1)
  500. mtctr r2
  501. mtlr r0
  502. lwz r2,_XER(r1)
  503. lwz r0,_CCR(r1)
  504. mtspr XER,r2
  505. mtcrf 0xFF,r0
  506. REST_10GPRS(3, r1)
  507. REST_10GPRS(13, r1)
  508. REST_8GPRS(23, r1)
  509. REST_GPR(31, r1)
  510. lwz r2,_NIP(r1) /* Restore environment */
  511. lwz r0,_MSR(r1)
  512. mtspr SRR0,r2
  513. mtspr SRR1,r0
  514. lwz r0,GPR0(r1)
  515. lwz r2,GPR2(r1)
  516. lwz r1,GPR1(r1)
  517. SYNC
  518. rfi
  519. crit_return:
  520. mfmsr r28 /* Disable interrupts */
  521. li r4,0
  522. ori r4,r4,MSR_EE
  523. andc r28,r28,r4
  524. SYNC /* Some chip revs need this... */
  525. mtmsr r28
  526. SYNC
  527. lwz r2,_CTR(r1)
  528. lwz r0,_LINK(r1)
  529. mtctr r2
  530. mtlr r0
  531. lwz r2,_XER(r1)
  532. lwz r0,_CCR(r1)
  533. mtspr XER,r2
  534. mtcrf 0xFF,r0
  535. REST_10GPRS(3, r1)
  536. REST_10GPRS(13, r1)
  537. REST_8GPRS(23, r1)
  538. REST_GPR(31, r1)
  539. lwz r2,_NIP(r1) /* Restore environment */
  540. lwz r0,_MSR(r1)
  541. mtspr SPRN_CSRR0,r2
  542. mtspr SPRN_CSRR1,r0
  543. lwz r0,GPR0(r1)
  544. lwz r2,GPR2(r1)
  545. lwz r1,GPR1(r1)
  546. SYNC
  547. rfci
  548. mck_return:
  549. mfmsr r28 /* Disable interrupts */
  550. li r4,0
  551. ori r4,r4,MSR_EE
  552. andc r28,r28,r4
  553. SYNC /* Some chip revs need this... */
  554. mtmsr r28
  555. SYNC
  556. lwz r2,_CTR(r1)
  557. lwz r0,_LINK(r1)
  558. mtctr r2
  559. mtlr r0
  560. lwz r2,_XER(r1)
  561. lwz r0,_CCR(r1)
  562. mtspr XER,r2
  563. mtcrf 0xFF,r0
  564. REST_10GPRS(3, r1)
  565. REST_10GPRS(13, r1)
  566. REST_8GPRS(23, r1)
  567. REST_GPR(31, r1)
  568. lwz r2,_NIP(r1) /* Restore environment */
  569. lwz r0,_MSR(r1)
  570. mtspr SPRN_MCSRR0,r2
  571. mtspr SPRN_MCSRR1,r0
  572. lwz r0,GPR0(r1)
  573. lwz r2,GPR2(r1)
  574. lwz r1,GPR1(r1)
  575. SYNC
  576. rfmci
  577. /* Cache functions.
  578. */
  579. .globl flush_icache
  580. flush_icache:
  581. .globl invalidate_icache
  582. invalidate_icache:
  583. mfspr r0,L1CSR1
  584. ori r0,r0,L1CSR1_ICFI
  585. msync
  586. isync
  587. mtspr L1CSR1,r0
  588. isync
  589. blr /* entire I cache */
  590. .globl invalidate_dcache
  591. invalidate_dcache:
  592. mfspr r0,L1CSR0
  593. ori r0,r0,L1CSR0_DCFI
  594. msync
  595. isync
  596. mtspr L1CSR0,r0
  597. isync
  598. blr
  599. .globl icache_enable
  600. icache_enable:
  601. mflr r8
  602. bl invalidate_icache
  603. mtlr r8
  604. isync
  605. mfspr r4,L1CSR1
  606. ori r4,r4,0x0001
  607. oris r4,r4,0x0001
  608. mtspr L1CSR1,r4
  609. isync
  610. blr
  611. .globl icache_disable
  612. icache_disable:
  613. mfspr r0,L1CSR1
  614. lis r3,0
  615. ori r3,r3,L1CSR1_ICE
  616. andc r0,r0,r3
  617. mtspr L1CSR1,r0
  618. isync
  619. blr
  620. .globl icache_status
  621. icache_status:
  622. mfspr r3,L1CSR1
  623. andi. r3,r3,L1CSR1_ICE
  624. blr
  625. .globl dcache_enable
  626. dcache_enable:
  627. mflr r8
  628. bl invalidate_dcache
  629. mtlr r8
  630. isync
  631. mfspr r0,L1CSR0
  632. ori r0,r0,0x0001
  633. oris r0,r0,0x0001
  634. msync
  635. isync
  636. mtspr L1CSR0,r0
  637. isync
  638. blr
  639. .globl dcache_disable
  640. dcache_disable:
  641. mfspr r3,L1CSR0
  642. lis r4,0
  643. ori r4,r4,L1CSR0_DCE
  644. andc r3,r3,r4
  645. mtspr L1CSR0,r3
  646. isync
  647. blr
  648. .globl dcache_status
  649. dcache_status:
  650. mfspr r3,L1CSR0
  651. andi. r3,r3,L1CSR0_DCE
  652. blr
  653. .globl get_pir
  654. get_pir:
  655. mfspr r3,PIR
  656. blr
  657. .globl get_pvr
  658. get_pvr:
  659. mfspr r3,PVR
  660. blr
  661. .globl get_svr
  662. get_svr:
  663. mfspr r3,SVR
  664. blr
  665. .globl wr_tcr
  666. wr_tcr:
  667. mtspr TCR,r3
  668. blr
  669. /*------------------------------------------------------------------------------- */
  670. /* Function: in8 */
  671. /* Description: Input 8 bits */
  672. /*------------------------------------------------------------------------------- */
  673. .globl in8
  674. in8:
  675. lbz r3,0x0000(r3)
  676. blr
  677. /*------------------------------------------------------------------------------- */
  678. /* Function: out8 */
  679. /* Description: Output 8 bits */
  680. /*------------------------------------------------------------------------------- */
  681. .globl out8
  682. out8:
  683. stb r4,0x0000(r3)
  684. sync
  685. blr
  686. /*------------------------------------------------------------------------------- */
  687. /* Function: out16 */
  688. /* Description: Output 16 bits */
  689. /*------------------------------------------------------------------------------- */
  690. .globl out16
  691. out16:
  692. sth r4,0x0000(r3)
  693. sync
  694. blr
  695. /*------------------------------------------------------------------------------- */
  696. /* Function: out16r */
  697. /* Description: Byte reverse and output 16 bits */
  698. /*------------------------------------------------------------------------------- */
  699. .globl out16r
  700. out16r:
  701. sthbrx r4,r0,r3
  702. sync
  703. blr
  704. /*------------------------------------------------------------------------------- */
  705. /* Function: out32 */
  706. /* Description: Output 32 bits */
  707. /*------------------------------------------------------------------------------- */
  708. .globl out32
  709. out32:
  710. stw r4,0x0000(r3)
  711. sync
  712. blr
  713. /*------------------------------------------------------------------------------- */
  714. /* Function: out32r */
  715. /* Description: Byte reverse and output 32 bits */
  716. /*------------------------------------------------------------------------------- */
  717. .globl out32r
  718. out32r:
  719. stwbrx r4,r0,r3
  720. sync
  721. blr
  722. /*------------------------------------------------------------------------------- */
  723. /* Function: in16 */
  724. /* Description: Input 16 bits */
  725. /*------------------------------------------------------------------------------- */
  726. .globl in16
  727. in16:
  728. lhz r3,0x0000(r3)
  729. blr
  730. /*------------------------------------------------------------------------------- */
  731. /* Function: in16r */
  732. /* Description: Input 16 bits and byte reverse */
  733. /*------------------------------------------------------------------------------- */
  734. .globl in16r
  735. in16r:
  736. lhbrx r3,r0,r3
  737. blr
  738. /*------------------------------------------------------------------------------- */
  739. /* Function: in32 */
  740. /* Description: Input 32 bits */
  741. /*------------------------------------------------------------------------------- */
  742. .globl in32
  743. in32:
  744. lwz 3,0x0000(3)
  745. blr
  746. /*------------------------------------------------------------------------------- */
  747. /* Function: in32r */
  748. /* Description: Input 32 bits and byte reverse */
  749. /*------------------------------------------------------------------------------- */
  750. .globl in32r
  751. in32r:
  752. lwbrx r3,r0,r3
  753. blr
  754. #endif /* !CONFIG_NAND_SPL */
  755. /*------------------------------------------------------------------------------*/
  756. /*
  757. * void write_tlb(mas0, mas1, mas2, mas3, mas7)
  758. */
  759. .globl write_tlb
  760. write_tlb:
  761. mtspr MAS0,r3
  762. mtspr MAS1,r4
  763. mtspr MAS2,r5
  764. mtspr MAS3,r6
  765. #ifdef CONFIG_ENABLE_36BIT_PHYS
  766. mtspr MAS7,r7
  767. #endif
  768. li r3,0
  769. #ifdef CONFIG_SYS_BOOK3E_HV
  770. mtspr MAS8,r3
  771. #endif
  772. isync
  773. tlbwe
  774. msync
  775. isync
  776. blr
  777. /*
  778. * void relocate_code (addr_sp, gd, addr_moni)
  779. *
  780. * This "function" does not return, instead it continues in RAM
  781. * after relocating the monitor code.
  782. *
  783. * r3 = dest
  784. * r4 = src
  785. * r5 = length in bytes
  786. * r6 = cachelinesize
  787. */
  788. .globl relocate_code
  789. relocate_code:
  790. mr r1,r3 /* Set new stack pointer */
  791. mr r9,r4 /* Save copy of Init Data pointer */
  792. mr r10,r5 /* Save copy of Destination Address */
  793. GET_GOT
  794. mr r3,r5 /* Destination Address */
  795. lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
  796. ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
  797. lwz r5,GOT(__init_end)
  798. sub r5,r5,r4
  799. li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
  800. /*
  801. * Fix GOT pointer:
  802. *
  803. * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
  804. *
  805. * Offset:
  806. */
  807. sub r15,r10,r4
  808. /* First our own GOT */
  809. add r12,r12,r15
  810. /* the the one used by the C code */
  811. add r30,r30,r15
  812. /*
  813. * Now relocate code
  814. */
  815. cmplw cr1,r3,r4
  816. addi r0,r5,3
  817. srwi. r0,r0,2
  818. beq cr1,4f /* In place copy is not necessary */
  819. beq 7f /* Protect against 0 count */
  820. mtctr r0
  821. bge cr1,2f
  822. la r8,-4(r4)
  823. la r7,-4(r3)
  824. 1: lwzu r0,4(r8)
  825. stwu r0,4(r7)
  826. bdnz 1b
  827. b 4f
  828. 2: slwi r0,r0,2
  829. add r8,r4,r0
  830. add r7,r3,r0
  831. 3: lwzu r0,-4(r8)
  832. stwu r0,-4(r7)
  833. bdnz 3b
  834. /*
  835. * Now flush the cache: note that we must start from a cache aligned
  836. * address. Otherwise we might miss one cache line.
  837. */
  838. 4: cmpwi r6,0
  839. add r5,r3,r5
  840. beq 7f /* Always flush prefetch queue in any case */
  841. subi r0,r6,1
  842. andc r3,r3,r0
  843. mr r4,r3
  844. 5: dcbst 0,r4
  845. add r4,r4,r6
  846. cmplw r4,r5
  847. blt 5b
  848. sync /* Wait for all dcbst to complete on bus */
  849. mr r4,r3
  850. 6: icbi 0,r4
  851. add r4,r4,r6
  852. cmplw r4,r5
  853. blt 6b
  854. 7: sync /* Wait for all icbi to complete on bus */
  855. isync
  856. /*
  857. * Re-point the IVPR at RAM
  858. */
  859. mtspr IVPR,r10
  860. /*
  861. * We are done. Do not return, instead branch to second part of board
  862. * initialization, now running from RAM.
  863. */
  864. addi r0,r10,in_ram - _start + _START_OFFSET
  865. mtlr r0
  866. blr /* NEVER RETURNS! */
  867. .globl in_ram
  868. in_ram:
  869. /*
  870. * Relocation Function, r12 point to got2+0x8000
  871. *
  872. * Adjust got2 pointers, no need to check for 0, this code
  873. * already puts a few entries in the table.
  874. */
  875. li r0,__got2_entries@sectoff@l
  876. la r3,GOT(_GOT2_TABLE_)
  877. lwz r11,GOT(_GOT2_TABLE_)
  878. mtctr r0
  879. sub r11,r3,r11
  880. addi r3,r3,-4
  881. 1: lwzu r0,4(r3)
  882. cmpwi r0,0
  883. beq- 2f
  884. add r0,r0,r11
  885. stw r0,0(r3)
  886. 2: bdnz 1b
  887. /*
  888. * Now adjust the fixups and the pointers to the fixups
  889. * in case we need to move ourselves again.
  890. */
  891. li r0,__fixup_entries@sectoff@l
  892. lwz r3,GOT(_FIXUP_TABLE_)
  893. cmpwi r0,0
  894. mtctr r0
  895. addi r3,r3,-4
  896. beq 4f
  897. 3: lwzu r4,4(r3)
  898. lwzux r0,r4,r11
  899. cmpwi r0,0
  900. add r0,r0,r11
  901. stw r4,0(r3)
  902. beq- 5f
  903. stw r0,0(r4)
  904. 5: bdnz 3b
  905. 4:
  906. clear_bss:
  907. /*
  908. * Now clear BSS segment
  909. */
  910. lwz r3,GOT(__bss_start)
  911. lwz r4,GOT(__bss_end__)
  912. cmplw 0,r3,r4
  913. beq 6f
  914. li r0,0
  915. 5:
  916. stw r0,0(r3)
  917. addi r3,r3,4
  918. cmplw 0,r3,r4
  919. bne 5b
  920. 6:
  921. mr r3,r9 /* Init Data pointer */
  922. mr r4,r10 /* Destination Address */
  923. bl board_init_r
  924. #ifndef CONFIG_NAND_SPL
  925. /*
  926. * Copy exception vector code to low memory
  927. *
  928. * r3: dest_addr
  929. * r7: source address, r8: end address, r9: target address
  930. */
  931. .globl trap_init
  932. trap_init:
  933. mflr r4 /* save link register */
  934. GET_GOT
  935. lwz r7,GOT(_start_of_vectors)
  936. lwz r8,GOT(_end_of_vectors)
  937. li r9,0x100 /* reset vector always at 0x100 */
  938. cmplw 0,r7,r8
  939. bgelr /* return if r7>=r8 - just in case */
  940. 1:
  941. lwz r0,0(r7)
  942. stw r0,0(r9)
  943. addi r7,r7,4
  944. addi r9,r9,4
  945. cmplw 0,r7,r8
  946. bne 1b
  947. /*
  948. * relocate `hdlr' and `int_return' entries
  949. */
  950. li r7,.L_CriticalInput - _start + _START_OFFSET
  951. bl trap_reloc
  952. li r7,.L_MachineCheck - _start + _START_OFFSET
  953. bl trap_reloc
  954. li r7,.L_DataStorage - _start + _START_OFFSET
  955. bl trap_reloc
  956. li r7,.L_InstStorage - _start + _START_OFFSET
  957. bl trap_reloc
  958. li r7,.L_ExtInterrupt - _start + _START_OFFSET
  959. bl trap_reloc
  960. li r7,.L_Alignment - _start + _START_OFFSET
  961. bl trap_reloc
  962. li r7,.L_ProgramCheck - _start + _START_OFFSET
  963. bl trap_reloc
  964. li r7,.L_FPUnavailable - _start + _START_OFFSET
  965. bl trap_reloc
  966. li r7,.L_Decrementer - _start + _START_OFFSET
  967. bl trap_reloc
  968. li r7,.L_IntervalTimer - _start + _START_OFFSET
  969. li r8,_end_of_vectors - _start + _START_OFFSET
  970. 2:
  971. bl trap_reloc
  972. addi r7,r7,0x100 /* next exception vector */
  973. cmplw 0,r7,r8
  974. blt 2b
  975. lis r7,0x0
  976. mtspr IVPR,r7
  977. mtlr r4 /* restore link register */
  978. blr
  979. .globl unlock_ram_in_cache
  980. unlock_ram_in_cache:
  981. /* invalidate the INIT_RAM section */
  982. lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
  983. ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
  984. mfspr r4,L1CFG0
  985. andi. r4,r4,0x1ff
  986. slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
  987. mtctr r4
  988. 1: dcbi r0,r3
  989. addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
  990. bdnz 1b
  991. sync
  992. /* Invalidate the TLB entries for the cache */
  993. lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
  994. ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
  995. tlbivax 0,r3
  996. addi r3,r3,0x1000
  997. tlbivax 0,r3
  998. addi r3,r3,0x1000
  999. tlbivax 0,r3
  1000. addi r3,r3,0x1000
  1001. tlbivax 0,r3
  1002. isync
  1003. blr
  1004. .globl flush_dcache
  1005. flush_dcache:
  1006. mfspr r3,SPRN_L1CFG0
  1007. rlwinm r5,r3,9,3 /* Extract cache block size */
  1008. twlgti r5,1 /* Only 32 and 64 byte cache blocks
  1009. * are currently defined.
  1010. */
  1011. li r4,32
  1012. subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
  1013. * log2(number of ways)
  1014. */
  1015. slw r5,r4,r5 /* r5 = cache block size */
  1016. rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
  1017. mulli r7,r7,13 /* An 8-way cache will require 13
  1018. * loads per set.
  1019. */
  1020. slw r7,r7,r6
  1021. /* save off HID0 and set DCFA */
  1022. mfspr r8,SPRN_HID0
  1023. ori r9,r8,HID0_DCFA@l
  1024. mtspr SPRN_HID0,r9
  1025. isync
  1026. lis r4,0
  1027. mtctr r7
  1028. 1: lwz r3,0(r4) /* Load... */
  1029. add r4,r4,r5
  1030. bdnz 1b
  1031. msync
  1032. lis r4,0
  1033. mtctr r7
  1034. 1: dcbf 0,r4 /* ...and flush. */
  1035. add r4,r4,r5
  1036. bdnz 1b
  1037. /* restore HID0 */
  1038. mtspr SPRN_HID0,r8
  1039. isync
  1040. blr
  1041. .globl setup_ivors
  1042. setup_ivors:
  1043. #include "fixed_ivor.S"
  1044. blr
  1045. #endif /* !CONFIG_NAND_SPL */