release.S 7.7 KB

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  1. /*
  2. * Copyright 2008-2011 Freescale Semiconductor, Inc.
  3. * Kumar Gala <kumar.gala@freescale.com>
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <asm-offsets.h>
  24. #include <config.h>
  25. #include <mpc85xx.h>
  26. #include <version.h>
  27. #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
  28. #include <ppc_asm.tmpl>
  29. #include <ppc_defs.h>
  30. #include <asm/cache.h>
  31. #include <asm/mmu.h>
  32. /* To boot secondary cpus, we need a place for them to start up.
  33. * Normally, they start at 0xfffffffc, but that's usually the
  34. * firmware, and we don't want to have to run the firmware again.
  35. * Instead, the primary cpu will set the BPTR to point here to
  36. * this page. We then set up the core, and head to
  37. * start_secondary. Note that this means that the code below
  38. * must never exceed 1023 instructions (the branch at the end
  39. * would then be the 1024th).
  40. */
  41. .globl __secondary_start_page
  42. .align 12
  43. __secondary_start_page:
  44. /* First do some preliminary setup */
  45. lis r3, HID0_EMCP@h /* enable machine check */
  46. #ifndef CONFIG_E500MC
  47. ori r3,r3,HID0_TBEN@l /* enable Timebase */
  48. #endif
  49. #ifdef CONFIG_PHYS_64BIT
  50. ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
  51. #endif
  52. mtspr SPRN_HID0,r3
  53. #ifndef CONFIG_E500MC
  54. li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
  55. mfspr r0,PVR
  56. andi. r0,r0,0xff
  57. cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */
  58. blt 1f
  59. /* Set MBDD bit also */
  60. ori r3, r3, HID1_MBDD@l
  61. 1:
  62. mtspr SPRN_HID1,r3
  63. #endif
  64. /* Enable branch prediction */
  65. lis r3,BUCSR_ENABLE@h
  66. ori r3,r3,BUCSR_ENABLE@l
  67. mtspr SPRN_BUCSR,r3
  68. /* Ensure TB is 0 */
  69. li r3,0
  70. mttbl r3
  71. mttbu r3
  72. /* Enable/invalidate the I-Cache */
  73. lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
  74. ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
  75. mtspr SPRN_L1CSR1,r2
  76. 1:
  77. mfspr r3,SPRN_L1CSR1
  78. and. r1,r3,r2
  79. bne 1b
  80. lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
  81. ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
  82. mtspr SPRN_L1CSR1,r3
  83. isync
  84. 2:
  85. mfspr r3,SPRN_L1CSR1
  86. andi. r1,r3,L1CSR1_ICE@l
  87. beq 2b
  88. /* Enable/invalidate the D-Cache */
  89. lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
  90. ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
  91. mtspr SPRN_L1CSR0,r2
  92. 1:
  93. mfspr r3,SPRN_L1CSR0
  94. and. r1,r3,r2
  95. bne 1b
  96. lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
  97. ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
  98. mtspr SPRN_L1CSR0,r3
  99. isync
  100. 2:
  101. mfspr r3,SPRN_L1CSR0
  102. andi. r1,r3,L1CSR0_DCE@l
  103. beq 2b
  104. #define toreset(x) (x - __secondary_start_page + 0xfffff000)
  105. /* get our PIR to figure out our table entry */
  106. lis r3,toreset(__spin_table)@h
  107. ori r3,r3,toreset(__spin_table)@l
  108. /* r10 has the base address for the entry */
  109. mfspr r0,SPRN_PIR
  110. #ifdef CONFIG_E500MC
  111. rlwinm r4,r0,27,27,31
  112. #else
  113. mr r4,r0
  114. #endif
  115. slwi r8,r4,5
  116. add r10,r3,r8
  117. #if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
  118. /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
  119. slwi r8,r4,1
  120. addi r8,r8,32
  121. mtspr L1CSR2,r8
  122. #endif
  123. #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
  124. mfspr r8,L1CSR2
  125. oris r8,r8,(L1CSR2_DCWS)@h
  126. mtspr L1CSR2,r8
  127. #endif
  128. #ifdef CONFIG_BACKSIDE_L2_CACHE
  129. /* skip L2 setup on P2040/P2040E as they have no L2 */
  130. mfspr r2,SPRN_SVR
  131. lis r3,SVR_P2040@h
  132. ori r3,r3,SVR_P2040@l
  133. cmpw r2,r3
  134. beq 3f
  135. lis r3,SVR_P2040_E@h
  136. ori r3,r3,SVR_P2040_E@l
  137. cmpw r2,r3
  138. beq 3f
  139. /* Enable/invalidate the L2 cache */
  140. msync
  141. lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
  142. ori r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
  143. mtspr SPRN_L2CSR0,r2
  144. 1:
  145. mfspr r3,SPRN_L2CSR0
  146. and. r1,r3,r2
  147. bne 1b
  148. #ifdef CONFIG_SYS_CACHE_STASHING
  149. /* set stash id to (coreID) * 2 + 32 + L2 (1) */
  150. addi r3,r8,1
  151. mtspr SPRN_L2CSR1,r3
  152. #endif
  153. lis r3,CONFIG_SYS_INIT_L2CSR0@h
  154. ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l
  155. mtspr SPRN_L2CSR0,r3
  156. isync
  157. 2:
  158. mfspr r3,SPRN_L2CSR0
  159. andis. r1,r3,L2CSR0_L2E@h
  160. beq 2b
  161. #endif
  162. 3:
  163. #define EPAPR_MAGIC (0x45504150)
  164. #define ENTRY_ADDR_UPPER 0
  165. #define ENTRY_ADDR_LOWER 4
  166. #define ENTRY_R3_UPPER 8
  167. #define ENTRY_R3_LOWER 12
  168. #define ENTRY_RESV 16
  169. #define ENTRY_PIR 20
  170. #define ENTRY_R6_UPPER 24
  171. #define ENTRY_R6_LOWER 28
  172. #define ENTRY_SIZE 32
  173. /* setup the entry */
  174. li r3,0
  175. li r8,1
  176. stw r0,ENTRY_PIR(r10)
  177. stw r3,ENTRY_ADDR_UPPER(r10)
  178. stw r8,ENTRY_ADDR_LOWER(r10)
  179. stw r3,ENTRY_R3_UPPER(r10)
  180. stw r4,ENTRY_R3_LOWER(r10)
  181. stw r3,ENTRY_R6_UPPER(r10)
  182. stw r3,ENTRY_R6_LOWER(r10)
  183. /* load r13 with the address of the 'bootpg' in SDRAM */
  184. lis r13,toreset(__bootpg_addr)@h
  185. ori r13,r13,toreset(__bootpg_addr)@l
  186. lwz r13,0(r13)
  187. /* setup mapping for AS = 1, and jump there */
  188. lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
  189. mtspr SPRN_MAS0,r11
  190. lis r11,(MAS1_VALID|MAS1_IPROT)@h
  191. ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
  192. mtspr SPRN_MAS1,r11
  193. oris r11,r13,(MAS2_I|MAS2_G)@h
  194. ori r11,r13,(MAS2_I|MAS2_G)@l
  195. mtspr SPRN_MAS2,r11
  196. oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
  197. ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
  198. mtspr SPRN_MAS3,r11
  199. tlbwe
  200. bl 1f
  201. 1: mflr r11
  202. /*
  203. * OR in 0xfff to create a mask of the bootpg SDRAM address. We use
  204. * this mask to fixup the cpu spin table and the address that we want
  205. * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the
  206. * bootpg is at 0x7ffff000 in SDRAM.
  207. */
  208. ori r13,r13,0xfff
  209. and r11, r11, r13
  210. and r10, r10, r13
  211. addi r11,r11,(2f-1b)
  212. mfmsr r13
  213. ori r12,r13,MSR_IS|MSR_DS@l
  214. mtspr SPRN_SRR0,r11
  215. mtspr SPRN_SRR1,r12
  216. rfi
  217. /* spin waiting for addr */
  218. 2:
  219. lwz r4,ENTRY_ADDR_LOWER(r10)
  220. andi. r11,r4,1
  221. bne 2b
  222. isync
  223. /* setup IVORs to match fixed offsets */
  224. #include "fixed_ivor.S"
  225. /* get the upper bits of the addr */
  226. lwz r11,ENTRY_ADDR_UPPER(r10)
  227. /* setup branch addr */
  228. mtspr SPRN_SRR0,r4
  229. /* mark the entry as released */
  230. li r8,3
  231. stw r8,ENTRY_ADDR_LOWER(r10)
  232. /* mask by ~64M to setup our tlb we will jump to */
  233. rlwinm r12,r4,0,0,5
  234. /* setup r3, r4, r5, r6, r7, r8, r9 */
  235. lwz r3,ENTRY_R3_LOWER(r10)
  236. li r4,0
  237. li r5,0
  238. lwz r6,ENTRY_R6_LOWER(r10)
  239. lis r7,(64*1024*1024)@h
  240. li r8,0
  241. li r9,0
  242. /* load up the pir */
  243. lwz r0,ENTRY_PIR(r10)
  244. mtspr SPRN_PIR,r0
  245. mfspr r0,SPRN_PIR
  246. stw r0,ENTRY_PIR(r10)
  247. mtspr IVPR,r12
  248. /*
  249. * Coming here, we know the cpu has one TLB mapping in TLB1[0]
  250. * which maps 0xfffff000-0xffffffff one-to-one. We set up a
  251. * second mapping that maps addr 1:1 for 64M, and then we jump to
  252. * addr
  253. */
  254. lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
  255. mtspr SPRN_MAS0,r10
  256. lis r10,(MAS1_VALID|MAS1_IPROT)@h
  257. ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
  258. mtspr SPRN_MAS1,r10
  259. /* WIMGE = 0b00000 for now */
  260. mtspr SPRN_MAS2,r12
  261. ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
  262. mtspr SPRN_MAS3,r12
  263. #ifdef CONFIG_ENABLE_36BIT_PHYS
  264. mtspr SPRN_MAS7,r11
  265. #endif
  266. tlbwe
  267. /* Now we have another mapping for this page, so we jump to that
  268. * mapping
  269. */
  270. mtspr SPRN_SRR1,r13
  271. rfi
  272. /*
  273. * Allocate some space for the SDRAM address of the bootpg.
  274. * This variable has to be in the boot page so that it can
  275. * be accessed by secondary cores when they come out of reset.
  276. */
  277. .globl __bootpg_addr
  278. __bootpg_addr:
  279. .long 0
  280. .align L1_CACHE_SHIFT
  281. .globl __spin_table
  282. __spin_table:
  283. .space CONFIG_MAX_CPUS*ENTRY_SIZE
  284. /* Fill in the empty space. The actual reset vector is
  285. * the last word of the page */
  286. __secondary_start_code_end:
  287. .space 4092 - (__secondary_start_code_end - __secondary_start_page)
  288. __secondary_reset_vector:
  289. b __secondary_start_page