Kconfig 10 KB

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  1. config ARCH_MAP_SYSMEM
  2. depends on SANDBOX || NDS32
  3. def_bool y
  4. config CREATE_ARCH_SYMLINK
  5. bool
  6. config HAVE_ARCH_IOREMAP
  7. bool
  8. config NEEDS_MANUAL_RELOC
  9. bool
  10. config SYS_CACHE_SHIFT_4
  11. bool
  12. config SYS_CACHE_SHIFT_5
  13. bool
  14. config SYS_CACHE_SHIFT_6
  15. bool
  16. config SYS_CACHE_SHIFT_7
  17. bool
  18. config SYS_CACHELINE_SIZE
  19. int
  20. default 128 if SYS_CACHE_SHIFT_7
  21. default 64 if SYS_CACHE_SHIFT_6
  22. default 32 if SYS_CACHE_SHIFT_5
  23. default 16 if SYS_CACHE_SHIFT_4
  24. # Fall-back for MIPS
  25. default 32 if MIPS
  26. config LINKER_LIST_ALIGN
  27. int
  28. default 32 if SANDBOX
  29. default 8 if ARM64 || X86
  30. default 4
  31. help
  32. Force the each linker list to be aligned to this boundary. This
  33. is required if ll_entry_get() is used, since otherwise the linker
  34. may add padding into the table, thus breaking it.
  35. See linker_lists.rst for full details.
  36. choice
  37. prompt "Architecture select"
  38. default SANDBOX
  39. config ARC
  40. bool "ARC architecture"
  41. select ARC_TIMER
  42. select CLK
  43. select DM
  44. select HAVE_PRIVATE_LIBGCC
  45. select SUPPORT_OF_CONTROL
  46. select SYS_CACHE_SHIFT_7
  47. select TIMER
  48. config ARM
  49. bool "ARM architecture"
  50. select ARCH_SUPPORTS_LTO
  51. select CREATE_ARCH_SYMLINK
  52. select HAVE_PRIVATE_LIBGCC if !ARM64
  53. select SUPPORT_OF_CONTROL
  54. config M68K
  55. bool "M68000 architecture"
  56. select HAVE_PRIVATE_LIBGCC
  57. select NEEDS_MANUAL_RELOC
  58. select SYS_BOOT_GET_CMDLINE
  59. select SYS_BOOT_GET_KBD
  60. select SYS_CACHE_SHIFT_4
  61. select SUPPORT_OF_CONTROL
  62. config MICROBLAZE
  63. bool "MicroBlaze architecture"
  64. select NEEDS_MANUAL_RELOC
  65. select SUPPORT_OF_CONTROL
  66. imply CMD_IRQ
  67. config MIPS
  68. bool "MIPS architecture"
  69. select HAVE_ARCH_IOREMAP
  70. select HAVE_PRIVATE_LIBGCC
  71. select SUPPORT_OF_CONTROL
  72. config NDS32
  73. bool "NDS32 architecture"
  74. select SUPPORT_OF_CONTROL
  75. config NIOS2
  76. bool "Nios II architecture"
  77. select CPU
  78. select DM
  79. select OF_CONTROL
  80. select SUPPORT_OF_CONTROL
  81. imply CMD_DM
  82. config PPC
  83. bool "PowerPC architecture"
  84. select HAVE_PRIVATE_LIBGCC
  85. select SUPPORT_OF_CONTROL
  86. select SYS_BOOT_GET_CMDLINE
  87. select SYS_BOOT_GET_KBD
  88. config RISCV
  89. bool "RISC-V architecture"
  90. select CREATE_ARCH_SYMLINK
  91. select SUPPORT_OF_CONTROL
  92. select OF_CONTROL
  93. select DM
  94. imply DM_SERIAL
  95. imply DM_ETH
  96. imply DM_MMC
  97. imply DM_SPI
  98. imply DM_SPI_FLASH
  99. imply BLK
  100. imply CLK
  101. imply MTD
  102. imply TIMER
  103. imply CMD_DM
  104. imply SPL_DM
  105. imply SPL_OF_CONTROL
  106. imply SPL_LIBCOMMON_SUPPORT
  107. imply SPL_LIBGENERIC_SUPPORT
  108. imply SPL_SERIAL
  109. imply SPL_TIMER
  110. config SANDBOX
  111. bool "Sandbox"
  112. select ARCH_SUPPORTS_LTO
  113. select BOARD_LATE_INIT
  114. select BZIP2
  115. select CMD_POWEROFF
  116. select DM
  117. select DM_GPIO
  118. select DM_I2C
  119. select DM_KEYBOARD
  120. select DM_MMC
  121. select DM_SERIAL
  122. select DM_SPI
  123. select DM_SPI_FLASH
  124. select GZIP_COMPRESSED
  125. select HAVE_BLOCK_DEVICE
  126. select LZO
  127. select OF_BOARD_SETUP
  128. select PCI_ENDPOINT
  129. select SPI
  130. select SUPPORT_OF_CONTROL
  131. select SYSRESET_CMD_POWEROFF
  132. select SYS_CACHE_SHIFT_4
  133. select IRQ
  134. select SUPPORT_EXTENSION_SCAN
  135. imply BITREVERSE
  136. select BLOBLIST
  137. imply LTO
  138. imply CMD_DM
  139. imply CMD_EXCEPTION
  140. imply CMD_GETTIME
  141. imply CMD_HASH
  142. imply CMD_IO
  143. imply CMD_IOTRACE
  144. imply CMD_LZMADEC
  145. imply CMD_SATA
  146. imply CMD_SF
  147. imply CMD_SF_TEST
  148. imply CRC32_VERIFY
  149. imply FAT_WRITE
  150. imply FIRMWARE
  151. imply HASH_VERIFY
  152. imply LZMA
  153. imply SCSI
  154. imply TEE
  155. imply AVB_VERIFY
  156. imply LIBAVB
  157. imply CMD_AVB
  158. imply PARTITION_TYPE_GUID
  159. imply SCP03
  160. imply CMD_SCP03
  161. imply UDP_FUNCTION_FASTBOOT
  162. imply VIRTIO_MMIO
  163. imply VIRTIO_PCI
  164. imply VIRTIO_SANDBOX
  165. imply VIRTIO_BLK
  166. imply VIRTIO_NET
  167. imply DM_SOUND
  168. imply PCI_SANDBOX_EP
  169. imply PCH
  170. imply PHYLIB
  171. imply DM_MDIO
  172. imply DM_MDIO_MUX
  173. imply ACPI_PMC
  174. imply ACPI_PMC_SANDBOX
  175. imply CMD_PMC
  176. imply CMD_CLONE
  177. imply SILENT_CONSOLE
  178. imply BOOTARGS_SUBST
  179. imply PHY_FIXED
  180. imply DM_DSA
  181. imply CMD_EXTENSION
  182. imply KEYBOARD
  183. imply PHYSMEM
  184. config SH
  185. bool "SuperH architecture"
  186. select HAVE_PRIVATE_LIBGCC
  187. select SUPPORT_OF_CONTROL
  188. config X86
  189. bool "x86 architecture"
  190. select SUPPORT_SPL
  191. select SUPPORT_TPL
  192. select CREATE_ARCH_SYMLINK
  193. select DM
  194. select HAVE_ARCH_IOMAP
  195. select HAVE_PRIVATE_LIBGCC
  196. select OF_CONTROL
  197. select PCI
  198. select SUPPORT_OF_CONTROL
  199. select SYS_CACHE_SHIFT_6
  200. select TIMER
  201. select USE_PRIVATE_LIBGCC
  202. select X86_TSC_TIMER
  203. select IRQ
  204. imply HAS_ROM if X86_RESET_VECTOR
  205. imply BLK
  206. imply CMD_DM
  207. imply CMD_FPGA_LOADMK
  208. imply CMD_GETTIME
  209. imply CMD_IO
  210. imply CMD_IRQ
  211. imply CMD_PCI
  212. imply CMD_SF
  213. imply CMD_SF_TEST
  214. imply CMD_ZBOOT
  215. imply DM_ETH
  216. imply DM_GPIO
  217. imply DM_KEYBOARD
  218. imply DM_MMC
  219. imply DM_RTC
  220. imply DM_SCSI
  221. imply DM_SERIAL
  222. imply DM_SPI
  223. imply DM_SPI_FLASH
  224. imply DM_USB
  225. imply DM_VIDEO
  226. imply SYSRESET
  227. imply SPL_SYSRESET
  228. imply SYSRESET_X86
  229. imply USB_ETHER_ASIX
  230. imply USB_ETHER_SMSC95XX
  231. imply USB_HOST_ETHER
  232. imply PCH
  233. imply PHYSMEM
  234. imply RTC_MC146818
  235. imply ACPIGEN if !QEMU
  236. imply SYSINFO if GENERATE_SMBIOS_TABLE
  237. imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
  238. imply TIMESTAMP
  239. # Thing to enable for when SPL/TPL are enabled: SPL
  240. imply SPL_DM
  241. imply SPL_OF_LIBFDT
  242. imply SPL_DRIVERS_MISC
  243. imply SPL_GPIO
  244. imply SPL_PINCTRL
  245. imply SPL_LIBCOMMON_SUPPORT
  246. imply SPL_LIBGENERIC_SUPPORT
  247. imply SPL_SERIAL
  248. imply SPL_SPI_FLASH_SUPPORT
  249. imply SPL_SPI
  250. imply SPL_OF_CONTROL
  251. imply SPL_TIMER
  252. imply SPL_REGMAP
  253. imply SPL_SYSCON
  254. # TPL
  255. imply TPL_DM
  256. imply TPL_DRIVERS_MISC
  257. imply TPL_GPIO
  258. imply TPL_PINCTRL
  259. imply TPL_LIBCOMMON_SUPPORT
  260. imply TPL_LIBGENERIC_SUPPORT
  261. imply TPL_SERIAL
  262. imply TPL_OF_CONTROL
  263. imply TPL_TIMER
  264. imply TPL_REGMAP
  265. imply TPL_SYSCON
  266. config XTENSA
  267. bool "Xtensa architecture"
  268. select CREATE_ARCH_SYMLINK
  269. select SUPPORT_OF_CONTROL
  270. endchoice
  271. config SYS_ARCH
  272. string
  273. help
  274. This option should contain the architecture name to build the
  275. appropriate arch/<CONFIG_SYS_ARCH> directory.
  276. All the architectures should specify this option correctly.
  277. config SYS_CPU
  278. string
  279. help
  280. This option should contain the CPU name to build the correct
  281. arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
  282. This is optional. For those targets without the CPU directory,
  283. leave this option empty.
  284. config SYS_SOC
  285. string
  286. help
  287. This option should contain the SoC name to build the directory
  288. arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
  289. This is optional. For those targets without the SoC directory,
  290. leave this option empty.
  291. config SYS_VENDOR
  292. string
  293. help
  294. This option should contain the vendor name of the target board.
  295. If it is set and
  296. board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
  297. directory is compiled.
  298. If CONFIG_SYS_BOARD is also set, the sources under
  299. board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
  300. This is optional. For those targets without the vendor directory,
  301. leave this option empty.
  302. config SYS_BOARD
  303. string
  304. help
  305. This option should contain the name of the target board.
  306. If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
  307. or board/<CONFIG_SYS_BOARD> directory is compiled depending on
  308. whether CONFIG_SYS_VENDOR is set or not.
  309. This is optional. For those targets without the board directory,
  310. leave this option empty.
  311. config SYS_CONFIG_NAME
  312. string
  313. help
  314. This option should contain the base name of board header file.
  315. The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
  316. should be included from include/config.h.
  317. config SYS_DISABLE_DCACHE_OPS
  318. bool
  319. help
  320. This option disables dcache flush and dcache invalidation
  321. operations. For example, on coherent systems where cache
  322. operatios are not required, enable this option to avoid them.
  323. Note that, its up to the individual architectures to implement
  324. this functionality.
  325. config SYS_IMMR
  326. hex
  327. depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
  328. default 0xFF000000 if MPC8xx
  329. default 0xF0000000 if ARCH_MPC8313
  330. default 0xE0000000 if MPC83xx && !ARCH_MPC8313
  331. default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
  332. default SYS_CCSRBAR_DEFAULT
  333. help
  334. Address for the Internal Memory-Mapped Registers (IMMR) window used
  335. to configure the features of many Freescale / NXP SoCs.
  336. config SKIP_LOWLEVEL_INIT
  337. bool "Skip the calls to certain low level initialization functions"
  338. depends on ARM || NDS32 || MIPS || RISCV
  339. help
  340. If enabled, then certain low level initializations (like setting up
  341. the memory controller) are omitted and/or U-Boot does not relocate
  342. itself into RAM.
  343. Normally this variable MUST NOT be defined. The only exception is
  344. when U-Boot is loaded (to RAM) by some other boot loader or by a
  345. debugger which performs these initializations itself.
  346. config SPL_SKIP_LOWLEVEL_INIT
  347. bool "Skip the calls to certain low level initialization functions"
  348. depends on SPL && (ARM || NDS32 || MIPS || RISCV)
  349. help
  350. If enabled, then certain low level initializations (like setting up
  351. the memory controller) are omitted and/or U-Boot does not relocate
  352. itself into RAM.
  353. Normally this variable MUST NOT be defined. The only exception is
  354. when U-Boot is loaded (to RAM) by some other boot loader or by a
  355. debugger which performs these initializations itself.
  356. config TPL_SKIP_LOWLEVEL_INIT
  357. bool "Skip the calls to certain low level initialization functions"
  358. depends on SPL && ARM
  359. help
  360. If enabled, then certain low level initializations (like setting up
  361. the memory controller) are omitted and/or U-Boot does not relocate
  362. itself into RAM.
  363. Normally this variable MUST NOT be defined. The only exception is
  364. when U-Boot is loaded (to RAM) by some other boot loader or by a
  365. debugger which performs these initializations itself.
  366. config SKIP_LOWLEVEL_INIT_ONLY
  367. bool "Skip the call to lowlevel_init during early boot ONLY"
  368. depends on ARM
  369. help
  370. This allows just the call to lowlevel_init() to be skipped. The
  371. normal CP15 init (such as enabling the instruction cache) is still
  372. performed.
  373. config SPL_SKIP_LOWLEVEL_INIT_ONLY
  374. bool "Skip the call to lowlevel_init during early boot ONLY"
  375. depends on SPL && ARM
  376. help
  377. This allows just the call to lowlevel_init() to be skipped. The
  378. normal CP15 init (such as enabling the instruction cache) is still
  379. performed.
  380. config TPL_SKIP_LOWLEVEL_INIT_ONLY
  381. bool "Skip the call to lowlevel_init during early boot ONLY"
  382. depends on TPL && ARM
  383. help
  384. This allows just the call to lowlevel_init() to be skipped. The
  385. normal CP15 init (such as enabling the instruction cache) is still
  386. performed.
  387. source "arch/arc/Kconfig"
  388. source "arch/arm/Kconfig"
  389. source "arch/m68k/Kconfig"
  390. source "arch/microblaze/Kconfig"
  391. source "arch/mips/Kconfig"
  392. source "arch/nds32/Kconfig"
  393. source "arch/nios2/Kconfig"
  394. source "arch/powerpc/Kconfig"
  395. source "arch/sandbox/Kconfig"
  396. source "arch/sh/Kconfig"
  397. source "arch/x86/Kconfig"
  398. source "arch/xtensa/Kconfig"
  399. source "arch/riscv/Kconfig"