socfpga_soc64_common.h 5.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
  7. #define __CONFIG_SOCFPGA_SOC64_COMMON_H__
  8. #include <asm/arch/base_addr_soc64.h>
  9. #include <asm/arch/handoff_soc64.h>
  10. #include <linux/stringify.h>
  11. /*
  12. * U-Boot general configurations
  13. */
  14. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  15. #define CONFIG_LOADADDR 0x2000000
  16. #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  17. #define CONFIG_REMAKE_ELF
  18. /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
  19. #define CPU_RELEASE_ADDR 0xFFD12210
  20. /*
  21. * U-Boot console configurations
  22. */
  23. #define CONFIG_SYS_MAXARGS 64
  24. #define CONFIG_SYS_CBSIZE 2048
  25. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  26. sizeof(CONFIG_SYS_PROMPT) + 16)
  27. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  28. /* Extend size of kernel image for uncompression */
  29. #define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024)
  30. /*
  31. * U-Boot run time memory configurations
  32. */
  33. #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
  34. #define CONFIG_SYS_INIT_RAM_SIZE 0x40000
  35. #ifdef CONFIG_SPL_BUILD
  36. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \
  37. + CONFIG_SYS_INIT_RAM_SIZE \
  38. - SOC64_HANDOFF_SIZE)
  39. #else
  40. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE \
  41. + 0x100000)
  42. #endif
  43. #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR)
  44. #define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024)
  45. /*
  46. * U-Boot environment configurations
  47. */
  48. /*
  49. * QSPI support
  50. */
  51. #ifdef CONFIG_CADENCE_QSPI
  52. /* Enable it if you want to use dual-stacked mode */
  53. /*#define CONFIG_QSPI_RBF_ADDR 0x720000*/
  54. /* Flash device info */
  55. /*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
  56. #ifndef CONFIG_SPL_BUILD
  57. #define CONFIG_MTD_PARTITIONS
  58. #define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
  59. #endif /* CONFIG_SPL_BUILD */
  60. #ifndef __ASSEMBLY__
  61. unsigned int cm_get_qspi_controller_clk_hz(void);
  62. #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
  63. #endif
  64. #endif /* CONFIG_CADENCE_QSPI */
  65. /*
  66. * Environment variable
  67. */
  68. #ifdef CONFIG_FIT
  69. #define CONFIG_BOOTFILE "kernel.itb"
  70. #else
  71. #define CONFIG_BOOTFILE "Image"
  72. #endif
  73. #define CONFIG_EXTRA_ENV_SETTINGS \
  74. "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  75. "bootfile=" CONFIG_BOOTFILE "\0" \
  76. "fdt_addr=8000000\0" \
  77. "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
  78. "mmcroot=/dev/mmcblk0p2\0" \
  79. "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  80. " root=${mmcroot} rw rootwait;" \
  81. "booti ${loadaddr} - ${fdt_addr}\0" \
  82. "mmcload=mmc rescan;" \
  83. "load mmc 0:1 ${loadaddr} ${bootfile};" \
  84. "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
  85. "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
  86. " root=${mmcroot} rw rootwait;" \
  87. "bootm ${loadaddr}\0" \
  88. "mmcfitload=mmc rescan;" \
  89. "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
  90. "linux_qspi_enable=if sf probe; then " \
  91. "echo Enabling QSPI at Linux DTB...;" \
  92. "fdt addr ${fdt_addr}; fdt resize;" \
  93. "fdt set /soc/spi@ff8d2000 status okay;" \
  94. "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
  95. " ${qspi_clock}; fi; \0" \
  96. "scriptaddr=0x02100000\0" \
  97. "scriptfile=u-boot.scr\0" \
  98. "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
  99. "then source ${scriptaddr}; fi\0" \
  100. "socfpga_legacy_reset_compat=1\0"
  101. /*
  102. * Generic Interrupt Controller Definitions
  103. */
  104. #define CONFIG_GICV2
  105. /*
  106. * External memory configurations
  107. */
  108. #define PHYS_SDRAM_1 0x0
  109. #define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024)
  110. #define CONFIG_SYS_SDRAM_BASE 0
  111. /*
  112. * Serial / UART configurations
  113. */
  114. #define CONFIG_SYS_NS16550_CLK 100000000
  115. #define CONFIG_SYS_NS16550_MEM32
  116. /*
  117. * Timer & watchdog configurations
  118. */
  119. #define COUNTER_FREQUENCY 400000000
  120. /*
  121. * SDMMC configurations
  122. */
  123. #ifdef CONFIG_CMD_MMC
  124. #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
  125. #endif
  126. /*
  127. * Flash configurations
  128. */
  129. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  130. /* Ethernet on SoC (EMAC) */
  131. #if defined(CONFIG_CMD_NET)
  132. #define CONFIG_DW_ALTDESCRIPTOR
  133. #endif /* CONFIG_CMD_NET */
  134. /*
  135. * L4 Watchdog
  136. */
  137. #ifndef CONFIG_SPL_BUILD
  138. #undef CONFIG_HW_WATCHDOG
  139. #undef CONFIG_DESIGNWARE_WATCHDOG
  140. #endif
  141. #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
  142. #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
  143. #ifndef __ASSEMBLY__
  144. unsigned int cm_get_l4_sys_free_clk_hz(void);
  145. #define CONFIG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000)
  146. #endif
  147. #else
  148. #define CONFIG_DW_WDT_CLOCK_KHZ 100000
  149. #endif
  150. /*
  151. * SPL memory layout
  152. *
  153. * On chip RAM
  154. * 0xFFE0_0000 ...... Start of OCRAM
  155. * SPL code, rwdata
  156. * empty space
  157. * 0xFFEx_xxxx ...... Top of stack (grows down)
  158. * 0xFFEy_yyyy ...... Global Data
  159. * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
  160. * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
  161. * 0xFFE3_FFFF ...... End of OCRAM
  162. *
  163. * SDRAM
  164. * 0x0000_0000 ...... Start of SDRAM_1
  165. * unused / empty space for image loading
  166. * Size 64MB ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
  167. * Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
  168. * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
  169. *
  170. */
  171. #define CONFIG_SPL_TARGET "spl/u-boot-spl-dtb.hex"
  172. #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
  173. #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
  174. #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
  175. #define CONFIG_SPL_BSS_START_ADDR (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
  176. - CONFIG_SPL_BSS_MAX_SIZE)
  177. #define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN)
  178. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \
  179. - CONFIG_SYS_SPL_MALLOC_SIZE)
  180. /* SPL SDMMC boot support */
  181. #ifdef CONFIG_SPL_LOAD_FIT
  182. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb"
  183. #else
  184. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  185. #endif
  186. #endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */