pg-wcom-expu1.h 1.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2020 Hitachi ABB Power Grids
  4. */
  5. #ifndef __CONFIG_PG_WCOM_EXPU1_H
  6. #define __CONFIG_PG_WCOM_EXPU1_H
  7. #define WCOM_EXPU1
  8. #define CONFIG_HOSTNAME "EXPU1"
  9. #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
  10. #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
  11. /* CLIPS FPGA Definitions */
  12. #define CONFIG_SYS_CSPR3_EXT (0x00)
  13. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CLIPS_BASE) | \
  14. CSPR_PORT_SIZE_8 | \
  15. CSPR_MSEL_GPCM | \
  16. CSPR_V)
  17. #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
  18. #define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \
  19. CSOR_GPCM_TRHZ_40)
  20. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
  21. FTIM0_GPCM_TEADC(0x7) | \
  22. FTIM0_GPCM_TEAHC(0x2))
  23. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
  24. FTIM1_GPCM_TRAD(0x12))
  25. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
  26. FTIM2_GPCM_TCH(0x1) | \
  27. FTIM2_GPCM_TWP(0x12))
  28. #define CONFIG_SYS_CS3_FTIM3 0x04000000
  29. /* PRST */
  30. #define WCOM_CLIPS_RST 0
  31. #define WCOM_QSFP_RST 1
  32. #define WCOM_PHY_RST 2
  33. #define WCOM_TMG_RST 3
  34. #define KM_DBG_ETH_RST 15
  35. /* QRIO GPIOs used for deblocking */
  36. #define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A
  37. #define KM_I2C_DEBLOCK_SCL 20
  38. #define KM_I2C_DEBLOCK_SDA 21
  39. /* ZL30343 on SPI */
  40. #define WCOM_ZL30343_CFG_ADDR 0xe8070000
  41. #define WCOM_ZL30343_SPI_BUS 0
  42. #define WCOM_ZL30343_CS 0
  43. #include "km/pg-wcom-ls102xa.h"
  44. #endif /* __CONFIG_PG_WCOM_EXPU1_H */