kmcent2.h 18 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2016 Keymile AG
  4. * Rainer Boschung <rainer.boschung@keymile.com>
  5. *
  6. */
  7. #ifndef __KMCENT2_H
  8. #define __KMCENT2_H
  9. #define CONFIG_HOSTNAME "kmcent2"
  10. #define KM_BOARD_NAME CONFIG_HOSTNAME
  11. /*
  12. * The Linux fsl_fman driver needs to be able to process frames with more
  13. * than just the VLAN tag (i.e. eDSA tag). It is passed as a kernel boot
  14. * parameters
  15. */
  16. #define CONFIG_KM_DEF_BOOT_ARGS_CPU "fsl_dpaa_fman.fsl_fm_max_frm=1558"
  17. #include "km/keymile-common.h"
  18. /* Application IFC chip selects */
  19. #define SYS_LAWAPP_BASE 0xc0000000
  20. #define SYS_LAWAPP_BASE_PHYS (0xf00000000ull | SYS_LAWAPP_BASE)
  21. /* Application IFC CS4 MRAM */
  22. #define CONFIG_SYS_MRAM_BASE SYS_LAWAPP_BASE
  23. #define SYS_MRAM_BASE_PHYS SYS_LAWAPP_BASE_PHYS
  24. #define SYS_MRAM_CSPR_EXT (0x0f)
  25. #define SYS_MRAM_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_MRAM_BASE) | \
  26. CSPR_PORT_SIZE_8 | /* 8 bit */ \
  27. CSPR_MSEL_GPCM | /* msel = gpcm */ \
  28. CSPR_V /* bank is valid */)
  29. #define SYS_MRAM_AMASK IFC_AMASK(2 * 1024 * 1024) /* 2 MiB */
  30. #define SYS_MRAM_CSOR CSOR_GPCM_TRHZ_40
  31. /* MRAM Timing parameters for IFC CS4 */
  32. #define SYS_MRAM_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
  33. FTIM0_GPCM_TEADC(0x8) | \
  34. FTIM0_GPCM_TEAHC(0x2))
  35. #define SYS_MRAM_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
  36. FTIM1_GPCM_TRAD(0xe))
  37. #define SYS_MRAM_FTIM2 (FTIM2_GPCM_TCS(0x2) | \
  38. FTIM2_GPCM_TCH(0x2) | \
  39. FTIM2_GPCM_TWP(0x8))
  40. #define SYS_MRAM_FTIM3 0x04000000
  41. #define CONFIG_SYS_CSPR4_EXT SYS_MRAM_CSPR_EXT
  42. #define CONFIG_SYS_CSPR4 SYS_MRAM_CSPR
  43. #define CONFIG_SYS_AMASK4 SYS_MRAM_AMASK
  44. #define CONFIG_SYS_CSOR4 SYS_MRAM_CSOR
  45. #define CONFIG_SYS_CS4_FTIM0 SYS_MRAM_FTIM0
  46. #define CONFIG_SYS_CS4_FTIM1 SYS_MRAM_FTIM1
  47. #define CONFIG_SYS_CS4_FTIM2 SYS_MRAM_FTIM2
  48. #define CONFIG_SYS_CS4_FTIM3 SYS_MRAM_FTIM3
  49. /* Application IFC CS6: BFTIC */
  50. #define SYS_BFTIC_BASE 0xd0000000
  51. #define SYS_BFTIC_BASE_PHYS (0xf00000000ull | SYS_BFTIC_BASE)
  52. #define SYS_BFTIC_CSPR_EXT (0x0f)
  53. #define SYS_BFTIC_CSPR (CSPR_PHYS_ADDR(SYS_BFTIC_BASE) | \
  54. CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
  55. CSPR_MSEL_GPCM | /* MSEL = GPCM */\
  56. CSPR_V) /* valid */
  57. #define SYS_BFTIC_AMASK IFC_AMASK(64 * 1024) /* 64kB */
  58. #define SYS_BFTIC_CSOR CSOR_GPCM_TRHZ_40
  59. /* BFTIC Timing parameters for IFC CS6 */
  60. #define SYS_BFTIC_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
  61. FTIM0_GPCM_TEADC(0x8) | \
  62. FTIM0_GPCM_TEAHC(0x2))
  63. #define SYS_BFTIC_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
  64. FTIM1_GPCM_TRAD(0x12))
  65. #define SYS_BFTIC_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
  66. FTIM2_GPCM_TCH(0x1) | \
  67. FTIM2_GPCM_TWP(0x12))
  68. #define SYS_BFTIC_FTIM3 0x04000000
  69. #define CONFIG_SYS_CSPR6_EXT SYS_BFTIC_CSPR_EXT
  70. #define CONFIG_SYS_CSPR6 SYS_BFTIC_CSPR
  71. #define CONFIG_SYS_AMASK6 SYS_BFTIC_AMASK
  72. #define CONFIG_SYS_CSOR6 SYS_BFTIC_CSOR
  73. #define CONFIG_SYS_CS6_FTIM0 SYS_BFTIC_FTIM0
  74. #define CONFIG_SYS_CS6_FTIM1 SYS_BFTIC_FTIM1
  75. #define CONFIG_SYS_CS6_FTIM2 SYS_BFTIC_FTIM2
  76. #define CONFIG_SYS_CS6_FTIM3 SYS_BFTIC_FTIM3
  77. /* Application IFC CS7 PAXE */
  78. #define CONFIG_SYS_PAXE_BASE 0xd8000000
  79. #define SYS_PAXE_BASE_PHYS (0xf00000000ull | CONFIG_SYS_PAXE_BASE)
  80. #define SYS_PAXE_CSPR_EXT (0x0f)
  81. #define SYS_PAXE_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_PAXE_BASE) | \
  82. CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
  83. CSPR_MSEL_GPCM | /* MSEL = GPCM */\
  84. CSPR_V) /* valid */
  85. #define SYS_PAXE_AMASK IFC_AMASK(64 * 1024) /* 64kB */
  86. #define SYS_PAXE_CSOR CSOR_GPCM_TRHZ_40
  87. /* PAXE Timing parameters for IFC CS7 */
  88. #define SYS_PAXE_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
  89. FTIM0_GPCM_TEADC(0x8) | \
  90. FTIM0_GPCM_TEAHC(0x2))
  91. #define SYS_PAXE_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
  92. FTIM1_GPCM_TRAD(0x12))
  93. #define SYS_PAXE_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
  94. FTIM2_GPCM_TCH(0x1) | \
  95. FTIM2_GPCM_TWP(0x12))
  96. #define SYS_PAXE_FTIM3 0x04000000
  97. #define CONFIG_SYS_CSPR7_EXT SYS_PAXE_CSPR_EXT
  98. #define CONFIG_SYS_CSPR7 SYS_PAXE_CSPR
  99. #define CONFIG_SYS_AMASK7 SYS_PAXE_AMASK
  100. #define CONFIG_SYS_CSOR7 SYS_PAXE_CSOR
  101. #define CONFIG_SYS_CS7_FTIM0 SYS_PAXE_FTIM0
  102. #define CONFIG_SYS_CS7_FTIM1 SYS_PAXE_FTIM1
  103. #define CONFIG_SYS_CS7_FTIM2 SYS_PAXE_FTIM2
  104. #define CONFIG_SYS_CS7_FTIM3 SYS_PAXE_FTIM3
  105. /* PRST */
  106. #define KM_BFTIC4_RST 0
  107. #define KM_DPAXE_RST 1
  108. #define KM_FEMT_RST 3
  109. #define KM_FOAM_RST 4
  110. #define KM_EFE_RST 5
  111. #define KM_ES_PHY_RST 6
  112. #define KM_XES_PHY_RST 7
  113. #define KM_ZL30158_RST 8
  114. #define KM_ZL30364_RST 9
  115. #define KM_BOBCAT_RST 10
  116. #define KM_ETHSW_DDR_RST 12
  117. #define KM_CFE_RST 13
  118. #define KM_PEXSW_RST 14
  119. #define KM_PEXSW_NT_RST 15
  120. /* QRIO GPIOs used for deblocking */
  121. #define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A
  122. #define KM_I2C_DEBLOCK_SCL 20
  123. #define KM_I2C_DEBLOCK_SDA 21
  124. /* High Level Configuration Options */
  125. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  126. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  127. #define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc
  128. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  129. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  130. #define CONFIG_PCIE1 /* PCIE controller 1 */
  131. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  132. /* Environment in parallel NOR-Flash */
  133. #define CONFIG_ENV_TOTAL_SIZE 0x040000
  134. #define ENV_DEL_ADDR 0xebf00000 /*direct for newenv*/
  135. #define CONFIG_SYS_CLK_FREQ 66666666
  136. /*
  137. * These can be toggled for performance analysis, otherwise use default.
  138. */
  139. #define CONFIG_SYS_CACHE_STASHING
  140. #define CONFIG_BACKSIDE_L2_CACHE
  141. #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  142. #define CONFIG_BTB /* toggle branch predition */
  143. #define CONFIG_ENABLE_36BIT_PHYS
  144. /* POST memory regions test */
  145. #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS
  146. /*
  147. * Config the L3 Cache as L3 SRAM
  148. */
  149. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  150. #define CONFIG_SYS_L3_SIZE 256 << 10
  151. #define CONFIG_SYS_DCSRBAR 0xf0000000
  152. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  153. /*
  154. * DDR Setup
  155. */
  156. #define CONFIG_VERY_BIG_RAM
  157. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  158. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  159. #define CONFIG_DDR_CLK_FREQ 66666666
  160. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  161. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  162. #define CONFIG_DDR_SPD
  163. #define CONFIG_SYS_SPD_BUS_NUM 0
  164. #define SPD_EEPROM_ADDRESS 0x54
  165. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  166. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  167. #define CONFIG_SYS_I2C_EEPROM_ADDR CONFIG_SYS_IVM_EEPROM_ADR
  168. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  169. /******************************************************************************
  170. * (PRAM usage)
  171. * ... -------------------------------------------------------
  172. * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
  173. * ... |<------------------- pram -------------------------->|
  174. * ... -------------------------------------------------------
  175. * @END_OF_RAM:
  176. * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
  177. * @CONFIG_KM_PHRAM: address for /var
  178. * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
  179. * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
  180. */
  181. /* size of rootfs in RAM */
  182. #define CONFIG_KM_ROOTFSSIZE 0x0
  183. /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
  184. * is not valid yet, which is the case for when u-boot copies itself to RAM
  185. */
  186. #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10)
  187. /*
  188. * IFC Definitions
  189. */
  190. /* NOR flash on IFC CS0 */
  191. #define CONFIG_SYS_FLASH_BASE 0xe8000000
  192. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \
  193. CONFIG_SYS_FLASH_BASE)
  194. #define CONFIG_SYS_NOR_CSPR_EXT (0x0f)
  195. #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
  196. CSPR_PORT_SIZE_16 | /* Port size = 16 bit */\
  197. 0x00000010 | /* drive TE high */\
  198. CSPR_MSEL_NOR | /* MSEL = NOR */\
  199. CSPR_V) /* valid */
  200. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) /* 64MB */
  201. #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | /* AVD toggle */\
  202. CSOR_NOR_TRHZ_20 | \
  203. CSOR_NOR_BCTLD)
  204. /* NOR Flash Timing Params */
  205. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
  206. FTIM0_NOR_TEADC(0x7) | \
  207. FTIM0_NOR_TEAHC(0x1))
  208. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
  209. FTIM1_NOR_TRAD_NOR(0x21) | \
  210. FTIM1_NOR_TSEQRAD_NOR(0x21))
  211. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCH(0x1) | \
  212. FTIM2_NOR_TCS(0x1) | \
  213. FTIM2_NOR_TWP(0xb) | \
  214. FTIM2_NOR_TWPH(0x6))
  215. #define CONFIG_SYS_NOR_FTIM3 0x0
  216. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
  217. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
  218. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  219. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  220. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  221. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  222. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  223. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  224. /* More NOR Flash params */
  225. #define CONFIG_SYS_FLASH_QUIET_TEST
  226. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  227. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
  228. #define CONFIG_SYS_FLASH_EMPTY_INFO
  229. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  230. /* NAND Flash on IFC CS1*/
  231. #define CONFIG_NAND_FSL_IFC
  232. #define CONFIG_SYS_NAND_BASE 0xfa000000
  233. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  234. #define CONFIG_SYS_NAND_CSPR_EXT (0x0f)
  235. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
  236. CSPR_PORT_SIZE_8 | /* Port Size = 8 bit */\
  237. 0x00000010 | /* drive TE high */\
  238. CSPR_MSEL_NAND | /* MSEL = NAND */\
  239. CSPR_V) /* valid */
  240. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) /* 64kB */
  241. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \
  242. CSOR_NAND_ECC_DEC_EN | /* ECC decoder on */ \
  243. CSOR_NAND_ECC_MODE_4 | /* 4-bit ECC */ \
  244. CSOR_NAND_RAL_3 | /* RAL = 3Bytes */ \
  245. CSOR_NAND_PGS_2K | /* Page size = 2K */ \
  246. CSOR_NAND_SPRZ_128 | /* Spare size = 128 */ \
  247. CSOR_NAND_PB(64) | /* 64 Pages/Block */ \
  248. CSOR_NAND_TRHZ_40 | /**/ \
  249. CSOR_NAND_BCTLD) /**/
  250. #define CONFIG_SYS_NAND_ONFI_DETECTION
  251. /* ONFI NAND Flash mode0 Timing Params */
  252. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
  253. FTIM0_NAND_TWP(0x8) | \
  254. FTIM0_NAND_TWCHT(0x3) | \
  255. FTIM0_NAND_TWH(0x5))
  256. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
  257. FTIM1_NAND_TWBE(0x1e) | \
  258. FTIM1_NAND_TRR(0x6) | \
  259. FTIM1_NAND_TRP(0x8))
  260. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
  261. FTIM2_NAND_TREH(0x5) | \
  262. FTIM2_NAND_TWHRE(0x3c))
  263. #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
  264. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  265. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  266. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  267. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  268. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  269. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  270. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  271. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  272. /* More NAND Flash Params */
  273. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  274. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  275. /* QRIO on IFC CS2 */
  276. #define CONFIG_SYS_QRIO_BASE 0xfb000000
  277. #define CONFIG_SYS_QRIO_BASE_PHYS (0xf00000000ull | CONFIG_SYS_QRIO_BASE)
  278. #define SYS_QRIO_CSPR_EXT (0x0f)
  279. #define SYS_QRIO_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
  280. CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
  281. 0x00000010 | /* drive TE high */\
  282. CSPR_MSEL_GPCM | /* MSEL = GPCM */\
  283. CSPR_V) /* valid */
  284. #define SYS_QRIO_AMASK IFC_AMASK(64 * 1024) /* 64kB */
  285. #define SYS_QRIO_CSOR (CSOR_GPCM_TRHZ_20 |\
  286. CSOR_GPCM_BCTLD)
  287. /* QRIO Timing parameters for IFC CS2 */
  288. #define SYS_QRIO_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \
  289. FTIM0_GPCM_TEADC(0x8) | \
  290. FTIM0_GPCM_TEAHC(0x2))
  291. #define SYS_QRIO_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
  292. FTIM1_GPCM_TRAD(0x6))
  293. #define SYS_QRIO_FTIM2 (FTIM2_GPCM_TCS(0x1) | \
  294. FTIM2_GPCM_TCH(0x1) | \
  295. FTIM2_GPCM_TWP(0x7))
  296. #define SYS_QRIO_FTIM3 0x04000000
  297. #define CONFIG_SYS_CSPR2_EXT SYS_QRIO_CSPR_EXT
  298. #define CONFIG_SYS_CSPR2 SYS_QRIO_CSPR
  299. #define CONFIG_SYS_AMASK2 SYS_QRIO_AMASK
  300. #define CONFIG_SYS_CSOR2 SYS_QRIO_CSOR
  301. #define CONFIG_SYS_CS2_FTIM0 SYS_QRIO_FTIM0
  302. #define CONFIG_SYS_CS2_FTIM1 SYS_QRIO_FTIM1
  303. #define CONFIG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2
  304. #define CONFIG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3
  305. #define CONFIG_MISC_INIT_F
  306. #define CONFIG_HWCONFIG
  307. /* define to use L1 as initial stack */
  308. #define CONFIG_SYS_INIT_RAM_LOCK
  309. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  310. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  311. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  312. /* The assembler doesn't like typecast */
  313. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  314. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  315. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  316. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  317. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  318. GENERATED_GBL_DATA_SIZE)
  319. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  320. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  321. #define CONFIG_SYS_MONITOR_LEN 0xc0000 /* 768k */
  322. #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  323. /*
  324. * Serial Port - controlled on board with jumper J8
  325. * open - index 2
  326. * shorted - index 1
  327. * Retain non-DM serial port for debug purposes.
  328. */
  329. #if !defined(CONFIG_DM_SERIAL)
  330. #define CONFIG_CONS_INDEX 1
  331. #define CONFIG_SYS_NS16550_SERIAL
  332. #define CONFIG_SYS_NS16550_REG_SIZE 1
  333. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
  334. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500)
  335. #endif
  336. #ifndef __ASSEMBLY__
  337. void set_sda(int state);
  338. void set_scl(int state);
  339. int get_sda(void);
  340. int get_scl(void);
  341. #endif
  342. /*
  343. * General PCI
  344. * Memory space is mapped 1-1, but I/O space must start from 0.
  345. */
  346. /* controller 1 */
  347. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  348. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  349. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  350. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  351. #define CONFIG_SYS_BMAN_NUM_PORTALS 10
  352. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  353. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  354. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  355. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  356. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  357. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  358. CONFIG_SYS_BMAN_CENA_SIZE)
  359. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  360. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  361. #define CONFIG_SYS_QMAN_NUM_PORTALS 10
  362. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  363. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  364. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  365. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  366. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  367. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  368. CONFIG_SYS_QMAN_CENA_SIZE)
  369. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  370. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  371. #define CONFIG_SYS_DPAA_FMAN
  372. #define CONFIG_SYS_DPAA_PME
  373. /* Default address of microcode for the Linux Fman driver */
  374. #define CONFIG_SYS_FMAN_FW_ADDR 0xE8020000
  375. #define CONFIG_SYS_QE_FW_ADDR 0xE8040000
  376. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  377. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  378. /* Qman / Bman */
  379. /* RGMII (FM1@DTESC5) is local managemant interface */
  380. #define CONFIG_SYS_RGMII2_PHY_ADDR 0x11
  381. #define CONFIG_ETHPRIME "fm1-mac5"
  382. /*
  383. * Hardware Watchdog
  384. */
  385. #define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) ~10min */
  386. #define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */
  387. /*
  388. * For booting Linux, the board info and command line data
  389. * have to be in the first 64 MB of memory, since this is
  390. * the maximum mapped by the Linux kernel during initialization.
  391. */
  392. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  393. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  394. /*
  395. * Environment Configuration
  396. */
  397. #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
  398. #define CONFIG_KM_DEF_ENV
  399. #endif
  400. #define __USB_PHY_TYPE utmi
  401. #define CONFIG_KM_DEF_ENV_CPU \
  402. "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
  403. "cramfsloadfdt=" \
  404. "cramfsload ${fdt_addr_r} " \
  405. "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
  406. "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
  407. "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
  408. " +${filesize} && " \
  409. "erase " __stringify(CONFIG_SYS_MONITOR_BASE) \
  410. " +${filesize} && " \
  411. "cp.b ${load_addr_r} " \
  412. __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
  413. "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
  414. " +${filesize}\0" \
  415. "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
  416. " +${filesize} && " \
  417. "erase " __stringify(CONFIG_SYS_FLASH_BASE) \
  418. " +${filesize} && " \
  419. "cp.b ${load_addr_r} " \
  420. __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \
  421. "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
  422. " +" __stringify(CONFIG_SYS_MONITOR_LEN) "\0" \
  423. "set_fdthigh=true\0" \
  424. "checkfdt=true\0" \
  425. "fpgacfg=true\0" \
  426. ""
  427. #define CONFIG_HW_ENV_SETTINGS \
  428. "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \
  429. "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
  430. "usb_dr_mode=host\0"
  431. #define CONFIG_KM_NEW_ENV \
  432. "newenv=protect off " __stringify(ENV_DEL_ADDR) \
  433. " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
  434. "erase " __stringify(ENV_DEL_ADDR) \
  435. " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
  436. "protect on " __stringify(ENV_DEL_ADDR) \
  437. " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"
  438. /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
  439. #ifndef CONFIG_KM_DEF_ARCH
  440. #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
  441. #endif
  442. #define CONFIG_EXTRA_ENV_SETTINGS \
  443. CONFIG_KM_DEF_ENV \
  444. CONFIG_KM_DEF_ARCH \
  445. CONFIG_KM_NEW_ENV \
  446. CONFIG_HW_ENV_SETTINGS \
  447. "EEprom_ivm=pca9547:70:9\0" \
  448. ""
  449. #endif /* __KMCENT2_H */