imx8mm_icore_mx8mm.h 2.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (c) 2020 Engicam srl
  4. * Copyright (c) 2020 Amarula Solutions(India)
  5. */
  6. #ifndef __IMX8MM_ICORE_MX8MM_H
  7. #define __IMX8MM_ICORE_MX8MM_H
  8. #include <linux/sizes.h>
  9. #include <asm/arch/imx-regs.h>
  10. #define CONFIG_SPL_MAX_SIZE (148 * 1024)
  11. #define CONFIG_SYS_MONITOR_LEN SZ_512K
  12. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
  13. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
  14. #define CONFIG_SYS_UBOOT_BASE \
  15. (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
  16. #ifdef CONFIG_SPL_BUILD
  17. # define CONFIG_SPL_STACK 0x920000
  18. # define CONFIG_SPL_BSS_START_ADDR 0x910000
  19. # define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
  20. # define CONFIG_SYS_SPL_MALLOC_START 0x42200000
  21. # define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
  22. /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
  23. # define CONFIG_MALLOC_F_ADDR 0x930000
  24. /* For RAW image gives a error info not panic */
  25. # define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  26. #endif /* CONFIG_SPL_BUILD */
  27. #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
  28. #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
  29. #ifndef CONFIG_SPL_BUILD
  30. #define BOOT_TARGET_DEVICES(func) \
  31. func(MMC, mmc, 2) \
  32. func(MMC, mmc, 0)
  33. #include <config_distro_bootcmd.h>
  34. #undef CONFIG_ISO_PARTITION
  35. #else
  36. #define BOOTENV
  37. #endif
  38. #define ENV_MEM_LAYOUT_SETTINGS \
  39. "fdt_addr_r=0x44000000\0" \
  40. "kernel_addr_r=0x42000000\0" \
  41. "ramdisk_addr_r=0x46400000\0" \
  42. "scriptaddr=0x46000000\0"
  43. #define CONFIG_EXTRA_ENV_SETTINGS \
  44. ENV_MEM_LAYOUT_SETTINGS \
  45. "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
  46. "console=ttymxc1,115200\0" \
  47. BOOTENV
  48. /* Link Definitions */
  49. #define CONFIG_LOADADDR 0x40480000
  50. #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  51. #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
  52. #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
  53. #define CONFIG_SYS_INIT_SP_OFFSET \
  54. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  55. #define CONFIG_SYS_INIT_SP_ADDR \
  56. (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  57. /* Size of malloc() pool */
  58. #define CONFIG_SYS_MALLOC_LEN SZ_32M
  59. #define CONFIG_SYS_SDRAM_BASE 0x40000000
  60. /* SDRAM configuration */
  61. #define PHYS_SDRAM 0x40000000
  62. #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
  63. #define CONFIG_SYS_BOOTM_LEN SZ_256M
  64. #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
  65. #define CONFIG_SYS_MEMTEST_END \
  66. (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
  67. /* UART */
  68. #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
  69. /* Monitor Command Prompt */
  70. #define CONFIG_SYS_CBSIZE 2048
  71. #define CONFIG_SYS_MAXARGS 64
  72. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  73. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  74. sizeof(CONFIG_SYS_PROMPT) + 16)
  75. /* USDHC */
  76. #define CONFIG_SYS_FSL_USDHC_NUM 2
  77. #define CONFIG_SYS_FSL_ESDHC_ADDR 0
  78. #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
  79. /* I2C */
  80. #define CONFIG_SYS_I2C_SPEED 100000
  81. #endif /* __IMX8MM_ICORE_MX8MM_H */