socfpga_cyclone5_vining_fpga-u-boot.dtsi 761 B

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR X11)
  2. /*
  3. * U-Boot additions
  4. *
  5. * Copyright (C) 2015 Marek Vasut <marex@denx.de>
  6. * Copyright (c) 2018 Simon Goldschmidt
  7. */
  8. #include "socfpga-common-u-boot.dtsi"
  9. /{
  10. aliases {
  11. spi0 = "/soc/spi@ff705000";
  12. udc0 = &usb1;
  13. };
  14. };
  15. &mmc {
  16. status = "disabled";
  17. };
  18. &qspi {
  19. u-boot,dm-pre-reloc;
  20. n25q128@0 {
  21. compatible = "n25q128", "jedec,spi-nor";
  22. u-boot,dm-pre-reloc;
  23. };
  24. n25q00@1 {
  25. compatible = "n25q00", "jedec,spi-nor";
  26. u-boot,dm-pre-reloc;
  27. };
  28. };
  29. &uart0 {
  30. clock-frequency = <100000000>;
  31. u-boot,dm-pre-reloc;
  32. };
  33. &uart1 {
  34. clock-frequency = <100000000>;
  35. };
  36. &porta {
  37. bank-name = "porta";
  38. };
  39. &portb {
  40. bank-name = "portb";
  41. };
  42. &portc {
  43. bank-name = "portc";
  44. };
  45. &watchdog0 {
  46. u-boot,dm-pre-reloc;
  47. };