x600.h 7.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2009, STMicroelectronics - All Rights Reserved
  4. * Author(s): Vipin Kumar, <vipin.kumar@st.com> for STMicroelectronics.
  5. *
  6. * Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de>
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. /*
  11. * High Level Configuration Options
  12. * (easy to change)
  13. */
  14. #define CONFIG_SPEAR600 /* SPEAr600 SoC */
  15. #define CONFIG_X600 /* on X600 board */
  16. #include <asm/arch/hardware.h>
  17. /* Timer, HZ specific defines */
  18. #define CONFIG_SYS_HZ_CLOCK 8300000
  19. #define CONFIG_SYS_FLASH_BASE 0xf8000000
  20. /* Reserve 8KiB for SPL */
  21. #define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */
  22. #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
  23. #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
  24. CONFIG_SYS_SPL_LEN)
  25. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  26. #define CONFIG_SYS_MONITOR_LEN 0x60000
  27. /* Serial Configuration (PL011) */
  28. #define CONFIG_SYS_SERIAL0 0xD0000000
  29. #define CONFIG_SYS_SERIAL1 0xD0080000
  30. #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \
  31. (void *)CONFIG_SYS_SERIAL1 }
  32. #define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
  33. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
  34. 57600, 115200 }
  35. #define CONFIG_SYS_LOADS_BAUD_CHANGE
  36. /* NOR FLASH config options */
  37. #define CONFIG_ST_SMI
  38. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  39. #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
  40. #define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE }
  41. #define CONFIG_SYS_MAX_FLASH_SECT 128
  42. #define CONFIG_SYS_FLASH_EMPTY_INFO
  43. #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
  44. #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
  45. /* NAND FLASH config options */
  46. #define CONFIG_NAND_FSMC
  47. #define CONFIG_SYS_NAND_SELF_INIT
  48. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  49. #define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE
  50. #define CONFIG_MTD_ECC_SOFT
  51. #define CONFIG_SYS_FSMC_NAND_8BIT
  52. #define CONFIG_SYS_NAND_ONFI_DETECTION
  53. #define CONFIG_NAND_ECC_BCH
  54. /* UBI/UBI config options */
  55. /* Ethernet config options */
  56. #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
  57. #define CONFIG_SPEAR_GPIO
  58. /* I2C config options */
  59. #define CONFIG_SYS_I2C
  60. #define CONFIG_SYS_I2C_BASE 0xD0200000
  61. #define CONFIG_SYS_I2C_SPEED 400000
  62. #define CONFIG_SYS_I2C_SLAVE 0x02
  63. #define CONFIG_I2C_CHIPADDRESS 0x50
  64. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  65. /* FPGA config options */
  66. #define CONFIG_FPGA_COUNT 1
  67. /* USB EHCI options */
  68. #define CONFIG_USB_EHCI_SPEAR
  69. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  70. /*
  71. * U-Boot Environment placing definitions.
  72. */
  73. /* Miscellaneous configurable options */
  74. #define CONFIG_BOOT_PARAMS_ADDR 0x00000100
  75. #define CONFIG_CMDLINE_TAG
  76. #define CONFIG_SETUP_MEMORY_TAGS
  77. #define CONFIG_SYS_MALLOC_LEN (8 << 20)
  78. #define CONFIG_SYS_LOAD_ADDR 0x00800000
  79. #define CONFIG_HOSTNAME "x600"
  80. #define CONFIG_UBI_PART ubi0
  81. #define CONFIG_UBIFS_VOLUME rootfs
  82. #define CONFIG_EXTRA_ENV_SETTINGS \
  83. "u-boot_addr=1000000\0" \
  84. "u-boot=" CONFIG_HOSTNAME "/u-boot.spr\0" \
  85. "load=tftp ${u-boot_addr} ${u-boot}\0" \
  86. "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
  87. " +${filesize};" \
  88. "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
  89. "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \
  90. " ${filesize};" \
  91. "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
  92. " +${filesize}\0" \
  93. "upd=run load update\0" \
  94. "ubifs=" CONFIG_HOSTNAME "/ubifs.img\0" \
  95. "part=" __stringify(CONFIG_UBI_PART) "\0" \
  96. "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \
  97. "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \
  98. "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \
  99. " ${filesize}\0" \
  100. "upd_ubifs=run load_ubifs update_ubifs\0" \
  101. "init_ubifs=nand erase.part ubi0;ubi part ${part};" \
  102. "ubi create ${vol} 4000000\0" \
  103. "netdev=eth0\0" \
  104. "rootpath=/opt/eldk-4.2/arm\0" \
  105. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  106. "nfsroot=${serverip}:${rootpath}\0" \
  107. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  108. "boot_part=0\0" \
  109. "altbootcmd=if test $boot_part -eq 0;then " \
  110. "echo Switching to partition 1!;" \
  111. "setenv boot_part 1;" \
  112. "else; " \
  113. "echo Switching to partition 0!;" \
  114. "setenv boot_part 0;" \
  115. "fi;" \
  116. "saveenv;boot\0" \
  117. "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \
  118. "root=ubi0:rootfs rootfstype=ubifs\0" \
  119. "kernel=" CONFIG_HOSTNAME "/uImage\0" \
  120. "kernel_fs=/boot/uImage \0" \
  121. "kernel_addr=1000000\0" \
  122. "dtb=" CONFIG_HOSTNAME "/" \
  123. CONFIG_HOSTNAME ".dtb\0" \
  124. "dtb_fs=/boot/" CONFIG_HOSTNAME ".dtb\0" \
  125. "dtb_addr=1800000\0" \
  126. "load_kernel=tftp ${kernel_addr} ${kernel}\0" \
  127. "load_dtb=tftp ${dtb_addr} ${dtb}\0" \
  128. "addip=setenv bootargs ${bootargs} " \
  129. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  130. ":${hostname}:${netdev}:off panic=1\0" \
  131. "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \
  132. "${baudrate}\0" \
  133. "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
  134. "net_nfs=run load_dtb load_kernel; " \
  135. "run nfsargs addip addcon addmtd addmisc;" \
  136. "bootm ${kernel_addr} - ${dtb_addr}\0" \
  137. "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
  138. "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
  139. "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \
  140. " addcon addmisc addmtd;" \
  141. "bootm ${kernel_addr} - ${dtb_addr}\0" \
  142. "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \
  143. "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \
  144. "ubifsload ${dtb_addr} ${dtb_fs};\0" \
  145. "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \
  146. "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \
  147. "bootcmd=run nand_ubifs\0" \
  148. "\0"
  149. /* Physical Memory Map */
  150. #define PHYS_SDRAM_1 0x00000000
  151. #define PHYS_SDRAM_1_MAXSIZE 0x40000000
  152. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  153. #define CONFIG_SRAM_BASE 0xd2800000
  154. /* Preserve the last 2 lwords for the boot-counter */
  155. #define CONFIG_SRAM_SIZE ((8 << 10) - 0x8)
  156. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SRAM_BASE
  157. #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SRAM_SIZE
  158. #define CONFIG_SYS_INIT_SP_OFFSET \
  159. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  160. #define CONFIG_SYS_INIT_SP_ADDR \
  161. (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  162. /*
  163. * SPL related defines
  164. */
  165. #define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00)
  166. #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear"
  167. /*
  168. * Please select/define only one of the following
  169. * Each definition corresponds to a supported DDR chip.
  170. * DDR configuration is based on the following selection
  171. */
  172. #define CONFIG_DDR_MT47H64M16 1
  173. #define CONFIG_DDR_MT47H32M16 0
  174. #define CONFIG_DDR_MT47H128M8 0
  175. /*
  176. * Synchronous/Asynchronous operation of DDR
  177. *
  178. * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
  179. * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
  180. * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation
  181. */
  182. #define CONFIG_DDR_2HCLK 1
  183. #define CONFIG_DDR_HCLK 0
  184. #define CONFIG_DDR_PLL2 0
  185. /*
  186. * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported
  187. * or not. Modify/Add to only these macros to define new boot types
  188. */
  189. #define USB_BOOT_SUPPORTED 0
  190. #define PCIE_BOOT_SUPPORTED 0
  191. #define SNOR_BOOT_SUPPORTED 1
  192. #define NAND_BOOT_SUPPORTED 1
  193. #define PNOR_BOOT_SUPPORTED 0
  194. #define TFTP_BOOT_SUPPORTED 0
  195. #define UART_BOOT_SUPPORTED 0
  196. #define SPI_BOOT_SUPPORTED 0
  197. #define I2C_BOOT_SUPPORTED 0
  198. #define MMC_BOOT_SUPPORTED 0
  199. #endif /* __CONFIG_H */